JPH1117547A - Digital-to-analog converter - Google Patents

Digital-to-analog converter

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Publication number
JPH1117547A
JPH1117547A JP16278597A JP16278597A JPH1117547A JP H1117547 A JPH1117547 A JP H1117547A JP 16278597 A JP16278597 A JP 16278597A JP 16278597 A JP16278597 A JP 16278597A JP H1117547 A JPH1117547 A JP H1117547A
Authority
JP
Japan
Prior art keywords
bits
constant current
conversion circuit
bit
digital signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16278597A
Other languages
Japanese (ja)
Inventor
Hiromi Arai
洋実 新井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP16278597A priority Critical patent/JPH1117547A/en
Publication of JPH1117547A publication Critical patent/JPH1117547A/en
Pending legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To obtain an accurate output even to the multibit input by preparing a 1st D/A conversion part which flows a constant current to a resistor ladder part of an R-2R system in response to the input bit and a 2nd D/A conversion part which flows plural constant currents after the conversion of bit number by defining the MSB side of the resistor ladder part as the load and obtaining the analog output from one of both ends of the load of the MSB side. SOLUTION: A 1st D/A conversion circuit 2 of an ordinary R-2R system consists of a resistor ladder 3 including the LSB through 6 bits, the bit switches 4A to 4F and the constant current sources 5A to 5F which flow a constant current I respectively. A 2nd D/A conversion circuit 6 consists of the bit switches 7A to 7C, the constant current sources 8A to 8C which flow a constant current 2I respectively and a bit converter 20. The converter 20 converts the input of higher two bits into the value of three bits, controls the switches 7A to 7C and adds together the currents 2I in sequence. As the numbers of bits in charge of both circuits 2 and 6 can be freely changed, the high conversion accuracy is secured.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、D/A変換器に関
するもので、特にビット数の多いデジタル信号入力に対
しても正確なアナログ出力が得られるIC化に適したD
/A変換器に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital-to-analog (D / A) converter, and more particularly to a digital-to-analog (D / A) converter suitable for use in an IC that can obtain an accurate analog output even for a digital signal input having a large number of bits.
/ A converter.

【0002】[0002]

【従来の技術】定電流源を利用したD/A変換器として
R−2R方式のラダー回路により構成される図2の如き
ものが考えられる。図2の入力端子(1)乃至(8)に
はデジタル信号が印加され、出力端子(9)にはアナロ
グ信号が発生する。入力端子(1)は最LSBとなり、
入力端子(8)は最MSBとなる。
2. Description of the Related Art As a D / A converter utilizing a constant current source, a D / A converter as shown in FIG. 2 constituted by an R-2R ladder circuit can be considered. A digital signal is applied to the input terminals (1) to (8) of FIG. 2, and an analog signal is generated at the output terminal (9). The input terminal (1) becomes the most LSB,
The input terminal (8) is the most significant bit.

【0003】入力端子(1)乃至(8)にデジタル信号
(0、0、0・・・0)が印加されると、定電流源(1
0)乃至(17)がオフとなり各抵抗には電流が流れな
い。この為、出力端子(9)には最大電圧である基準電
源Vrefが発生する。次に、入力端子(8)にデジタル
信号「1」が印加され、他の入力端子全てにデジタル信
号「0」が印加されると、定電流源(17)のみに電流
が流れる。すると、出力電圧は、Vref−R・I/2とな
る。
When a digital signal (0, 0, 0... 0) is applied to input terminals (1) to (8), a constant current source (1) is applied.
0) to (17) are turned off, and no current flows through each resistor. Therefore, a reference voltage Vref which is the maximum voltage is generated at the output terminal (9). Next, when the digital signal “1” is applied to the input terminal (8) and the digital signal “0” is applied to all other input terminals, current flows only to the constant current source (17). Then, the output voltage becomes Vref−R · I / 2.

【0004】但し、Iは定電流源(10)乃至(17)
の各々に流れる電流、Rは基準抵抗値とする。更に、定
電流源(16)のみに電流を流すと、出力電圧は、Vre
f−R・I/4となる。又、図3は重みづけされた抵抗を
直列接続して構成されたD/A変換器であり、これも定
電流源を利用している。各抵抗は、(1/2)のn乗
(nは2以上の自然数)で重みづけられている。図3
は、抵抗の構成が図2と異なるだけであり他の構成と動
作は図2と同様である。
Where I is a constant current source (10) to (17)
And R is a reference resistance value. Further, when a current flows only through the constant current source (16), the output voltage becomes Vre.
f−R · I / 4. FIG. 3 shows a D / A converter configured by connecting weighted resistors in series, which also uses a constant current source. Each resistance is weighted by (1/2) n (n is a natural number of 2 or more). FIG.
Is different from FIG. 2 only in the configuration of the resistor, and the other configurations and operations are the same as those in FIG.

【0005】図2及び図3のD/A変換器によれば、8
ビットのデジタル信号に応じた256通りのアナログ信
号が得られる。
According to the D / A converter shown in FIGS. 2 and 3, 8
256 types of analog signals corresponding to the bit digital signal are obtained.

【0006】[0006]

【発明が解決しようとする課題】しかしながら、図2及
び図3のD/A変換器は、一般に入力デジタル信号が7
ビット以上になるとその構成素子(例えばIC化されて
いる抵抗値、定電流源の電流値)のバラツキによりアナ
ログ出力電位が異常になる恐れがあった。バラツキがひ
どくなると前記アナログ出力電位は、入力ビットに応じ
て高くなるはずの電位が逆に低下してしまったり、入力
ビット信号を変化させても値が変わらなくなってしま
う。これは、デジタルのビット数が高くなるほど顕著と
なる。
However, the D / A converter shown in FIGS. 2 and 3 generally has an input digital signal of 7 bits.
If the number of bits is greater than or equal to the bit, the analog output potential may become abnormal due to the variation of the constituent elements (for example, the resistance value of the IC, the current value of the constant current source). When the variation becomes severe, the potential of the analog output potential, which should increase in accordance with the input bit, conversely decreases, and the value does not change even if the input bit signal is changed. This becomes more significant as the number of digital bits increases.

【0007】[0007]

【課題を解決するための手段】本発明は、上述の点に鑑
みなされたもので、R−2R方式の抵抗ラダー部と複数
ビットのデジタル信号に応じて定電流Iを前記抵抗ラダ
ー回路に供給する第1スイッチ部とを含む第1D/A変
換回路と、前記抵抗ラダー部の最MSB側を負荷として
複数ビットのデジタル信号に応じて複数の定電流2Iを
供給する第2スイッチ部を含む第2D/A変換回路とを
備え、前記抵抗ラダー部の最MSB側の負荷の一端から
アナログ出力を得るようにしたことを特徴とする。
SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and provides a resistor ladder section of an R-2R system and a constant current I to the resistor ladder circuit in accordance with a digital signal of a plurality of bits. A first D / A conversion circuit including a first switch unit for performing the operation, and a second switch unit that supplies a plurality of constant currents 2I in response to a plurality of bits of a digital signal using the most MSB side of the resistor ladder unit as a load. A 2D / A conversion circuit, wherein an analog output is obtained from one end of the load on the most MSB side of the resistor ladder section.

【0008】[0008]

【発明の実施の形態】図1は、本発明のD/A変換器を
示すもので、(1)は電源、(2)はR−2R方式の抵
抗ラダー部(3)と複数ビットのデジタル信号に応じて
オンオフする複数のスイッチ(4A)乃至(4F)を備
える第1スイッチ部(4)と該第1スイッチ部(4)の
各スイッチ(4A)乃至(4F)に応じて前記抵抗ラダ
ー部(3)に定電流Iを流す複数の定電流源(5A)乃
至(5F)とを含む第1D/A変換回路、(6)は複数
ビットのデジタル信号に応じてオンオフする複数のスイ
ッチ(7A)乃至(7C)を備える第2スイッチ部
(7)と該第2スイッチ部(7)の各スイッチ(7A)
乃至(7C)に応じて、前記抵抗ラダー部(3)の最M
SB側に定電流2Iを流す複数の定電流源(8A)乃至
(8C)とを含む第2D/A変換回路、(9)はアナロ
グ信号の出力端子である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a D / A converter according to the present invention. (1) is a power supply, (2) is an R-2R type resistor ladder section (3) and a multi-bit digital ladder section. A first switch unit (4) including a plurality of switches (4A) to (4F) that are turned on and off according to signals, and the resistance ladder according to each switch (4A) to (4F) of the first switch unit (4). A first D / A conversion circuit including a plurality of constant current sources (5A) to (5F) for flowing a constant current I to the section (3); and (6) a plurality of switches (ON / OFF) according to a plurality of bits of a digital signal. 7A) to (7C) and the respective switches (7A) of the second switch unit (7)
To (7C), the maximum M of the resistance ladder portion (3)
A second D / A conversion circuit including a plurality of constant current sources (8A) to (8C) for flowing a constant current 2I to the SB side, and (9) is an analog signal output terminal.

【0009】デジタル信号は、8ビットで印加される。
8ビットの内、LSB側の6ビットは単純に第1D/A
変換回路(2)のスイッチ(4A)乃至(4F)に印加
される。残りの2ビットは3ビットの値に変換されて第
2D/A変換回路(6)のスイッチ(7A)乃至(7
C)に印加される。第1D/A変換回路(2)の最MS
B側の抵抗Rと抵抗2Rとの接続点Aから左側(LSB
側)を見ると、これは図2の出力端子(9)から左側を
みたものと同じ回路構成となり、同様に動作する。
[0009] The digital signal is applied in 8 bits.
Of the 8 bits, the 6 bits on the LSB side are simply the first D / A
It is applied to the switches (4A) to (4F) of the conversion circuit (2). The remaining 2 bits are converted to 3-bit values, and the switches (7A) to (7A) of the second D / A conversion circuit (6) are converted.
C). Most MS of the first D / A conversion circuit (2)
The left side (LSB) from the connection point A between the resistor R on the B side and the resistor 2R.
2 has the same circuit configuration as the output terminal (9) shown in FIG. 2 on the left side, and operates similarly.

【0010】即ち、スイッチ(4F)のみを閉じて残り
の全てのスイッチを開いたとする。すると、出力電圧
は、Vref−R・Iとなる。更に、定電流源(5E)の
みに電流を流すと、出力電圧は、Vref−R・I/2とな
る。このため、スイッチ(4A)乃至(4F)の開閉に
より6ビット分をR−2R方式でD/A変換できる。
That is, it is assumed that only the switch (4F) is closed and all the remaining switches are opened. Then, the output voltage becomes Vref-RI. Further, when a current is passed only to the constant current source (5E), the output voltage becomes Vref-RI / 2. Therefore, D / A conversion of 6 bits can be performed by the R-2R method by opening and closing the switches (4A) to (4F).

【0011】次に図1のD/A変換器の上位2ビットに
ついて説明する。上位2ビットは、誤差を少なくするた
めに電流加算型のD/A変換を行うようにしている。定
電流源(8A)乃至(8C)は、各々電流2Iを流す。
又、スイッチ(7A)から点A側を見たインピーダンス
は、Rである。このため、スイッチ(7A)を閉じ、そ
れ以外のスイッチを全て開いたとすると、出力電圧は、
Vref−2R・Iとなりスイッチ(4F)側に比べて1
ビット分MAB側になっていることが解る。
Next, the upper two bits of the D / A converter of FIG. 1 will be described. The upper two bits are subjected to current addition type D / A conversion in order to reduce errors. Each of the constant current sources (8A) to (8C) passes a current 2I.
The impedance when the point A is viewed from the switch (7A) is R. Therefore, assuming that the switch (7A) is closed and all other switches are opened, the output voltage becomes
Vref-2R · I, which is 1 compared to the switch (4F) side
It can be seen that the bit is on the MAB side.

【0012】定電流源(8A)乃至(8C)は、各々電
流2Iを流し電流を順次加算していくタイプである。こ
のため、抵抗値や電流値の誤差を小さくできる。IC化
回路の場合、抵抗値や電流値はできるだけ等しい値のも
のを使用すれば抵抗や電流の値同士の誤差が少なくて済
む。このため、全体の誤差が低減される。図1では等し
い電流源を使用するので2ビットに対応する状態をつく
るのに3ビット分のスイッチ及び電流源を必要とする。
そこで、ビット数変換器(20)を設け2ビットの入力
信号に応じて3ビットの出力信号を発生させている。そ
の様子を図4に示す。図4の左側2ビットは、入力信号
を示し、中央3ビットは出力信号を示す。該出力信号の
「0」はスイッチが開いた状態を示し、出力信号の
「1」はスイッチが閉じた状態を示す。今、スイッチ
(4A)乃至(4F)が全て開いているとすると、その
時の出力電圧は図4に示す「出力電圧」となる。即ち、
図4の出力ビット「100」の時はスイッチ(7A)乃
至(7C)の内、スイッチ(7A)のみが閉じる。その
為、出力電圧はVref−2R・Iとなる。図4は2ビッ
トを3ビットに変換する場合を示しているがこれ以外も
できる。例えば、8ビットの内上位3ビットを電流加算
型としてD/A変換器を構成してもよい。この場合には
スイッチと電流源が7ビット分必要となる。この一般式
はnビット分が必要な場合には2のn乗マイナス1で表
される。
The constant current sources (8A) to (8C) are of a type in which a current 2I flows and the currents are sequentially added. Therefore, errors in the resistance value and the current value can be reduced. In the case of an IC circuit, if the resistance and the current have the same value as much as possible, errors between the resistance and the current can be reduced. Therefore, the overall error is reduced. In FIG. 1, since equal current sources are used, a 3-bit switch and a current source are required to create a state corresponding to 2 bits.
Therefore, a bit number converter (20) is provided to generate a 3-bit output signal according to a 2-bit input signal. This is shown in FIG. The left two bits in FIG. 4 indicate an input signal, and the central three bits indicate an output signal. "0" of the output signal indicates that the switch is open, and "1" of the output signal indicates that the switch is closed. Assuming that the switches (4A) to (4F) are all open, the output voltage at that time becomes the “output voltage” shown in FIG. That is,
When the output bit is "100" in FIG. 4, only the switch (7A) is closed among the switches (7A) to (7C). Therefore, the output voltage becomes Vref−2R · I. FIG. 4 shows a case where 2 bits are converted into 3 bits, but other methods are also possible. For example, the D / A converter may be configured by using the upper 3 bits of the 8 bits as a current addition type. In this case, a switch and a current source for 7 bits are required. This general formula is expressed by 2 to the power of n minus 1 when n bits are required.

【0013】図1の説明では第2D/A変換回路(6)
をMSB側に設ける場合について説明したが、これはL
SB側に設けてもよい。下位2ビットの場合には電流値
を2Iに変えてI/4とする。下位3ビットの場合には
電流値をI/8とする。即ち、下位nビットについてD/
A変換を行うにはI/(2のn乗)となる。LSB側に
設ける場合も図1の場合と同様にビット数が高く(7以
上)なっても正確なアナログ出力信号が得られる。
In the description of FIG. 1, the second D / A conversion circuit (6)
Has been described on the MSB side, but this is
It may be provided on the SB side. In the case of the lower 2 bits, the current value is changed to 2I and set to I / 4. In the case of the lower three bits, the current value is set to I / 8. That is, D /
To perform A conversion, I / (2 n). Even in the case where it is provided on the LSB side, an accurate analog output signal can be obtained even if the number of bits is high (7 or more) as in the case of FIG.

【0014】[0014]

【発明の効果】以上述べた如く、本発明によれば、ビッ
ト数の多いデジタル信号入力に対しても正確なアナログ
出力が得られるIC化に適したD/A変換器が提供でき
る。特に、本発明によれば、第1のD/A変換回路と第
2のD/A変換回路が担当するビット数が自由に選べる
ので精度と素子数増加を鑑みて所望のD/A変換器が得
られる。
As described above, according to the present invention, it is possible to provide a D / A converter suitable for integration into an IC that can obtain an accurate analog output even for a digital signal input having a large number of bits. In particular, according to the present invention, the number of bits assigned to the first D / A conversion circuit and the second D / A conversion circuit can be freely selected. Is obtained.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明のD/A変換器を示す回路図である。FIG. 1 is a circuit diagram showing a D / A converter according to the present invention.

【図2】従来のD/A変換器を示す回路図である。FIG. 2 is a circuit diagram showing a conventional D / A converter.

【図3】従来のD/A変換器を示す回路図である。FIG. 3 is a circuit diagram showing a conventional D / A converter.

【図4】図1の説明に供する入力信号・出力信号の対応
図である。
FIG. 4 is a correspondence diagram of an input signal and an output signal used for explaining FIG. 1;

【符号の説明】[Explanation of symbols]

(2) 第1D/A変換回路 (6) 第2D/A変換回路 (9) 出力端子 (2) First D / A conversion circuit (6) Second D / A conversion circuit (9) Output terminal

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 R−2R方式の抵抗ラダー部と複数ビッ
トのデジタル信号に応じて定電流Iを前記抵抗ラダー部
の各抵抗に供給する第1スイッチ部とを含む第1D/A
変換回路と、 前記抵抗ラダー部の最MSB側を負荷として複数ビット
のデジタル信号に応じて複数の定電流2Iを供給する第
2スイッチ部を含む第2D/A変換回路とを備え、前記
抵抗ラダー部の最MSB側の負荷の一端からアナログ出
力を得るようにしたことを特徴とするD/A変換器。
1. A first D / A including an R-2R type resistor ladder unit and a first switch unit that supplies a constant current I to each resistor of the resistor ladder unit according to a digital signal of a plurality of bits.
And a second D / A conversion circuit including a second switch unit that supplies a plurality of constant currents 2I in accordance with a digital signal of a plurality of bits by using a most significant bit of the resistance ladder unit as a load. A D / A converter characterized in that an analog output is obtained from one end of a load on the most MSB side of the section.
【請求項2】 R−2R方式の抵抗ラダー部と複数ビッ
トのデジタル信号に応じてオンオフする複数のスイッチ
を備える第1スイッチ部と該第1スイッチ部の各スイッ
チに応じて前記抵抗ラダー部に定電流Iを流す複数の定
電流源とを含む第1D/A変換回路と、 複数ビットのデジタル信号に応じてオンオフする複数の
スイッチを備える第2スイッチ部と該第2スイッチ部の
各スイッチに応じて、前記抵抗ラダー部の最MSB側に
定電流2Iを流す複数の定電流源とを含む第2D/A変
換回路とを備え、前記抵抗ラダー部の最MSB側の負荷
の一端からアナログ出力を得るようにしたことを特徴と
するD/A変換器。
2. A first switch unit comprising an R-2R type resistor ladder unit and a plurality of switches which are turned on / off in response to a digital signal of a plurality of bits, and the resistor ladder unit according to each switch of the first switch unit. A first D / A conversion circuit including a plurality of constant current sources for supplying a constant current I; a second switch unit including a plurality of switches that are turned on and off in accordance with a digital signal of a plurality of bits; and each switch of the second switch unit. A second D / A conversion circuit including a plurality of constant current sources for supplying a constant current 2I to the most MSB side of the resistance ladder section, and an analog output from one end of the most MSB side load of the resistance ladder section. A D / A converter characterized by:
【請求項3】 R−2R方式の抵抗ラダー部と複数ビッ
トのデジタル信号に応じて定電流Iを前記抵抗ラダー回
路に供給する第1スイッチ部とを含む第1D/A変換回
路と、 前記抵抗ラダー部の最LSB側を負荷として複数ビット
のデジタル信号に応じて複数の定電流:I/(2のn
乗)(但し、nは第2D/A変換回路が出力するビット
数)を供給する第2スイッチ部を含む第2D/A変換回
路とを備え、前記抵抗ラダー部の最MSB側の負荷の一
端からアナログ出力を得るようにしたことを特徴とする
D/A変換器。
3. A first D / A conversion circuit including an R-2R type resistor ladder unit and a first switch unit that supplies a constant current I to the resistor ladder circuit in accordance with a digital signal of a plurality of bits; A plurality of constant currents: I / (2 n
And a second D / A conversion circuit including a second switch unit for supplying the power to the power supply (where n is the number of bits output by the second D / A conversion circuit). A D / A converter characterized in that an analog output is obtained from a digital signal.
JP16278597A 1997-06-19 1997-06-19 Digital-to-analog converter Pending JPH1117547A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16278597A JPH1117547A (en) 1997-06-19 1997-06-19 Digital-to-analog converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16278597A JPH1117547A (en) 1997-06-19 1997-06-19 Digital-to-analog converter

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JPH1117547A true JPH1117547A (en) 1999-01-22

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006032592A1 (en) 2004-09-20 2006-03-30 Analog Devices, Inc. Digital-to-analog converter structures
JP2006311001A (en) * 2005-04-27 2006-11-09 Hitachi Ltd Semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006032592A1 (en) 2004-09-20 2006-03-30 Analog Devices, Inc. Digital-to-analog converter structures
JP2008514065A (en) * 2004-09-20 2008-05-01 アナログ・デバイシズ・インコーポレーテッド Digital / analog converter
JP2006311001A (en) * 2005-04-27 2006-11-09 Hitachi Ltd Semiconductor device
JP4670458B2 (en) * 2005-04-27 2011-04-13 株式会社日立製作所 Semiconductor device

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