JPH11175437A - Radio lan controller and radio lan control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a buffer function and DMA function for absorbing the difference in transferring speed between interfaces, and a communication controller function for operating the control of a transmitting and receiving function and state communication to a CPU by using radio LAN interface control information. SOLUTION: The difference in the transferring speed between a CPU 16 and a radio LAN interface 19 is absorbed by FIFO 12 and 13, and a transmitting and receiving buffer is separated so that high speed data transfer can be realized. Then, the status monitor of the radio LAN interface 19, the reception of interruption communication from the radio LAN interface 19, proper control to the radio LAN interface 19, state communication to the CPU 16, and data transfer with a memory 17 can be attained by a control part 14. Thus, the mutual interface difference among the CPU 16, memory 17, and radio LAN interface 19 can be absorbed, and data transmission and reception between the CPU 16 and the radio LAN interface 19, and between the memory 17 and the radio LAN interface 19 can be attained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an arithmetic processing unit such as a CPU of a computer system and a wireless LAN (L).
BACKGROUND OF THE INVENTION A communication controller device for transmitting and receiving data to and from an interface of a wireless local area network (hereinafter referred to as a wireless LAN interface) has a buffer function for absorbing a difference in transfer speed between the interfaces and a DMA (Direct Memory Acces).
s) The present invention relates to a wireless LAN control device and a wireless LAN control method, characterized by controlling a transmission / reception function and notifying a status to a CPU using control information of a wireless LAN interface.

[0002]

2. Description of the Related Art Conventionally, in a communication control circuit,
Since the data transfer rate on the wireless LAN interface side is lower than the data transfer rate on the CPU side, the throughput of the bus on the CPU side is affected by the throughput of the wireless LAN interface. In order to improve this, simply mounting a buffer for absorbing the difference in transfer speed has little effect of reducing the load on the CPU. Further, the communication controller circuit itself does not have a function of determining the state of the wireless LAN interface, and relies on the processing of the CPU.

[0003]

The difference between the CPU and the memory capable of storing software and the interface having the wireless LAN function is absorbed by the CPU and the wireless LAN interface and between the memory and the wireless LAN interface. In a general-purpose communication controller LSI capable of transmitting and receiving data, the following has been eagerly desired.

(1) The difference in transfer speed between the CPU and the wireless LAN interface is absorbed by having an internal buffer, and the transmission and reception buffers are separated to realize high-speed data transfer. Upon monitoring the status of the interface, receiving notification of an interrupt from the wireless LAN interface, and the like, appropriate control to the wireless LAN interface, notification of the state to the CPU, and data transfer to the memory are performed. (2) By monitoring the state of wireless communication of the wireless LAN interface (for example, the strength of radio waves),
It notifies the CPU of the control of data transmission / reception to the wireless LAN interface and transfers data to / from the memory.

(3) The optimum data transfer amount is controlled by monitoring the status of a plurality of built-in buffers and notifying the CPU of the status.

Accordingly, the present invention has been made in view of the above circumstances, and has been developed in consideration of a CPU of a computer system and a wireless LA.
In a communication controller device for transmitting and receiving data to and from the N interface, a buffer function and a DMA function for absorbing a difference in transfer speed between the interfaces, a control of a transmitting and receiving function using control information of a wireless LAN interface, and a state notification to a CPU. It is an object of the present invention to provide a wireless LAN control device and a wireless LAN control method.

[0007]

The present invention has the following features to attain the above object.

That is, the wireless LAN control device of the present invention uses a wireless LAN interface via a wireless LAN interface.
L of the computer system which performs data communication by using
In the AN control device, a DMA controller that sets and controls direct memory access transfer of data transmitted and received by the computer system by the computer system, interface means for transmitting and receiving data to and from the wireless LAN interface, and a CPU of the computer system. Transmission buffer means for storing transmission data from the DMA controller to absorb a difference in transfer rate of the bus of the wireless LAN interface, and absorption of a difference in transfer rate of the bus of the wireless LAN interface to the CPU of the computer system. Receiving means for storing data received from the interface means,
An interface and control means for monitoring the states of the DMA controller to determine whether data transmission / reception is possible and controlling data transmission / reception based on the result of the determination. The control means performs the determination when transmitting data. When data transmission is possible based on the result, the transmission data is read from the memory of the computer system by the DMA controller and stored in the transmission buffer means, and the stored transmission data is transferred to the wireless LAN interface by the interface means. When receiving data, if the data can be received based on the determination result, the received data is stored from the wireless LAN interface into the receiving buffer means by the interface means, and the stored received data is transmitted to the DMA controller by the DMA controller. Characterized by a control to be transferred to Yutashisutemu.

According to this configuration, the difference in transfer speed between the CPU and the wireless LAN interface is absorbed by having an internal buffer, and the speed of data transfer is increased by separating the transmission and reception buffers. It can monitor the status of the wireless LAN interface, receive an interrupt notification from the wireless LAN interface, and perform appropriate control to the wireless LAN interface, notification of the state to the CPU, and data transfer with the memory. The interface between a memory capable of storing software and an interface having a wireless LAN function is absorbed, and data can be transmitted and received between the CPU and the wireless LAN interface and between the memory and the wireless LAN interface.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a diagram showing a schematic configuration of an example of an embodiment of the present invention.

In FIG. 1, a communication controller 10 comprises:
DMA controller 1
1 and FIFOs 12 and 13, a control unit 14, and an IF 15 are provided internally. DMA (Direct Memory Ac)
cess) controller 11 is a communication controller 10
This is a circuit for controlling the DMA transfer in the inside. FIF
O12 and O13 are FIFOs (or buffers) for transmission / reception.
5 is provided. Here, the FIFO 12 is a transmission channel, and the FIFO 13 is a reception channel.

The control unit 14 is provided between the DMA controller 11 and the IF 15, and controls the wireless LAN (Local).
(Area Network) is a control circuit for controlling transfer to the interface 19. Then, the wireless LAN interface 19 of the interface 15 and D
The state of the MA controller 11 is controlled. The interface (IF) 15 controls the wireless LA under the control of the control unit 14.
This is a circuit for performing data transfer with the N interface 19.

As the interface itself between the communication controller 10 and the wireless LAN interface, general bus specifications (for example, ISA bus, PCMCIA, etc.) are often used.

The CPU 16 performs arithmetic processing and various controls of the system, and the memory 17 is a system memory. The CPU 16, the memory 17, and the communication controller 10 are connected to the bus 18. Bus 18 is a CP
A system bus for transferring data between the U16, the memory 17, the communication controller 10, and other system resources.

The wireless LAN interface 19 is the main body of the wireless LAN interface, and has an interface capable of transferring data with the interface 15.

Referring to FIG. 1, the data transfer of the communication controller will be described.

In the system shown in FIG.
In order to transmit / receive data to / from N, the CPU 16 sets DMA transfer to the DMA controller 11 in accordance with an execution program command such as firmware or software.

Here, the case of data transmission from the memory 17 to the wireless LAN interface 19 will be described.

The control unit 14 monitors whether the wireless LAN interface 19 can transmit. The control unit 14 performs control to read the state of the wireless LAN interface 19 into the interface 15 at regular intervals (the wireless LAN interface 19 may interrupt the state change to notify the state). Also, the DMA controller 11
Also recognizes whether the transmission preparation is completed.

The transfer control of data transmission by the control unit 14 will be described with reference to the flowchart shown in FIG.

The control unit 14 first determines whether the wireless LAN interface 19 is in a transferable state and whether the DMA controller 11 is ready for transmission (step A1).

Wireless LAN interface 19 and DMA
If the controller 11 is not ready (No in step A1), the process is returned to determine again whether the preparation is completed.

Wireless LAN Interface 19 and DMA
When the controller 11 is ready (step A
1), the control unit 14 controls the DMA controller 11
Then, a transmission data transfer start command is issued to the wireless LAN interface 19 (step A2).

The transmission data is read from the memory 17 via the bus 18 by the DMA controller 11,
Stored in the FIFO 12. The interface 15
The data is extracted from the FIFO 12 and output to the wireless LAN interface 19. Then, the wireless LAN interface 19 transmits the transmission data.

Subsequently, an error during transfer is detected (step A3). If an error during transfer is detected (Yes in step A3), the process is returned to continue the transfer.

If no error is detected during the transfer (No in step A3), when the transfer is completed, the controller 1
4 outputs a transfer end command to the wireless LAN interface 19. The DMA controller 11 has a CPU
16 is notified of the transfer completion (step A4).

Next, the case of receiving data from the wireless LAN interface 19 to the memory 17 will be described. In this case, as in the case of transmission, the CPU 16
A transfer setting is performed.

The wireless LAN interface 19 notifies the controller 14 of a request to transfer received data to the controller 14 by interruption (or a periodic wireless LAN by the controller 14).
The notification can be made by monitoring the interface 19).

The control of data reception by the control unit 14 is shown in FIG.
This will be described with reference to the flowchart of FIG. First, wireless LA
It is determined whether the N interface 19 is in a transferable state and whether the DMA controller 11 is ready for transmission (step A1). If the wireless LAN interface 19 and the DMA controller 11 are not ready (No in step A1), the process is returned to determine again whether the preparation is completed.

Wireless LAN Interface 19 and DMA
When the controller 11 is ready (step A
(Yes of 1), the control unit 14 issues a transfer start command of the received data to the DMA controller 11 and the wireless LAN interface 19 (step A2).

The received data is read from the wireless LAN interface 19 via the interface 15 and stored in the FIFO 13. DMA controller 1
1 retrieves the received data from the FIFO 13 and
8 to the memory 17. An error during transfer is detected (step A3), and if an error during transfer is detected (Yes in step A3), the process is returned to continue the transfer.

If no error is detected during the transfer (No in step A3), the controller 1
4 outputs a transfer end command to the wireless LAN interface 19. The DMA controller 11 has a CPU
16 is notified of the transfer completion (step A4).

(Second Embodiment) Hereinafter, a second embodiment will be described. The schematic configuration is the same as that of the first embodiment, and FIG. 1 is referred for the description.

According to the second embodiment, the control unit 14
The state of the AN interface 19 is detected, and transfer control is performed based on the state. The flow of this processing will be described with reference to the flowchart of FIG.

It is assumed that the wireless LAN interface 19 has a wireless transfer state (for example, a change in transfer speed) as internal information.

The control unit 14 monitors the internal information at predetermined intervals (step B1), and notifies the CPU 16 of the monitoring result (B2). The CPU 16 determines whether there is a change in the transfer state of the wireless LAN based on the notified internal information (in this case, determines whether there is a change in the transfer rate of the wireless LAN) (step B3).

If there is no change in the transfer speed (No in step B3), the process ends. On the other hand, if the transfer speed has changed (Yes in step B3), the CPU 16
Controls the transfer speed to an optimum speed according to a change in the transfer speed of the wireless LAN. Alternatively, it is a matter of course that transfer with high accuracy (such as transfer with enhanced error detection information) may be performed.

(Third Embodiment) A third embodiment will be described below. The schematic configuration is the same as that of the first embodiment, and FIG. 1 is referred for the description.

In the third embodiment, the control unit 14
The status of the FOs (or buffers) 12 and 13 is monitored, and transfer control is performed based on the status. The flow of this process will be described with reference to FIGS.

First, the flow of processing for data transmission will be described with reference to FIG. The transmission data is buffered in the FIFO 12. Normal interface 15 is F
The speed at which data is retrieved from the
The speed at which the controller 11 reads data from the memory 17 is faster.

However, if the bus 18 is congested for some reason and the transfer speed of the interface 15 from the memory 17 to the FIFO 12 is lower than the transfer speed required for the wireless LAN interface 19, the wireless LAN interface 19 Means that data underrun occurred and data was not transferred correctly.

The state of the FIFO 12 is controlled by the control unit 1
4 monitors at predetermined intervals (step C1), and notifies the CPU 16 of the monitoring result (step C2). And
The CPU 16 determines whether there is a possibility of occurrence of the underrun as described above based on the monitoring result (step C3).

If there is no possibility of occurrence of an underrun (no step C3), the process ends. On the other hand, when there is a possibility that an underrun may occur (there is a step C3), the CPU 16 changes the packet size to be transferred (step C4) and performs the transfer without the occurrence of the underrun.

The processing flow in the case of data reception will be described with reference to FIG.

In the FIFO 13, if the data transfer rate from the wireless LAN interface 19 becomes faster than the transfer rate from the FIFO 13 to the memory 17, overrun may occur.

The state of the FIFO 13 is determined by the controller 1
4 monitors at predetermined intervals (step D1) and notifies the CPU 16 of the monitoring result (step D2).

The CPU 16 determines whether there is a possibility of occurrence of the overrun as described above based on the monitoring result (step D3).

If there is no possibility of occurrence of overrun (no step D3), the process ends.

When there is a possibility that an underrun may occur (step D3), the CPU 16 reduces the number of packets to be transferred at one time and increases the number of DMA transfers (step D4), thereby causing the occurrence of overrun. Not transfer can be performed.

[0051]

As described above in detail, according to the present invention, C
By reducing the load on the PU and reducing the occupancy of the system bus, it is possible to suppress a decrease in the throughput of the entire system due to data transfer with the wireless LAN interface, and to improve the performance of the system.

[Brief description of the drawings]

FIG. 1 is a diagram showing a schematic configuration of a first embodiment of the present invention.

FIG. 2 is a flowchart showing a processing operation according to the embodiment;

FIG. 3 is a flowchart showing a processing operation according to a second embodiment of the present invention.

FIG. 4 is a flowchart showing a processing operation in the case of data transmission according to the embodiment;

FIG. 5 is a flowchart showing a processing operation in the case of data reception according to the third embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Communication controller 11 ... DMA controller 12 ... FIFO 13 ... FIFO 14 ... Control part 15 ... Interface 16 ... CPU 17 ... Memory 18 ... Bus 19 ... Wireless LAN interface

Claims (8)

[Claims] 1. A wireless LAN control device for a computer system that performs data communication by wireless LAN via a wireless LAN interface, wherein a DMA controller that sets and controls direct memory access transfer of data transmitted and received by the computer system. Interface means for transmitting and receiving data to and from the wireless LAN interface; and a transmission buffer for storing transmission data from the DMA controller for absorbing a difference in transfer speed between a CPU of the computer system and a bus of the wireless LAN interface. Means for receiving data from the interface means in order to absorb a difference in transfer rate between the CPU of the computer system and the bus of the wireless LAN interface. Receiving buffer means for storing data, and control means for monitoring the states of the wireless LAN interface and the DMA controller to determine the possibility of data transmission / reception, and controlling data transmission / reception based on the determination result. The control means reads the transmission data from the memory of the computer system by the DMA controller and stores the transmission data in the transmission buffer means when the data can be transmitted based on the determination result when transmitting the data, and stores the stored transmission data in the interface means When data can be received based on the determination result when receiving data, the received data is stored from the wireless LAN interface into the reception buffer means by the interface means, and Day The above DMA
A wireless LAN control device, wherein a controller controls transfer to the computer system. 2. The wireless LAN according to claim 1, wherein said control means determines the possibility of data transmission / reception based on a notification of a state change from said wireless LAN interface.
AN control device. 3. The wireless LAN interface has information on a transfer status of wireless data such as a transfer speed. The control means monitors the information at a predetermined interval and notifies the computer system of the information. 3. The wireless LAN control device according to claim 1, wherein a data transfer rate is controlled based on the notified information. 4. The control means monitors the states of the transmission buffer means and the reception buffer means, and notifies the computer system of a result of the monitoring, and the computer system based on the notified monitoring result. 4. The wireless LAN control device according to claim 1, wherein the amount of data transferred is controlled. 5. A wireless LAN control method for a computer system that performs data communication by wireless LAN via a wireless LAN interface, wherein the DMA controller sets and controls direct memory access transfer of data transmitted and received by the computer system. When transmitting data, the status of the wireless LAN interface and the DMA controller is monitored to determine the possibility of data transmission. If data transmission is possible based on the determination result, the DM
A controller stores transmission data read from the memory of the computer system to absorb a difference in transfer speed between the CPU of the computer system and the bus of the wireless LAN interface, and transfers the stored transmission data to the wireless LAN interface. When receiving data, the status of the wireless LAN interface and the DMA controller are monitored to determine the possibility of receiving data. If data can be received based on the result of the determination, the data is received from the wireless LAN interface. The transferred received data is stored to absorb a difference in transfer speed between the CPU of the computer system and the bus of the wireless LAN interface, and the stored received data is transferred to the computer system by the DMA controller. A wireless LAN control method comprising controlling. 6. The wireless LAN control method according to claim 5, wherein the possibility of data transmission / reception is determined based on the notification of the state change from the wireless LAN interface. 7. The wireless LAN interface has information on a transfer status of wireless data such as a transfer speed.
7. The wireless communication system according to claim 5, wherein the information is monitored at predetermined intervals and notified to the computer system, and the computer system controls a data transfer rate based on the notified information. LAN control method. 8. A storage state of data at the time of data transmission / reception is monitored, a result of the monitoring is notified to the computer system, and the computer system controls a data transfer amount based on the notified monitoring result. The wireless LAN control method according to claim 5, 6 or 7, wherein: