JPH11174122A - Method for boundary scan test - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enlarge a boundary scan test range to devices non-corresponding to a boundary scan. SOLUTION: Semiconductor devices 12-1 to 12-n capable of scan test and a semiconductor device 14 incapable of scan test are mounted to a substrate 11 to be tested which connects between a semiconductor device 13 capable of scan test and the semiconductor device 14 incapable of scan test. A connection line between the semiconductor device 13 capable of scan test and the semiconductor device 14 incapable of scan test is tested in a boundary scan method at the substrate 11 to be tested. In this case, a test access port 18 of the semiconductor device 13 capable of scan test is controlled, thereby feeding test pattern data to the semiconductor device 14 incapable of scan test, and at the same time taking a test pattern from the scan semiconductor device 14 incapable of scan test into the semiconductor device 13 capable of scan test to carry out the boundary scan.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a boundary scan test method effective for an interconnect test and a cluster test between semiconductor devices on a substrate on which a plurality of semiconductor devices are mounted.

[0002]

2. Description of the Related Art Conventionally, on a substrate on which a semiconductor device having cells for boundary scan (registers holding data for boundary scan test) is mounted,
An interconnect test and a cluster test are performed on a connection line (net) connecting semiconductor devices having cells for boundary scan by a boundary scan method.

FIG. 9 shows a printed circuit board (PC) on which a semiconductor device having cells for boundary scan is mounted.
B) is shown. A plurality of semiconductor devices 2a to 2c corresponding to the boundary scan are fitted on the PCB 1. Semiconductor devices 2a to 2 compatible with boundary scan
c has a core circuit 3 having an original function built therein, and corresponds to each input / output pin 4 on a line connecting the input / output end of the core circuit 3 and the input / output pin 4 of the device itself. Thus, a plurality of registers 5 are provided.

An instruction is set from a boundary scan controller 6 connected to each of the semiconductor devices 2a to 2c to an instruction register 7 in the semiconductor device 2a to 2c, and the internal controller 8 of the semiconductor device 2a to 2c follows the instruction. Test data is set in each register 5.

For example, when testing the net 10 connecting the semiconductor devices 2a and 2b, an instruction is set in an instruction register 7a of the semiconductor device 2a, and the instruction corresponding to the input / output pins of the net 10 is set according to the instruction. The test data is set in each of the registered registers. On the other hand, an instruction is set in the instruction register 7b of the semiconductor device 2b, and the internal controller 8b fetches the test data from the register of the semiconductor device 2a and stores it in the corresponding register of the semiconductor device 2b. The test data held in the register of the semiconductor device 2b is written to the transfer register 9b and transferred to the boundary scan controller 6. By checking the test data taken into the boundary scan controller 6, it can be determined whether the net 10 connecting the semiconductor devices 2a and 2b is normal.

Since a plurality of semiconductor devices 2a to 2c mounted on the PCB 1 form nets according to circuit functions, an interconnect test or a cluster test of each net is sequentially executed under the control of the boundary scan controller 6. Then, the connection between the semiconductor devices 2a to 2c can be tested.

[0007]

However, since the above-described boundary scan test is limited to a net connecting semiconductor devices having cells for boundary scan, even if the semiconductor device is mounted on the PCB 1, the boundary scan test is performed. The nets connecting to non-compliant (no boundary scan cells) devices had to be tested differently.

The present invention has been made in view of the above situation, and can be incorporated in a part of a scan chain even if the net is connected to a device that does not support boundary scan. An object of the present invention is to provide a boundary scan test method and apparatus capable of expanding a test area to a corresponding device.

[0009]

In order to achieve the above object, the present invention takes the following measures. According to the present invention, a scan-compatible semiconductor device including a cell for boundary scan and a non-scan-compatible semiconductor device not supporting boundary scan are mounted, and the scan-compatible semiconductor device and the non-scan-compatible semiconductor device are mounted. A method of testing a connection line between the scan-compatible semiconductor device and the non-scan-compatible semiconductor device by a boundary scan method on a substrate under test electrically connected between the scan-compatible semiconductor devices. Controlling a test access port of the device to give test pattern data to the scan-incompatible semiconductor device, and output a predetermined output pattern from the scan-incompatible semiconductor device to the test pattern itself or the test pattern; Connection la Uptake to the scan corresponding semiconductor device through emissions, then testing the connection line by executing a boundary scan of the scan corresponding semiconductor device.

[0010] Even in a non-scan-compatible semiconductor device, it is possible to write test pattern data and to extract an output pattern predetermined for the test pattern itself or the test pattern. If the test pattern itself or the output pattern taken into the scan-compatible semiconductor device is collected and checked by the boundary scan, as a result, the connection line between the scan-compatible semiconductor device and the non-scan-compatible semiconductor device is checked.

The present invention relates to a boundary scan of a plurality of scan-compatible semiconductor devices mounted on a substrate under test and a boundary of a single scan-compatible semiconductor device connected via a connection line to the non-scan-compatible semiconductor device. Scan and scan control by controlling separate test access ports, and a test pattern or an output pattern taken into the scan-compatible semiconductor device from the non-scan-compatible semiconductor device by a boundary scan of the entire scan-compatible semiconductor device. Collect as test result information when a device is targeted.

According to the present invention, a scan-compatible semiconductor device provided with a boundary scan cell and a non-scan-compatible semiconductor device not supporting the boundary scan are mounted, and the scan-compatible semiconductor device and the scan-non-compliant semiconductor device are mounted. A method of testing a connection line between the scan-capable semiconductor device and the non-scan-capable semiconductor device by a boundary scan method on a substrate under test electrically connected to a device via a connection line, Controlling the scan-compatible semiconductor device from a controller that performs a boundary scan of the scan-compatible semiconductor device, and applying test pattern data to the non-scan-compatible semiconductor device, and the test pattern itself or the test pattern from the non-scan-compatible semiconductor device. An output pattern that is predetermined for serial test pattern uptake to the scan corresponding semiconductor device through said connection line, then testing the connection line by executing a boundary scan of the scan corresponding semiconductor device.

According to the present invention, a boundary scan of a plurality of scan-compatible semiconductor devices mounted on a substrate under test is executed by controlling a test access port, and a scan is performed from a scan-incompatible semiconductor device by control of the controller. The test pattern or the output pattern is fetched into a corresponding semiconductor device, and the test pattern or the output pattern is collected as test result information when the scan-compatible semiconductor device is targeted by a boundary scan of the entire scan-compatible semiconductor device.

[0014]

Embodiments of the present invention will be described below. (First Embodiment) FIG. 1 shows a first embodiment of the present invention. The semiconductor devices mounted on the PCB under test 11 include a plurality of semiconductor devices 12-1 to 12-n that support boundary scan (including the memory control device 13) and a memory control device 13 that does not support boundary scan. And a memory 14 whose writing / reading is controlled from the memory. Each of the semiconductor devices 12-1 to 12-n corresponding to the boundary scan forms a main boundary scan chain (main scan chain).

The control CPU 15 generates a control code to test each net connecting the semiconductor devices 12-1 to 12-n and the memory 14 not supporting boundary scan and supplies the control code to the boundary scan controller 16. The boundary scan controller 16 generates a scan signal, a clock, and the like from the control code sent from the control CPU 15 to generate a test access port (TAP) 17 or 18.
Control.

One test access port 17 is connected to each of the semiconductor devices 12-1 to 12-12 corresponding to the boundary scan.
The scan signal is sent to the main scan chain block 19 forming the main scan chain at -n to control the boundary scan of the main scan chain. The other test access port 18
Is used to control the memory control device 13 independently of the main scan chain in order to test a net connecting the memory control device 13 and the memory 14 not supporting boundary scan. The memory control device 13 transmits the test data set in the registers 20-1 to 20-m provided corresponding to the input / output pins connected to the memory 14 according to the memory control signal to the memory 14 not supporting boundary scan. Interact between

The test access port 17 and the main scan chain block 19 are connected by a boundary scan control signal line 21, and the test access port 18 and the memory control device 13 are connected by a boundary scan control signal line 22. These boundary scan control signal lines 21 and 22 are composed of test clock (TCLK), test mode set (TMS), test data input (TDI), and test data output (TDO) lines.

Next, the details of the boundary scan test for the semiconductor devices 12-1 to 12-n mounted on the PCB 11 to be tested and the memory 14 that does not support boundary scan will be described.

FIG. 2 is a flowchart of the entire process of the boundary scan test. A control code is provided from the control CPU 15 to the boundary scan controller 16. The scan data generated by the boundary scan controller 16 according to the control code controls the test access port 18 to write test data to the boundary scan cell of the memory control device 13, and stores the test data in the boundary scan non-compatible memory 14. The data is written to a predetermined address of the boundary scan non-compliant memory 14 through a network connecting between.

FIG. 3 shows a memory 1 not supporting boundary scan.
4 shows a signal state when the test data is written to No. 4. The test data is input by the TDI of the control line 22 for giving a signal from the test access port 18 to the memory control device 13, and the test data write command is input by the TMS.

At this time, the boundary scan controller 16 controls so that the states of TMS and TCLK on the control signal line 21 of the other test access port 17 are maintained at the H level. Thereby, the port selection unit 2
The command transmitted by TMS and the clock transmitted by TCLK from the test access port 18 via the AND gate of No. 3 are supplied to the memory control device 13.
Also, by maintaining the TDI of the control signal line 21 of the other test access port 17 at L level (a state without input data), the TDI is transmitted from the test access port 18 via the OR gate of the port selection unit 24 by TDI. The received test data is stored in the memory control device 13.
Given to.

The memory control device 13 receives a command from the test access port 18 and sets test data in the registers 20-1 to 2-m, which are boundary scan cells. And writes the test data to the memory 14 not supporting boundary scan.

FIG. 3 shows the test access port 18.
, The test data input to the memory control device 13 via the TDI is used for the boundary scan of the memory control device 13, and then returns to the test access port 18 via the TDO. When the boundary scan test is performed only on the memory control device 13, as shown in FIG. 3, the test data used for the boundary scan is transferred from the memory control device 13 to the test access port 1 via the TDO.
Return to 8.

When the test data is written into the memory 14 not supporting the boundary scan under the control of the test access port 18, the boundary scan controller 16
To a test access port 17 to perform a boundary scan test of the main scan chain.

FIG. 4 shows signal states when a boundary scan test of the main scan chain is performed. Instructions (TMS) and test data (T) from the test access port 17 to the individual semiconductor devices 12-1 to 12-n forming the main scan chain block 19 via the boundary scan control signal line 21.
DI) and a clock (TCLK). The boundary scan test for each of the semiconductor devices 12-1 to 12-n is as described above.

Here, the memory control device 13 reads out the test data written in the memory 14 in the above-described write processing and tests the net connected to the non-boundary scan non-compatible memory 14 to register 20-1. ~
20-n. Then, the registers 20-1 to 20
The test data held at −n is written to the transfer register of the memory control device 13 in the same manner as in the above-described boundary scan test. The test data read from the memory 14 that does not support boundary scan into the memory control device 13
Transfer to the test access port 17 via DO.

The test data that has reciprocated on the net connecting the memory control device 13 and the memory 14 not supporting boundary scan is taken in from the test access port 17 and the soundness of the net is checked in the same manner as the other nets.

If it is necessary to rewrite the test data for verifying the net connecting the memory control device 13 and the memory 14 not supporting boundary scan during the scan, the signal state as shown in FIG. By changing the data, the new test data is given to the memory control device 13 to instruct the memory control device 13 to write to the memory 14 not supporting boundary scan. In this way, by changing the test data to be written to the non-boundary scan-compatible memory 14 and performing scanning, it is possible to check a plurality of test patterns.

Further, instead of writing the test data from the memory control device 13 to the memory 14 not supporting boundary scan, the memory 1 not supporting boundary scan 1
4 is refreshed, data is read from the memory control device 13 to the boundary scan non-compliant memory 14 after the refresh, and the data is transferred to the test access port 17 via the TDO when the memory control device 13 scans. Since the memory content of the boundary scan non-compliant memory 14 after the refresh is in the "no data" state, if the data transferred to the test access port 17 after the refresh is in the "no data" state, the memory control device 13 It is determined that the net connecting the boundary scan non-compliant memory 14 is sound.

According to such an embodiment, the test access port 17 for controlling the boundary scan test for the main scan chain block 19 and the semiconductor device 14 that does not support the boundary scan are included in the main scan chain block 19. Since the semiconductor device 1 includes the test access port 18 for controlling the control device 13, the semiconductor device 1 does not support the boundary scan.
Boundary scan test can be performed up to the net connecting to the network 4.

(Second Embodiment) Of the test access ports provided respectively corresponding to the main scan chain block and the semiconductor device that does not support boundary scan, the test access port of the semiconductor device that does not support boundary scan is used. A controller having the same function is provided on the PCB under test.

FIG. 5 shows a second embodiment of the present invention. The semiconductor devices mounted on the PCB under test 30 include a plurality of semiconductor devices 12-1 to 12-n that support boundary scan (including the memory control device 13) and a memory control device 13 that does not support boundary scan. And a memory 14 whose writing / reading is controlled from the memory. Further, a controller 31 for controlling writing / reading to / from the memory 14 in the memory control device 13 is mounted on the PCB 30.

The controller 31 controls TCLK, TMS,
The control of the memory control device 13 through the control signal lines of TDO and TDI is the same as that of the test access port 18 in the first embodiment, but the timing of writing / refreshing during the main scan is the boundary scan. It is not determined by the controller 32 but determined by itself. That is, by monitoring the TMS of the test access port 17 that controls the main scan chain block 19, the timing of writing / reading to / from the memory 14 not supporting boundary scan is acquired. If the memory 14 needs to be refreshed during the boundary scan, an interrupt is issued to the boundary scan controller 32 to stop the scan.

Next, the details of the boundary scan test for the semiconductor devices 12-1 to 12-n and the memory 14 not compatible with the boundary scan mounted on the PCB under test 30 will be described.

FIG. 6 is a flowchart of the entire process of the boundary scan test. The control CPU 15 supplies a control code to the scan controller 32, inputs test data from the controller 31 to the memory control device 13, and performs an initial setting process of writing the test data to the boundary scan non-compliant memory 14.

FIG. 7 shows a memory 1 not supporting boundary scan.
4 shows a signal state when the test data is written to No. 4. The controller 31 includes the memory control device 13
, A TDI signal is input through an OR gate 24, and a TMS and TCLK signal are input through an AND gate of the input port selection unit 23.

The memory control device 13 receives a memory control signal (TMS, TCLK,
The initial setting is completed by writing the test data to the boundary scan non-compliant memory 14 as a set in the boundary scan cell based on the TDI signals). When the initialization is completed, the controller 31 sends a notification of the completion of the initialization to the boundary scan controller 32.

The boundary scan controller 32 confirms that the test data has been written to the memory 14 not supporting boundary scan by a notification from the controller 31.
Supplies a scan signal or the like to the test access port 17 to perform a boundary scan test of the main scan chain.

FIG. 8 shows signal states when a boundary scan test of the main scan chain is performed. Instructions (TMS) and test data (T) from the test access port 17 to the individual semiconductor devices 12-1 to 12-n forming the main scan chain block 19 via the boundary scan control signal line 21.
DI) and a clock (TCLK). The boundary scan test for each of the semiconductor devices 12-1 to 12-n is as described above.

Each time one boundary scan is completed, the controller 31 writes new test data into the memory 14 not supporting boundary scan. The timing at that time is obtained by monitoring the SAMPLE / PRELOAD signal of TMS output from the test access port 17.

When refresh of the memory 14 not supporting boundary scan is required during the main scan, the controller 31 issues an interrupt signal to the boundary scan controller 32 to interrupt the scan. After the memory 14 is refreshed, the boundary scan of the main scan chain block 19 is performed again from the test access port 17.

As shown in FIG. 7, a scan of the memory control device 13 including a net connecting the memory control device 13 and the boundary scan non-compatible memory 14 is independently performed, and the TDO is sent to the controller 31 from the TDO. The scan result may be transferred.

According to such an embodiment, similarly to the first embodiment, it is possible to execute a boundary scan test on a net connecting between the memory control device 13 and the boundary scan non-compliant memory 14. it can.

In the above description, a memory is taken as an example of a semiconductor device that does not support boundary scan, but an element other than a memory may be used. For example, the present invention can be applied to a device that outputs a data pattern determined to be given a predetermined pattern of data from a semiconductor device that supports boundary scan. The present invention is not limited to the above embodiment, and various modifications can be made without departing from the spirit of the present invention.

[0045]

As described above in detail, according to the present invention, even a net connecting to a device which does not support boundary scan can be incorporated in a part of the scan chain, and a device which does not support boundary scan. The present invention can provide a boundary scan test method capable of expanding the test area up to.

[Brief description of the drawings]

FIG. 1 is an overall configuration diagram of a first embodiment of the present invention.

FIG. 2 is a flowchart of a boundary scan test according to the first embodiment.

FIG. 3 is a signal state diagram when writing test data to a memory according to the first embodiment;

FIG. 4 is a signal state diagram when a main scan chain is executed in the first embodiment.

FIG. 5 is an overall configuration diagram of a second embodiment of the present invention.

FIG. 6 is a flowchart of a boundary scan test according to the second embodiment.

FIG. 7 is a signal state diagram when writing test data to a memory according to the second embodiment.

FIG. 8 is a signal state diagram when a main scan chain is executed in the second embodiment.

FIG. 9: Conventional PCB with boundary scan cell
FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 ... PCB under test 12-1-12-n ... Semiconductor device corresponding to boundary scan 13 ... Memory control device 14 ... Non-boundary scan compatible memory 15 ... Control CPU 16 ... Boundary scan controller 17, 18 ... Test access port 19: Main scan chain block 21, 22 ... Boundary scan control signal line

Claims (4)

[Claims] A scan-compatible semiconductor device including cells for boundary scan and a scan-non-compliant semiconductor device not supporting boundary-scan are mounted, and the scan-compatible semiconductor device and the scan-non-compliant semiconductor device are provided. A method of testing a connection line between the scan-compatible semiconductor device and the non-scan-compatible semiconductor device by a boundary scan method on a substrate under test electrically connected between the scan-compatible semiconductor device and the scan-compatible semiconductor device. A test access port of the semiconductor device is controlled to supply test pattern data to the scan-incompatible semiconductor device, and an output pattern predetermined for the test pattern itself or the test pattern from the scan-incompatible semiconductor device. Uptake to the scan corresponding semiconductor device through said connection line, then the boundary scan test method characterized by testing the connection line by executing a boundary scan of the scan corresponding semiconductor device. 2. The boundary scan test method according to claim 1, wherein a plurality of boundary scan semiconductor devices mounted on the substrate under test are connected via a connection line to the boundary scan of the plurality of scan-compatible semiconductor devices as a whole. The boundary scan of a single scan-compatible semiconductor device by controlling a separate test access port, and the test pattern or output pattern taken into the scan-compatible semiconductor device from the non-scan-compatible semiconductor device. A boundary scan test method comprising: collecting as a test result information when a semiconductor device corresponding to the scan is a target in a boundary scan of the whole. 3. A scan-compatible semiconductor device having a cell for boundary scan and a non-scan-compatible semiconductor device not supporting boundary scan are mounted, and the scan-compatible semiconductor device and the non-scan-compatible semiconductor device are mounted. A method of testing a connection line between the scan-compatible semiconductor device and the non-scan-compatible semiconductor device by a boundary scan method on a substrate under test electrically connected between the scan-compatible semiconductor device and the scan-compatible semiconductor device. A controller that performs a boundary scan of the semiconductor device controls the scan-compatible semiconductor device to supply test pattern data to the non-scan-compatible semiconductor device, and the test pattern itself or the test pattern from the non-scan-compatible semiconductor device. A predetermined output pattern for the pattern is taken into the scan-compatible semiconductor device through the connection line, and thereafter, the connection line is tested by performing a boundary scan of the scan-compatible semiconductor device. Boundary scan test method. 4. The boundary scan test method according to claim 3, wherein a boundary scan is performed on all of the plurality of scan-compatible semiconductor devices mounted on the substrate under test by controlling a test access port, and the controller receives a signal from the controller. When the test pattern or the output pattern is fetched from the scan-incompatible semiconductor device to the scan-compatible semiconductor device by the control, and the test pattern or the output pattern is targeted for the scan-compatible semiconductor device in the boundary scan of the entire scan-compatible semiconductor device A boundary scan test method, which is collected as test result information.