JPH1117109A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device which enables increase in the surface area of a capacitor lower electrode simply and with good controllability and a small number of steps. SOLUTION: On a silicon oxide film 2 deposited on a silicon wafer 1, a polysilicon 5a containing no phosphorus and a polysilicon 5b containing phosphorus are alternately stacked. The polysilicons 5a, 5b are thermally oxidized to form a thermal oxide film 6 on the surfaces of the polysilicons 5a, 5b. The thermal oxide film 6 is formed to be thick on the surface of the polysilicon 5b having a high concentration of phosphorus, and the surfaces of the polysilicons 5a, 5b are formed in recessed and protruding shapes. Thus, the surface area of a capacitor lower electrode can be increased simply and at a small number of steps with good controllability.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a lower electrode of a capacitor.

[0002]

2. Description of the Related Art In recent years, memory LSIs using semiconductors have become extremely highly integrated, and various improvements have been made in order to ensure the capacity of fine capacitors. One method of obtaining high capacitance without increasing the area occupied by the capacitor is to roughen the surface of the capacitor lower electrode.

FIGS. 15 to 17 are process diagrams showing a conventional method of roughening the lower electrode of a capacitor. As shown in FIG. 15, a silicon oxide film 2 is deposited on a silicon wafer 1. Then, after depositing polysilicon, patterning is performed to form the capacitor lower electrode 3.

Next, as shown in FIG. 16, a nucleus 4 of polysilicon is formed on the surface of the capacitor lower electrode 3. Next, as shown in FIG. 17, the surface of the capacitor lower electrode 3 is roughened by grain growth of the polysilicon nucleus 4.

[0005]

The conventional method for roughening the capacitor lower electrode is as described above. To increase the surface area of the capacitor lower electrode, formation of the capacitor lower electrode, nucleation, and grain growth of the nucleus are performed. However, there is a problem that the number of steps is large. In addition, there is also a problem that the process is complicated because it includes a step of nucleation which is not included in a general semiconductor process. Furthermore, in the nucleation step, it is difficult to control the adhesion of nuclei, and there is a problem that the adhesion of nuclei varies, and it is difficult to control the increase in the surface area of the capacitor lower electrode.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and provides a method of manufacturing a semiconductor device which can increase the surface area of a capacitor lower electrode, is simple, has good controllability, and has a small number of steps. It is intended to be.

[0007]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming an insulating film on a semiconductor substrate; and forming a polysilicon film or an amorphous silicon film containing no impurities on the insulating film. Forming a stack by alternately sequentially depositing a polysilicon film or an amorphous silicon film containing impurities and an amorphous silicon film; thermally oxidizing the stack to form a thermal oxide film on the surface of the stack; And forming a concave and convex portion on the side surface of the laminate by removing the above.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming an insulating film on a semiconductor substrate; etching the insulating film to form a concave portion in the insulating film;
Forming a stack by alternately and sequentially depositing a polysilicon film or an amorphous silicon film containing no impurities and a polysilicon film or an amorphous silicon film containing impurities on the insulating film containing the concave portion; Etching the insulating film until the insulating film is exposed, embedding the laminate in the concave portion, thermally oxidizing the laminate to form a thermal oxide film on the upper surface of the laminate, and forming the thermal oxide film and the laminate side surface. Forming an unevenness on the upper surface of the stack by removing the insulating film.

According to a third aspect of the present invention, in a method of manufacturing a semiconductor device, a polysilicon film containing no impurities or an amorphous silicon film and a polysilicon film containing impurities are controlled by controlling a flow rate of a gas containing impurities in a CVD method. Alternatively, an amorphous silicon film is alternately and sequentially deposited to form a laminate.

According to a fourth aspect of the present invention, in the method of manufacturing a semiconductor device, a polysilicon film or an amorphous silicon film containing no impurities and a polysilicon film or an amorphous silicon film containing impurities are alternately deposited by sputtering. Thus, a laminate is formed.

According to a fifth aspect of the present invention, in a method of manufacturing a semiconductor device, a polysilicon film or an amorphous silicon film is deposited by a CVD method, and the impurity is implanted to a desired depth by an ion implantation method. A stacked structure of a polysilicon film or an amorphous silicon film that does not contain and a polysilicon film or an amorphous silicon film that contains impurities is formed.

According to a sixth aspect of the present invention, in the method of manufacturing a semiconductor device, the impurity is any one of phosphorus, arsenic, and antimony.

According to a seventh aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a laminate having unevenness is used as a capacitor lower electrode.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. 1 to 5 are process sectional views showing a method for forming a capacitor lower electrode according to the present invention. First, as shown in FIG. 1, a silicon oxide film 2 as an insulating film is deposited on a silicon wafer 1 as a semiconductor substrate. Thereafter, a polysilicon 5a containing no phosphorus as an impurity and a polysilicon 5b having a phosphorus concentration of 5 to 8 × 10 ²⁰ atoms / cm ³ are respectively formed on the silicon oxide film 2 to a thickness of about 10 nm.
Deposit alternately to the extent.

At this time, the polysilicon 5 having a different phosphorus concentration is used.
As a method of depositing a and 5b, a method of controlling the flow rate of phosphine (PH ₃ ) when depositing polysilicon by CVD, or alternatively, alternately depositing polysilicon having different phosphorus concentrations on the silicon oxide film 2. Or a method of depositing polysilicon containing no phosphorus on the silicon oxide film 2 and then implanting phosphorus atoms at different depths by ion implantation to form layers having different phosphorus concentrations. There is.

In FIG. 1, the capacitor lower electrode is described as being formed on the silicon oxide film 2. However, a device such as a transistor may exist below the silicon oxide film 2.

Next, as shown in FIG. 2, the polysilicons 5a and 5b are patterned by photolithography and etching.

Next, as shown in FIG.
a, 5b are thermally oxidized to form a thermal oxide film 6 on the surfaces of the polysilicons 5a, 5b. At this time, the polysilicon 5a, 5
Since the oxidation rate of b depends on the phosphorus concentration, the thermal oxide film 6 is formed thick on the surface of the polysilicon 5b having a high phosphorus concentration, and the surfaces of the polysilicons 5a and 5b have irregularities.

At this time, the thermal oxidation of the polysilicons 5a and 5b is performed by an oxidation method containing hydrogen atoms, for example, a wet oxidation method. This is because the oxidation can be performed at a low temperature, and the dependency of the growth rate of the oxide film on the phosphorus concentration is larger than that of an oxidation method containing no hydrogen, for example, a dry oxidation method.

Next, as shown in FIG.
The thermal oxide film 6 on the surfaces a and 5b is removed with a hydrofluoric acid solution. As a result, the capacitor lower electrode 5 having an uneven side wall can be formed, and the surface area of the capacitor lower electrode 5 increases.

After that, as shown in FIG. 5, a dielectric film 7 and an upper electrode 8 made of polysilicon are formed on the capacitor lower electrode 5 having an uneven side wall, and a capacitor is formed by patterning.

As described above, the surface of the capacitor lower electrode 5 can be made uneven with good controllability in a simple and small number of steps, and the surface area of the capacitor lower electrode 5 is increased, so that the capacitor capacity can be sufficiently secured.

Here, the case where phosphorus is used as an impurity contained in polysilicon has been described, but arsenic or antimony may be used. Although the case where the capacitor lower electrode 5 is made of polysilicon has been described, amorphous silicon may be used. Further, without being limited to this example, the present invention can be widely applied to a method of manufacturing a device that requires formation of unevenness on a plane or expansion of a surface area.

Embodiment 2 FIG. In the first embodiment, the case where the side wall of the capacitor lower electrode is made uneven is described. Here, the case where the upper surface of the capacitor lower electrode is made uneven is described.

6 to 11 are process sectional views showing a method of forming a capacitor lower electrode according to the second embodiment. First, FIG.
As shown in FIG. 1, a silicon oxide film 2
Is deposited. Thereafter, photolithography and etching are performed on the silicon oxide film 2 to pattern a portion for forming a capacitor lower electrode into a concave portion 9 shape.

Next, as shown in FIG. 7, the recessed portions 9 of the silicon oxide film 2
Polysilicon 5b having a phosphorus concentration of × 10 ²⁰ atoms / cm ³ is alternately deposited to a thickness of about 10 nm. At this time, the polysilicons 5a having different phosphorus concentrations,
5b is deposited by controlling the flow rate of phosphine (PH ₃ ) when depositing polysilicon by CVD, or alternately sputtering polysilicon having a different phosphorus concentration on the silicon oxide film 2. And the like.

Next, as shown in FIG.
By exposing the surface of the silicon oxide film 2 by etching the polysilicon 5a, 5b,
5b is embedded.

Next, as shown in FIG. 9, the polysilicons 5a and 5b embedded in the recess 9 are thermally oxidized to form a thermal oxide film 6 on the surfaces of the polysilicons 5a and 5b. At this time, since the oxidation rate of the polysilicons 5a and 5b depends on the phosphorus concentration, the thermal oxide film 6 is formed thick on the surface of the polysilicon 5b having a high phosphorus concentration, and the surfaces of the polysilicons 5a and 5b are The shape becomes uneven.

At this time, the thermal oxidation of the polysilicons 5a and 5b is performed by an oxidation method containing hydrogen atoms, for example, a wet oxidation method. This is because the oxidation can be performed at a low temperature, and the dependency of the growth rate of the oxide film on the phosphorus concentration is larger than that of an oxidation method containing no hydrogen, for example, a dry oxidation method.

Next, as shown in FIG. 10, a thermal oxide film 6 of polysilicon 5a, 5b and polysilicon 5a, 5b
The oxide film 2 on the side surface is removed by performing anisotropic etching. As a result, the capacitor lower electrode 10 having an uneven upper surface can be formed, and the surface area of the capacitor lower electrode can be increased.

Thereafter, as shown in FIG. 11, a dielectric film 7 and an upper electrode 8 made of polysilicon are formed on a capacitor lower electrode 10 having an uneven upper surface, and a capacitor is formed by patterning.

As described above, the surface of the capacitor lower electrode 10 is made uneven in a simple and small number of steps with good controllability and the surface area of the capacitor lower electrode 10 is increased, so that a sufficient capacitance of the capacitor can be ensured.

Although the case where phosphorus is used as an impurity contained in polysilicon has been described, arsenic or antimony may be used. Although the case where the capacitor lower electrode 10 is made of polysilicon has been described, amorphous silicon may be used.

Embodiment 3 The capacitor described in the first embodiment can be formed also in a capacitor having a three-dimensional structure. 12 to 14 are views showing a method of forming a capacitor lower electrode having a cylindrical structure according to the third embodiment.

First, as shown in FIG. 12, similarly to FIG. 1, the polysilicon 5a containing no phosphorus and the polysilicon 5b having a phosphorus concentration of 5 to 8 × 10 ²⁰ atoms / cm ³ are formed on the side wall of the cylinder. And each have a thickness of about 10 nm
Deposit alternately to the extent.

At this time, the polysilicon 5 having a different phosphorus concentration is used.
As a method of depositing a and 5b, a method of controlling the flow rate of phosphine (PH ₃ ) when depositing polysilicon by CVD, or a method of alternately sputtering polysilicon having different phosphorus concentrations. Alternatively, there is a method of depositing polysilicon containing no phosphorus and then implanting phosphorus atoms to different depths by ion implantation to form layers having different phosphorus concentrations.

Next, as shown in FIG. 13, the polysilicons 5a and 5b are thermally oxidized to form a thermal oxide film on the surfaces of the polysilicons 5a and 5b. At this time, the polysilicon 5a,
Since the oxidation rate of 5b depends on the phosphorus concentration, the thermal oxide film is formed thick on the surface of the polysilicon 5b having a high phosphorus concentration, and the surfaces of the polysilicons 5a and 5b have irregularities. Thereafter, the thermal oxide film on the surfaces of the polysilicons 5a and 5b is removed with a hydrofluoric acid solution. As a result, the cylindrical capacitor lower electrode 1 having an uneven side wall
1 can be formed, and the surface area of the capacitor lower electrode 11 can be increased.

Next, as shown in FIG. 14, a dielectric film 7 and an upper electrode 8 made of polysilicon are formed on a cylindrical capacitor lower electrode 11 having an uneven side wall in the same manner as in a normal cylindrical capacitor manufacturing process. Are formed and patterned to form a concave-convex cylindrical capacitor.
Therefore, the surface of the capacitor lower electrode 11 is made uneven in a simple and few steps with good controllability and the surface area of the capacitor lower electrode 11 is increased, so that the capacitor capacity can be sufficiently secured.

Further, in the same manner as in the second embodiment, if the upper surface of the bottom portion of the cylindrical capacitor lower electrode 11 is formed in an uneven shape, the surface area of the capacitor lower electrode 11 can be further increased.

Here, a case where phosphorus is used as an impurity contained in polysilicon has been described, but arsenic or antimony may be used. Although the case where the capacitor lower electrode 11 is made of polysilicon has been described, amorphous silicon may be used.

[0041]

As described above, according to the present invention, an insulating film is formed on a semiconductor substrate, and a polysilicon film or an amorphous silicon film containing no impurities and a polysilicon film or an amorphous film containing impurities are formed on the insulating film. Forming a stack by alternately sequentially depositing a silicon film and forming a stack; forming a thermal oxide film on the stack surface by thermally oxidizing the stack; and removing the thermal oxide film to form the stack side surface. And the step of forming irregularities on the surface of the polysilicon film or the amorphous silicon film can be made uneven with simple and small steps with good controllability, and the surface area can be increased.

A step of forming an insulating film on the semiconductor substrate and etching the insulating film to form a recess in the insulating film; and forming a polysilicon film containing no impurities on the insulating film including the recess. Forming a stack by alternately sequentially depositing an amorphous silicon film and a polysilicon film containing impurities or an amorphous silicon film, and embedding the stack in the recess by etching the stack until the insulating film is exposed. Forming a thermal oxide film on the upper surface of the stack by thermally oxidizing the stack, and forming irregularities on the upper surface of the stack by removing the thermal oxide film and the insulating film on the side surfaces of the stack. The surface of the laminated polysilicon film or amorphous silicon film can be made uneven with good controllability in simple and few steps, and the surface area can be reduced. It is possible to increase.

Also, by controlling the flow rate of the gas containing impurities in the CVD method, a polysilicon film or an amorphous silicon film containing no impurities and a polysilicon film or an amorphous silicon film containing impurities are alternately sequentially deposited and laminated. Is formed, a stack can be formed with a simple process with good controllability.

Further, since a polysilicon film or an amorphous silicon film containing no impurities and a polysilicon film or an amorphous silicon film containing impurities are alternately and sequentially deposited by sputtering to form a laminate,
A laminate can be formed with a simple process with good controllability.

After a polysilicon film or an amorphous silicon film is deposited by the CVD method, an impurity is implanted to a desired depth by an ion implantation method, so that a polysilicon film or an amorphous silicon film containing no impurities and an impurity are contained. Since a stack with a polysilicon film or an amorphous silicon film is formed, a stack can be formed with a simple process with good controllability.

Further, since the impurity is any one of phosphorus, arsenic and antimony, the oxidation rate when forming a thermal oxide film on the surface of polysilicon or amorphous silicon depends on the impurity concentration, and Since the film thickness is different, an uneven shape can be formed on the surface of the polysilicon film or the amorphous silicon film, and the surface area can be increased.

Further, since the laminated structure having the irregularities is used as the capacitor lower electrode, the surface area of the capacitor lower electrode can be increased, and the capacitor capacity can be sufficiently secured even if the element is miniaturized.

[Brief description of the drawings]

FIG. 1 is a process sectional view illustrating a method for forming a capacitor lower electrode according to Embodiment 1 of the present invention;

FIG. 2 is a process cross-sectional view showing a method for forming a capacitor lower electrode according to the first embodiment of the present invention;

FIG. 3 is a process sectional view illustrating the method of forming the capacitor lower electrode according to the first embodiment of the present invention.

FIG. 4 is a process sectional view illustrating the method of forming the capacitor lower electrode according to the first embodiment of the present invention.

FIG. 5 is a process sectional view illustrating the method of forming the capacitor lower electrode according to the first embodiment of the present invention.

FIG. 6 is a process sectional view illustrating the method of forming the capacitor lower electrode according to the second embodiment of the present invention.

FIG. 7 is a process sectional view illustrating the method of forming the capacitor lower electrode according to the second embodiment of the present invention.

FIG. 8 is a process sectional view illustrating the method of forming the capacitor lower electrode according to the second embodiment of the present invention.

FIG. 9 is a process sectional view illustrating the method of forming the capacitor lower electrode according to the second embodiment of the present invention.

FIG. 10 is a process sectional view illustrating the method of forming the capacitor lower electrode according to the second embodiment of the present invention.

FIG. 11 is a process sectional view illustrating the method of forming the capacitor lower electrode according to the second embodiment of the present invention.

FIG. 12 is a process sectional view illustrating the method of forming the capacitor lower electrode according to the third embodiment of the present invention.

FIG. 13 is a process sectional view illustrating the method of forming the capacitor lower electrode according to the third embodiment of the present invention.

FIG. 14 is a process sectional view illustrating the method of forming the capacitor lower electrode according to the third embodiment of the present invention.

FIG. 15 is a process sectional view showing a conventional method for roughening the capacitor lower electrode.

FIG. 16 is a process cross-sectional view showing a conventional method for roughening a capacitor lower electrode.

FIG. 17 is a process sectional view showing a conventional method of roughening the capacitor lower electrode.

[Explanation of symbols]

Reference Signs List 1 silicon wafer, 2 silicon oxide film, 5a phosphorus-free polysilicon, 5b phosphorus-containing polysilicon, 6 thermal oxide film, 9 concave portion, 5, 10, 11 capacitor lower electrode.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Yoshitaka Otsu 4-1-1 Mizuhara, Itami-shi, Hyogo Ryoden Semiconductor System Engineering Co., Ltd. (72) Tomohiko Hayashi 4-1-1 Mizuhara, Itami-shi, Hyogo Ryoden Semiconductor System Engineering Co., Ltd.

Claims (7)

[Claims] An insulating film is formed on a semiconductor substrate, and a polysilicon film or an amorphous silicon film containing no impurities and a polysilicon film or an amorphous silicon film containing impurities are alternately deposited on the insulating film. Forming a laminate, thermally oxidizing the laminate to form a thermal oxide film on the laminate surface, and removing the thermal oxide film to form irregularities on the laminate side surfaces. A method for manufacturing a semiconductor device, comprising: A step of forming an insulating film on the semiconductor substrate and etching the insulating film to form a recess in the insulating film; and forming a polysilicon film containing no impurities on the insulating film including the recess. Forming a stack by alternately sequentially depositing an amorphous silicon film and a polysilicon film containing impurities or an amorphous silicon film, and embedding the stack in the recess by etching the stack until the insulating film is exposed. And forming a thermal oxide film on the upper surface of the stack by thermally oxidizing the stack, by removing the thermal oxide film and the insulating film on the side surface of the stack,
Forming a concavo-convex pattern on the upper surface of the layered structure. 3. A polysilicon film or an amorphous silicon film containing no impurity and a polysilicon film or an amorphous silicon film containing an impurity are alternately sequentially deposited and stacked by controlling a flow rate of a gas containing an impurity in a CVD method. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the method is performed. 4. A stacked structure is formed by alternately sequentially depositing a polysilicon film or an amorphous silicon film containing no impurities and a polysilicon film or an amorphous silicon film containing impurities by a sputtering method. A method for manufacturing a semiconductor device according to claim 1. 5. After depositing a polysilicon film or an amorphous silicon film by a CVD method, an impurity is implanted to a desired depth by an ion implantation method, and the polysilicon film or the amorphous silicon film containing no impurities and the impurities are contained. 2. The method according to claim 1, wherein a lamination with a polysilicon film or an amorphous silicon film is formed. 6. The method of manufacturing a semiconductor device according to claim 1, wherein the impurity is any one of phosphorus, arsenic, and antimony. 7. The method of manufacturing a semiconductor device according to claim 1, wherein a layer having irregularities is used as a capacitor lower electrode.