JPH1117019A - Semiconductor integrated circuit device and method for manufacturing wiring programming element used for the device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to form an element in microscopic size by a method wherein a wiring programming element, to be selectively cut, is composed of the top wiring layer, and after formation of the surface of the first insulating film, the second insulating film, covering the cutting surface and the aperture part of the programming wiring part, is formed. SOLUTION: The top layer of a metal wiring layer M3, which constitutes a wiring programming element to be selectively cut corresponding to the result of the electric test on an electronic circuit, is formed on an interlayer insulating film INS4. Then, the surface of the first insulating film INS5, excluding the fixed wiring of the electronic circuit provided on the interlayer insulating film IND4 is formed. A program cutting part HP and the surface of a pad part, is formed. Subsequently, resist is applied on the first insulating film INS5, and an aperture is provided on the resist on the upper part of the wiring programming element to be cut by EB(electron beam) lithography. Lastyl, the first insulating film INS5 is etched using the resist as a mask, and the second insulating film INS6 is deposited.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a method of manufacturing a wiring program element used therein, and more particularly to a technology effective for use in a defect remedy technology in a RAM (random access memory). is there.

[0002]

2. Description of the Related Art As a technique for relieving defects in a semiconductor memory, there is a method in which a row (word line) or a column (data line or bit line) including a defective memory cell is collectively replaced with a redundant row and a redundant column. In this method, after the end of the wafer process, after testing the operation of all bits with a wafer probe,
A defective row address or a column address is programmed for each chip by cutting a fuse in the chip. Then, each time a row address or a column address is input during chip operation, the programmed defective address is compared with the input address, and if they match, a redundant row or column is activated. As a method for cutting a fuse, a laser cutter is generally used.

[0003] Row replacement and column replacement are effective techniques when most of the memory cells in a row or column become inoperable, such as when a word line or data line is short-circuited or disconnected. On the other hand, when a small number of memory cells in the row are defective, such as a refresh defect caused by a defect in the substrate, there is a problem that efficiency is deteriorated. Therefore, a defective column address ROM is prepared for each word line, the column address of the defective cell on one word line is stored, and only the defective cell of the column address is replaced with the cell of the redundant column. Each replacement is proposed in Japanese Patent Application Laid-Open No. 6-20494.

[0004]

When a laser cutter is used for cutting a fuse as in the prior art, the size of the fuse cannot be reduced because the laser spot size is large. Also, it takes time to cut it,
When a large number of fuses are mounted, a correspondingly long time is required for cutting (programming). In addition, since the cut surface of the fuse is not covered with the insulating film after cutting, a guard ring is required, which also contributes to the inability to reduce the size of the fuse. For this reason,
At present, fuses for redundant circuits are about 10 μm square. In the conventional bit-by-bit replacement method, it is necessary to arrange ROMs at word line pitches. Usually, the word line pitch is about twice as large as the minimum processing size of the wafer process. For example, in the case of a 1 Gbit dynamic RAM of the 0.16 um rule, it is 0.32 um. Therefore, when trying to program a defective address ROM with a fuse, it is difficult to arrange the fuse because the size of the fuse is about 10 μm square. In order to solve the above-mentioned problems, the present inventors have developed a wiring program element having a fine element size and capable of selectively cutting in a short time in accordance with an operation test result of an electronic circuit. I came to.

An object of the present invention is to provide a semiconductor integrated circuit device equipped with a wiring program element having a fine element size and capable of selectively cutting in a short time, and a method of manufacturing the wiring program element. It is in. Another object of the present invention is to provide a semiconductor integrated circuit device having a wiring program element capable of being programmed in accordance with the result of an operation test of an electronic circuit and realizing high integration and low cost, and a semiconductor integrated circuit device having the same. An object of the present invention is to provide a method of manufacturing a wiring program element. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0006]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, a semiconductor integrated circuit device provided with an electronic circuit having a desired circuit function and a pad used for inputting and outputting an operating voltage and a signal of the electronic circuit is provided in a semiconductor integrated circuit device. A wiring program element, which forms a part of a path and is selectively cut in accordance with an electrical test result of the electronic circuit, is constituted by an uppermost wiring layer, and is formed by a first insulating film formed thereon. A program wiring portion having a cut surface etched and removed using a selective opening and a surface of the first insulating film excluding an upper surface of the pad, the cut surface of the program wiring portion, and a cutting surface used for cutting the program wiring portion. And a second insulating film covering an opening surface of the opening formed by irradiating an electron beam or a light spot with a resist film opening corresponding to the photosensitive portion in accordance with the test result.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a cross-sectional structural view of an embodiment for explaining a method of manufacturing a wiring program element according to the present invention. In the step (a), a final (uppermost) metal wiring layer M3 forming an electronic circuit having a desired circuit function is processed and formed. The metal wiring layer M3 is formed of a third aluminum layer formed on an interlayer insulating film INS4 that is electrically separated from wirings and the like below the metal wiring layer M3. And a pad (bonding pad, etc.) used for connection with an external terminal and a program cutting portion HP which changes a function of the electronic circuit by selective cutting of the wiring path.

In the step (b), a first insulating film INS5 is formed except for the surface of the pad portion. This first insulating film INS5 is formed of the same as the final passivation film in the conventional semiconductor integrated circuit device. For example, as the insulating layer INS5, hydrogen annealing is performed after depositing a silicon oxide film 0.3 μm by plasma CVD using tetraethoxysilane as a raw material. This hydrogen annealing is performed to reduce the interface order of the MOSFET,
As the process temperature, for example, about 450 ° C. is used. In each of the steps described below, the process temperature is 45
The temperature can be suppressed to 0 ° C. or less, and the effect of annealing can be maintained. Subsequently, a silicon nitride film 1.0 μm deposited by a plasma CVD method is laminated. This first insulating film INS5
Has a role of preventing the wiring and the program cutting portion HP from being damaged at the time of the probe or being deteriorated by moisture.

As described above, unlike the final passivation film in the conventional semiconductor integrated circuit device, the first insulating film INS5 is formed by the metal wiring layer M3 when an electronic circuit formed on a semiconductor wafer is electrically tested. This is to temporarily protect the wiring and the program cut portion, or to omit the silicon nitride film deposited by the plasma CVD method in order to facilitate the selective opening formation in the next step (c). It may be. When the semiconductor integrated circuit device is a memory circuit such as a dynamic RAM, the operation of the memory cells of all bits is tested to check the addresses of the defective memory cells. Then, it is checked whether the defective memory cell can be replaced with the redundant memory cell by the row replacement, the column replacement, or the bit-by-bit replacement method described in detail later. Although not particularly limited, in the case of a wafer probe, if the prober is a ball type, metal damage to the pad portion can be reduced.

In the step (c), if the chip can be replaced by a non-defective product, the row address or the column address of the defective memory cell is selectively cut by the wiring program element HP by the following method. Program. The wiring program element is formed using the final wiring layer M3. A resist is applied to the wafer on which the wafer probe has been completed, and an opening is formed in the resist above the wiring program element to be cut by EB (electron beam) lithography.

In the step (d), the first insulating film INS5 is dry-etched using the resist as a mask, and the etching is stopped when the cut portion of the wiring program element is exposed.

In the step (e), the cut portion of the exposed wiring program element is etched and cut. For example, dry etching is used for these etchings. The processing dimensions are for cutting the third layer M3, which is the uppermost layer, and the pitch of the third layer M3 itself is not so fine. Since the width and pitch cannot be formed minutely, the power of the plasma for the dry etching can be reduced, and the damage to the device can be reduced.

In step (f), after depositing a second insulating layer INS6 as a final passivation film on the entire surface, the second insulating film INS6 in the bonding pad portion is removed. The second insulating film INS6 is composed of, for example, a laminated film of a 0.3 μm silicon oxide film and a PIQ deposited by a plasma CVD method. If it is desired to enhance the function of preventing intrusion of moisture, a silicon nitride film 1um deposited by a plasma CVD method before the PIQ may be further laminated. Although not shown in the figure, the semiconductor wafer is diced for each chip and assembled into a package.

According to the present invention, the wiring program element HP
Can be reduced to about the minimum wiring width of the uppermost wiring layer M3, and the pitch of the wiring program elements HP can be reduced to the minimum pitch of the uppermost wiring layer M3. Therefore, such a wiring program element HP
Even when a large number of devices are mounted, the chip area can be reduced. This is because EB lithography is used to form the cutting opening, so that fine processing is possible as compared with a laser beam, and the wiring program element HP
This is because the cut portion is covered with the insulating layer, so that the penetration of moisture into the wafer is small, and an extra guard ring is unnecessary.

Since the above-mentioned EB lithography does not require a mask, unlike general optical lithography, it is possible to easily program whether or not the wiring program element is cut by changing the exposure pattern data of the EB. is there. Further, in EB lithography, the time required for exposing a cut portion of one wiring program element is extremely fast, on the order of microseconds. Since the process is performed collectively in units of semiconductor wafers, especially when the number of wiring program elements in one chip is large, the wiring program element cutting can be performed at a much higher speed than the laser cutting one by one. The process can be performed.

The reduction in the size of the wiring program element has the advantage that the chip area can be reduced even in a conventional redundant circuit system such as a row replacement or a column replacement. It becomes possible to replace defective memory cells of the dynamic RAM of the system by bits with redundant memory cells.

FIG. 2 is a schematic layout diagram showing one embodiment of a dynamic RAM to which the present invention is applied. The dynamic RAM of this embodiment is of a hierarchical word line or divided word line system, and realizes bit-by-bit relief corresponding to the divided sub-word lines. The entire chip is largely divided into a peripheral circuit section and an array section. The peripheral circuits are arranged in a cross at the center in the vertical and horizontal directions of the chip. The array is 4 depending on the peripheral circuit.
It is divided and arranged.

In the array section, sense amplifiers SA are arranged above and below a DRAM array in which memory cells are arranged on a lattice, and subword drivers SWD are arranged on the left and right.
Although not shown, the sub-word line (SWL) to which the address selection terminal of the memory cell is connected is connected to the sub-word driver SW.
The data line or bit line connected to D and connected to the input / output terminal of the memory cell is connected to the input / output terminal of the sense amplifier SA.

A row decoder and an SA (sense amplifier) control circuit are arranged in the vertical direction on the boundary between the array section and the peripheral circuit section, and a column decoder and a sub-word select line output circuit XS are arranged in the horizontal direction. As will be described later in detail, a main word line (MWL) which is an output of the X decoder is wired in a horizontal direction on the array, and a sub-word select line output circuit XS
Is output in the vertical direction on the sub-word driver SWD. A sub-word driver selects a sub-word line (SWL) according to the main word line (MWL) and a sub-word selection line (FX).

The SA control circuit generates a signal for controlling the sense amplifier SA such as a precharge signal. A column select line (YS), which is an output of the column decoder, is wired in a vertical direction on the array, and controls a column switch for connecting the sense amplifier SA to an unillustrated input / output line (I / O). The defective column address ROM and the comparator at the vertical end of the chip are used for performing bit-by-bit relief, as will be described later in detail.

The above peripheral circuit will be described. The high voltage generation circuit Vch is a circuit that generates a voltage higher than a power supply voltage input from outside the chip used for a word line or the like. The data line voltage generation circuit Vdl is a circuit that generates a high-level voltage of the data line. Peripheral circuit voltage generator V
ci is a circuit for generating a high-level voltage of a peripheral circuit. The substrate voltage generation circuit Vbb is a circuit that generates a negative voltage lower than the ground potential used for the substrate voltage. The intermediate potential generation circuit Vref is a circuit that generates an intermediate potential between a power supply potential input from outside the chip and a ground potential.

The main amplifier MA is a circuit for amplifying data on input / output (I / O) lines at high speed and transmitting the amplified data to an output buffer Do. The output buffer Do is connected to the main amplifier MA.
Is output from the bonding pad Pad to the outside of the chip. The input buffer Di is a circuit for transmitting data from outside the chip to the input / output (I / O) line.

The row address buffer XAB is connected to the pad P
This is a circuit that sends a row address signal transmitted from ad to a row decoder. The row control circuit is a circuit for controlling the operation timing of a row decoder, an SA control circuit, and the like based on a row timing signal (RAS) from outside the chip. The column address buffer YAB is a circuit that sends a column address transmitted from the pad Pad to a column decoder. The column control circuit is a column timing signal (CAS) from outside the chip
Is a circuit for controlling the operation timing of the column decoder, the output buffer Do, etc. The write control circuit controls the input buffer Di based on the write control signal (WE).
This is a circuit for controlling the writing of data from the I / O line to the input / output (I / O) line. The test circuit is a circuit used for an operation test inside the chip. The refresh control circuit Re is a circuit that controls refreshing during a refresh operation, and includes an address generating circuit for a self-refresh operation.

The row redundancy circuit includes a wiring program element for storing a defective row address and an address comparator, and is a circuit for performing row replacement. Similarly, the column redundancy circuit includes a wiring program element for storing a defective column address and an address comparator, and is a circuit for performing column replacement. When the wiring program element cutting process according to the present invention is used, the wiring program element can be reduced in size and the redundant circuit can be dispersedly arranged in the vicinity of the array. Further, the wiring program element of these redundant circuits may be a conventional laser-blown fuse under the hierarchical word-type bit-by-bit repair method described below. In this case, by combining with the wiring program element using the EB process of the present invention, it is possible to relieve a memory cell which has become inoperative due to the process after cutting.

FIG. 3 is a schematic circuit diagram showing one embodiment of a dynamic RAM to which the present invention is applied.
The dynamic RAM of this embodiment (hereinafter simply referred to as DRA)
It may be called M. ) Is performed for the above-mentioned hierarchical word type bit-by-bit rescue. DR using hierarchical word system
In the AM array, the word lines are hierarchized into a main word line MWL and a sub word line SWL. Main word line M
WL is selected by the row decoder, and the sub word line SWL
Is selected by the sub-word driver SWD.

The memory cell MC of the DRAM exists at the intersection of the sub-word line SWL and one of the pair of complementary data lines DL. The input / output terminal of the sense amplifier SA is connected to the complementary data line DL. The connection between the sense amplifier SA and the input / output line I / O is controlled by a column switch which is switch-controlled by a column selection line YS which is an output of the column decoder. At the time of reading, data Dout is output to the outside of the chip via the input / output line I / O and the main amplifier MA. At the time of writing, data Din is input from the outside of the chip via the input / output line I / O and the write buffer WB. Is done.

In this embodiment, for per bit replacement,
A redundant column selection line RYS, a redundant input / output line RI / O, a selector, a comparator, and a defective column address ROM are provided. The operation of per-bit replacement will be described below. A row address is input, and one main word line MWL is activated by a row decoder. The sub-word driver SW is connected to the main word line MWL and a sub-word line selection line FX (not shown).
By D, one of a plurality of sub-word lines SWL provided corresponding to the main word line MWL is selected.
By such a selection operation of the sub-word line SWL, a read signal corresponding to the information charge from the memory cell MC appears on the complementary data line DL. The sense amplifier amplifies the minute potential difference of the complementary data line DL to a high level and a low level.

Since the main word line MWL is directly extended and connected one-to-one with the word line of the ROM, one word line of the defective column address ROM is selected and the main word line MWL is selected. , And the defective column address is read in response to the selection of the main word line MWL.

A column address is input following the row-related selection operation. The comparator compares the column address with the defective column address read from the defective address ROM, and if they do not match, only the normal column YS is selected. Therefore, at the time of writing, the input data Din is written to the data line DL and the sense amplifier SA in the normal column via the write buffer WB-I / O line I / O, and the storage capacitor of the selected memory cell has the corresponding high level or A low-level charge is held. At the time of reading, data of the main amplifier MA connected to the input / output line I / O is output as output data Dout by the selector controlled by the selection signal RS.

If the comparator determines that the defective column address and the input column address match, both the redundant column RYS and the normal column YS are activated. However, since the input / output lines are separated into RI / O and I / O, no data collision occurs. At the time of writing, the input data Din is written to both the redundant column RYS and the normal column YS. At the time of reading, the control signal RS is activated, and the main amplifier MA connected to the redundant input / output line RI / O by the selector.
Is selected as output data Dout, so that correct data is read.

This system is characterized in that input / output lines are separated into redundant column input / output lines RI / O and normal input / output lines I / O. In this system, when a redundant column is selected, Since the decoder does not need to deactivate the normal column YS, the circuit configuration is simplified, and both are operated in parallel, and the output signal of the main amplifier MA is selected by a selector. Therefore, there is an advantage that the operation becomes faster.

In the hierarchical word type bit-by-bit repair method, when one redundant column replaces a defective cell existing in a plurality of columns, one redundant column is used.
Since a plurality of sub-word lines are controlled by four main word lines (four in this example), normal cells and redundant cells are replaced in units of a plurality of bits (four bits in this example).
In this example, the sub-word line SWL selected by the main word line MWL and the memory cell MC selected by the column selection signal YS1 are the four shown by the cell block CB1.
If there is at least one defective cell in the cell block CB1, the cell block CB2 in the redundant column is used.
Is replaced by This is an efficient replacement method when the influence of a defect in a wafer affects not only one cell but also a plurality of neighboring cells.

In the present invention, the defective column address ROM described above is used.
It is best to use the wiring program element shown in FIG. 1 as described below with reference to FIG. 4, but the present invention is not limited to this. In the hierarchical word type DRAM as in this embodiment, the wiring pitch of the main word line MWL is expanded to four times the wiring pitch of the sub word line SWL to which the memory cell is connected. Therefore,
The word line pitch of the defective column address ROM, which is obtained by extending the main word line MWL as it is, has a relatively wide space. Therefore, in addition to the wiring program element formed at a high density as described above, various types such as a type using a fuse cut by a laser beam, a type using an electrically writable nonvolatile storage element such as an EEPROM, etc. Can be taken.

FIG. 4 is a circuit diagram of an embodiment in which the defective column address ROM is constructed using the wiring program elements. The wiring program type ROM is
As described above, the ROM is a ROM that programs information "1" and "0" by cutting the wiring program element of the final wiring layer by EB lithography. Therefore, the layers below the final wiring layer M3 can be formed by a process for forming a normal DRAM. Further, unlike the case where the EPROM is used, a program does not require a high voltage higher than a power supply voltage.

The present invention is further characterized in that the replacement unit is the main word line MWL. This makes it possible to increase the pitch at which the memory cells of the defective column address ROM are arranged to the pitch of the main word line MWL. In this case, it is necessary to arrange the wiring program elements at the pitch of the main word line MWL, but the main word line MWL is usually connected to the second wiring layer M2 or the third wiring layer M2.
Since the wiring is performed in the third wiring layer M3, it is extremely easy to arrange the wiring program elements at the pitch by using the process of the present invention.

The defective column address ROM shown in FIG. 3 is activated by cutting the ROM activation wiring program element HRE in the ROM starting circuit. If the DRAM memory cell has few defects and does not require bit-by-bit replacement, the wiring program element HRE is not cut off and the N-channel MOSFET Q2 and the P-channel MOSFET Q3 are not cut.
, The input terminal of the CMOS inverter circuit is made high, and the output signal VPC is made low. At this time, the bit lines BL0 to BL2 of the ROM are always kept at the ground potential VSS. Therefore, by providing the ROM starting circuit, the charge / discharge power of the bit lines BL0 to BL2 of the ROM can be suppressed when the bit-by-bit replacement is not performed. Also, since all the outputs of the ROM become "0",
It is possible to inform the comparator that bit-by-bit replacement is not performed.

When performing bit-by-bit replacement, in the wiring program element cutting process after the wafer probe, a defective column address is programmed in the ROM for each main word line MWL, and the wiring program element HRE is cut. In this case, the output VPC of the CMOS inverter circuit is latched at the operating voltage Vcc / 2 with the N-channel MOSFET Q1 receiving the output VPC turned on. Therefore, when the precharge signal PC is activated, each of the bit lines BL0 to BL2 is precharged to Vcc / 2. The precharge signal PC is a signal having the same timing as the precharge signal for controlling the DRAM sense amplifier, although not particularly limited.

As described above, the defective column address ROM
Operates every time a row address of DARM is newly selected. After the row address is input and the precharge signal PC is deactivated, the row decoder outputs the main word line M.
When WL is selected, the main word line MWL in the DRAM array is selected, and the main word line MWL and the bit lines BL0 to BL0 in the defective column ROM are also selected.
MO in the ROM memory cell RMC at the intersection such as BL2
When the SFET is turned on and the wiring program element in the memory cell RMC is not disconnected, the bit line BL0 and the like are discharged to the ground potential VSS. When the MOSFET is disconnected, no discharge path is formed even when the MOSFET is turned on, so that the bit line BL0 and the like are connected to Vcc / 2.
Remains at the precharge level.

For example, if the wiring program element is defined as “0” when it is cut and “1” when it is not cut, this potential is amplified by the ROM sense amplifier RSA and programmed to the memory cell. It is possible to read the information of “0” and “1”. This information is passed to one input of the comparator as a bad column address,
As described above, the comparison with the column address supplied to the other input is performed to determine the match / mismatch.

FIG. 5 is a schematic circuit diagram showing another embodiment of the dynamic RAM to which the present invention is applied. In this embodiment, four defective column address ROMs are arranged in the word line direction. Individual defective column address R
OM0 to ROM3 are the same as those in FIG. 4. Word lines are arranged at the same pitch as the main word line MWL of the DRAM array in the data line direction. In the example, the YS line is 1024
The same number of memory cells RMC as the number of memory cells RMC (10 bits for the Y address) are provided corresponding to the book.

Four defective column addresses ROM0 to ROM3
Are four sets of sub-word lines SWL in the DRAM array.
The column address of the upper defective cell is programmed. For example, the sub word lines SWL00, SWL01, SWL02, SWL03 selected by the main word line MWL0
However, the column addresses of the defective cells above the above-mentioned RROM0, ROM1,
It is programmed in the memory cells RMC on the word lines of the ROM 2 and ROM 3 connected to the main word line MWL.

That is, one main word line MWL is activated by the row decoder, and the four sub-word lines SWL00, SWL01, SWL0 are output by the sub-word selection line FX which is the output of the sub-word selection circuit XS.
2. When one of SWL03 is selected, a read signal from the selected memory cell MC appears on the data line DL. The read signal of the data line is amplified by the sense amplifier SA. At the same time as the row selection operation of such a DRAM array, the defective column addresses ROM0 to ROM
3 is accessed in response to the main word line MWL selection operation. The defective column addresses ROM0 to ROM3 are
It has a word line (storage area) corresponding to each main word line MWL, and stores column addresses of defective memory cells on the main word line MWL, so that a maximum of four types of defective column addresses are read.

From these four types of defective column addresses,
The selector is controlled by the sub-word selection line FX,
A defective column address corresponding to the selected sub-word line SWL is selected and supplied to one input of a comparator. Subsequent steps are the same as in the embodiment of FIG. That is, when a column address is subsequently input, this column address is compared with the defective column address by the comparator.
Only is selected. In the above comparator, if it is determined that the defective column address matches the input column address,
The redundant column RYS and the normal column YS are both activated. However, since the input / output lines are separated into RI / O and I / O, no data collision occurs.

In the above hierarchical word type bit-by-bit repair method,
In addition to the feature that the arrangement pitch of the cells of the ROM in the data line direction is increased to the main word line MWL pitch, a defective column address ROM is provided for each sub-word line SWL. Cells and redundant cells can be replaced. For example, in the sub word line SWL10 corresponding to the main word line MWL1, the memory cell MC at the intersection with the column address YS2 is replaced with a redundant cell RMC, and in the sub word line SWL13 of the same main word line MWL1, the intersection with a different column address YS1. Can be replaced with a redundant cell RMC. This is an efficient replacement method when a defect in a wafer affects only one cell.

FIG. 6 is a plan view showing one embodiment of a ROM using the wiring program element according to the present invention. In the figure, the lower layer pattern is shown in (a),
(B) shows an upper layer (uppermost layer wiring) pattern. 7A is a cross-sectional view of FIG. 7B, and FIG. 7B is a BB ′ cross-sectional view of FIG.

L is a MOSFET composed of n + regions
FG, which extends in the lateral direction so as to be sandwiched between them, is a gate electrode and constitutes a word line of the ROM. M1 is a first layer metal wiring, M2 is a second layer metal wiring, and M3 is a third layer (top layer) metal wiring. The active region (source) sandwiched between the pair of word lines is one in which the sources of the two MOSFETs corresponding to the pair of word lines are shared.
The ground potential Vss of the circuit connected to M1 through T
Is given.

The drain side of the MOSFET is connected to a first metal layer M1 through a contact hole CONT, and this metal layer M1 is connected to a second metal layer M1 through a through hole TC1.
The third metal layer M3 is connected to the third metal layer M2 via the through hole TC2. In the cross-sectional view of FIG. 7, INS1 is an interlayer insulating film for separating the active region L or FG from M1.
S2, IN3 An interlayer insulating film separating M1 and M2, INS4 is an interlayer insulating film separating M2 and M3, and INS5 and INS5 are protective films of M3.

In FIG. 6B, M3 and TC2
Is shown. The above-mentioned M3 is used as a bit line BL of the ROM, and a portion surrounded by oblique lines is a cutting region, and forms a wiring program element HP. FIG. 6A is stacked below FIG. 6B such that the through holes TC2 indicated by arrows overlap in the direction perpendicular to the substrate. That is, one of the wiring program elements HP is connected to the third-layer metal layer M3 extending in the vertical direction forming the bit line BL, and the other end is connected to the second-layer metal layer M2 through the through hole TC2. M2, and the metal layer M2 is connected to the first metal layer M1 via the through hole TC1. The first metal layer M1 is connected to the active region L of the MOSFET through the contact hole CONT.
(Drain).

FIG. 8 is a sectional view of a DRAM memory cell. SN is a lower electrode of the storage capacitor, INC is a capacitive insulating film (dielectric) of the storage capacitor, and TG is a plate electrode of the storage capacitor. SCONT is a through hole that connects the source and drain (active region L) of the selection MOSFET and the storage capacitor lower electrode SN. INS2 is an interlayer insulating film separating M1 and SN, and INS3 is an interlayer insulating film separating TG and M2. As can be seen from the comparison with FIG. 7, the wiring program type ROM according to the present invention adds another layer only by adding the EB lithography of the final metal layer to the DRAM process of FIG. It can be created without anything.

In the embodiment of FIGS. 3 and 5, the DRAM is used.
A row decoder is arranged on the right side of the array, and a defective column address ROM is arranged on the left side. As an example, the second word metal wiring (aluminum) is connected to the main word line MWL in the DRAM array.
Assuming that the third layer metal wiring is used for the column selection line YS using M2, the wiring of the main word line MWL composed of the second metal layer M2 in the boundary area between the DRAM array and the defective column address ROM. The layer is connected to the first polysilicon layer FG via a through hole, and is connected to the word line of the defective column address ROM. With such an arrangement, the word lines in the defective column address ROM are laid out only by the FGs and need not be passed through the second-layer metal wirings M2. There are advantages that can be.

Conversely, the pitch of the second-layer metal wiring M2 can be reduced, and the word line in the defective column address ROM passes through the first-layer polysilicon layer FG and the second-layer metal wiring layer M2. If this is possible, a defective column address ROM may be arranged between the row decoder and the DRAM array. In this case, there is an advantage that the word line of the defective column address ROM is activated quickly, and the redundancy judgment is performed at high speed.

The hierarchical word type bit-by-bit repair of the present invention can be combined with a conventional redundancy method by row replacement and column replacement using open fuses. If a defect is found in the unit of a word line or a YS line, it is replaced with a redundant row or column, and a random defect is finely replaced using a hierarchical word type bit-by-bit repair. By changing the rescue method depending on the failure mode,
Relief efficiency can be increased.

FIG. 9 is a flowchart for explaining a method of manufacturing a semiconductor integrated circuit device having the above-mentioned wiring program element. In the step (a), an uppermost layer (for example, M3) is formed. That is, in the step of forming the uppermost layer M3, the wiring program element is also formed.
In this step (a), a surface protection film (the first insulating film) is formed except on the bonding pad. In the step (b), an operation test using a wafer probe is performed. In the step (b), when the surface protective film does not have sufficient water resistance, the operation test is performed in a dry atmosphere.

In the step (c), processing of the program element, that is, an opening is formed in the resist above the wiring program element to be cut by EB lithography EB in accordance with the above test result, and dry etching is performed using the opening as a mask. The cut portion of the wiring program element is exposed, and the exposed cut portion of the wiring program element is etched and cut.
In the step (d), an insulating film is formed as a surface protective film except for the bonding pad portion. In step (e),
Dicing is performed, and the semiconductor chips formed on the wafer are divided individually. In the step (f), the divided semiconductor chips are sorted out and packaged as non-defective products. In the step (g), initial defects are washed out by aging or burn-in, and those which are determined to be good by the final test are shipped.

FIG. 10 is a circuit diagram showing another embodiment of the present invention. In this embodiment, a wiring cutting process using EB lithography is used for trimming a circuit. In the wafer probing process, the timing of the circuit on the created wafer is measured. Based on this result, the wiring program element is cut in order to adjust necessary timing in the circuit. In the wiring program type variable delay circuit shown in FIG. 3, the delay time can be adjusted by selectively cutting the wiring program element.

In this embodiment, the input signal IN is connected to the input terminal of the inverter circuit INV1 at the input stage. The inverter circuit INV1 includes four inverters having four different output impedances, such as G1, G2, G4, and G8, connected in parallel, and inputs are commonly connected. The outputs of the individual inverters G1, G2, G4 and G8 are commonly connected via a wiring program element. The inverter circuits G1, G2. The G4 and G8 current driving forces are set to have binary weights such as 1: 2: 4: 8. For example, if the inverter circuit G1 is a unit circuit, the inverter circuit G2 is configured by connecting the two unit circuits in parallel, the inverter circuit G4 is configured by connecting the four unit circuits in parallel, and the inverter circuit G8 is configured by Eight unit circuits are connected in parallel. From another point of view, the MOSF constituting the inverter circuit G1
If the ET is used as a reference, the MOSFETs constituting the inverter circuits G2, G4 and G8 are formed to have twice, four and eight times the size (channel width).

The output of the inverter circuit INV1 is
MOS capacitors C1, C2, C4 and C8 are selectively connected via a wiring program element. These capacitance values are formed with binary weights such as 1: 2: 4: 8. The output of the inverter circuit INV1 is connected to the input of an output inverter circuit INV2 for performing waveform shaping, and the output of the inverter circuit INV2 is used as an output terminal OUT. When the wafer is created, all the wiring program elements are connected. To slow down the variable delay circuit, the inverter circuits G1, G2, G4,
The wiring program element connected to G8 is disconnected. Depending on the combination of wiring program elements to be cut,
A delay amount up to 15 times the initial value can be obtained. Conversely, in order to speed up the variable delay circuit, the capacitors C1, C2, C4, C8
Disconnect the wiring program element connected to. Depending on the combination of the wiring program elements to be cut, a delay amount up to 1/15 of the initial value can be obtained.

FIG. 11 is a block diagram showing a case where the wiring program type variable delay circuit of the present invention is applied to an SMD (Synchronous Mirror Delay) circuit. The SMD circuit is described in February 1996, AEE International Solid-State Circuits Conference, Digest of Technical Papers, page 374 (1996 IEEE International
Solid-State Circuits Conference Digest of Technical
Papers). This is a kind of a clock recovery circuit, and is a circuit for obtaining a clock inside a chip having the same phase as an external clock. In this circuit, with respect to the delay d1 of the input buffer and the delay d2 of the clock driver,
A dummy delay circuit that generates a delay of d1 + d2 is important. The dummy delay circuit is designed to simulate the original circuit configuration of the input buffer and the clock driver in order to generate d1 + d2. However, due to process variations, the delay amounts of these circuits are different from each other. In some cases.

Therefore, a wiring program type variable delay circuit is used for the dummy delay circuit. In this circuit,
During the wafer probe, the phase difference between the external clock and the internal clock is measured, and the delay amount of the dummy delay can be programmed so as to match the phase difference. If the phases of the external clock and the internal clock match exactly as described above, the timing margin when transferring data between chips can be reduced. Therefore, the high-speed circuit can be operated stably by trimming the circuit.

The wiring program type variable delay circuit as shown in FIG. 10 can be used, for example, as a timer circuit for determining a refresh cycle of a dynamic RAM. That is, the shortest information retention time of the memory cell is checked by the probing process, and the refresh cycle is set within the retention time. By doing so, it is possible to reduce the power consumption in the data holding state as compared with the conventional case where the refresh cycle is set to be shorter than the capability of the information holding time of the memory cell with a time margin. Can be.

FIGS. 12 and 13 are schematic circuit diagrams showing one embodiment of a part of the dynamic RAM according to the present invention. FIG. 12 shows a memory array section, and FIG. 13 shows a power supply circuit. Address and data input / output interfaces, column-related selection circuits, control circuits, and the like that constitute the dynamic RAM are omitted.

In FIG. 12, dynamic memory cells include word lines W1 to W3... Wn provided in one memory array MAC exemplarily shown as a representative.
One of two pairs of complementary bit lines (same as data line DL in FIG. 3 and the like) bit and / bit or / bit
The eight provided between are illustratively shown as representatives. The dynamic memory cell has an address selection MOS
It comprises an FET Qm and a storage capacitor Cs. The gate of the address selection MOSFET Qm is connected to the corresponding word line W1 and the like, the drain of the MOSFET Qm is connected to the corresponding bit line bit and the like, and the storage capacitor Cs is connected to the source. The other electrode of the storage capacitor Cs is shared and receives a plate voltage. In the DRAM of this embodiment, the selection level of the word line W1 or the like is a high voltage VCH which is higher than the high level of the bit line bit or the like by the threshold voltage of the address selection MOSFET Qm. The non-selection level of the word line is a negative voltage VNN which is lower than the ground potential VSS of the circuit.

The sense amplifier described below is connected to the internal step-down voltage VD
When operating at L, the high level amplified by the sense amplifier SA described below and applied to the bit line is set to a level corresponding to the internal voltage VDL. Therefore, the high voltage VCH corresponding to the word line selection level is set to a high voltage such as VDL + Vth. The input / output node of the sense amplifier SA is connected to the pair of complementary bit lines bit and / bit. The complementary bit lines bit and / bit are arranged so as to extend in parallel as shown in the figure, and are appropriately crossed as necessary in order to balance capacitance and the like. The complementary bit lines bit and / bit are connected to the shared switch MOSF when the sense amplifier employs the shared sense method.
ET is connected to the input / output node of the unit circuit of the sense amplifier SA.

The unit circuit of the sense amplifier SA is composed of N-channel type amplifying MOSFETs Q4, Q5 and P-channel type amplifying MOSFETs Q6, Q7, whose gates and drains are cross-connected to form a latch. The sources of the N-channel MOSFETs Q4 and Q5 are connected to a common source line, and the ground potential VSS of the circuit is supplied to the common source line via the N-channel power switch MOSFET Q8 at the operation timing of the sense amplifier. P-channel type MOSFE
The sources of TQ6 and Q7 are connected to a common source line, and the common source line has a P-channel type power switch MOSFET Q at the operation timing of the sense amplifier.
9, the internal step-down voltage VDL is supplied.

Although not particularly limited, the operating voltage on the high level side of the sense amplifier is set between the start of the amplification operation and before the amplified signal of the bit line reaches the voltage VDL in order to achieve a high-speed operation of the sense amplifier. An overdrive that temporarily supplies a high voltage such as VCH may be used. That is, a P-channel MOSFET may be provided in parallel with the MOSFET Q9, and the P-channel MOSFET may be turned on temporarily at the start of the amplification operation of the sense amplifier to supply the high voltage VCH. A wiring program type variable delay circuit can be used for such overdrive time adjustment.

An equalizing MOSF for short-circuiting a complementary bit line is connected to an input / output node of the unit circuit of the sense amplifier.
ETQ1 and switch MOSF for supplying half precharge voltage VDL / 2 to complementary bit lines bit and / bit
A precharge circuit including ETQ2 and Q3 is provided. The gates of these MOSFETs Q1 to Q3 are commonly supplied with an equalize (or precharge) signal EQ. The driver circuit for forming the equalizing signal EQ has a selection level of VCH and a non-selection level of a negative voltage such as VNN, like the word driver WD1 for driving the word lines W1 to W3. .

On the other hand, a power switch MOSFET Q for supplying the ground potential of the circuit to the sense amplifier SA
8 drives the internal voltage VDL.
And the above-mentioned negative voltage VNN to form a drive operation signal SAN having a high level such as an internal step-down voltage and a low level such as the negative voltage VNN. The above sense amplifier SA
Switch MOS for supplying internal step-down voltage VDL to the power supply
The driver SAPD that drives the FET Q9 generates a drive signal SAP having a high level such as the high voltage VCH and a low level such as the circuit ground potential VSS.

Although not particularly limited, the memory array MAC
Is applied with a substrate voltage VBB that is lower than the negative voltage VNN.
A voltage higher than the high voltage VCH is applied to the N-type well region where the P-type MOSFET forming the sense amplifier is connected to the deep N-type well region where the type well region is formed. High voltage VPP is applied. The voltage VBB and the voltage VPP are each formed by a charge pump circuit.

An X decoder XDEC for forming a selection signal for the word line W1 and the like, a word driver WD, and an array control circuit AC are included in the precharge signal EQ.
VCH, VDL, VSS, and VNN are supplied as the above-mentioned operating voltages to the driver forming the driver and the drivers SAND and SANP forming the drive signal of the sense amplifier.
A high voltage VCPP is applied as a bias voltage to the N-type well region where the T is formed, and an N-channel type MOSFET is formed.
A negative voltage VBB is applied to the P-type well region or the P-type substrate where the T is formed.

In FIG. 13, high voltage VPP is formed by high voltage generating circuit VPPG. The high voltage generation circuit VPPG includes an oscillation circuit (OSC) 1, a charge pump circuit (Charge pump circuit) 2, and a level sensor (Leve).
l Sensor) 3 and the charge pump circuit 2
Receives the oscillation pulse generated by the oscillation circuit 1 and generates a high voltage by a charge pump operation. The level sensor 3 performs a level sensing operation to stabilize the high voltage VPP to a desired high voltage, and controls the operation of the oscillation circuit 1 intermittently. That is, the oscillation operation is stopped when the high voltage VPP reaches a desired high voltage, and the oscillation circuit 1 is operated when the high voltage VPP decreases.

The high voltage VPP is set higher than the high voltage VCH corresponding to the selected level of the word line W1 or the like. For example, as shown in the operation waveform diagram of FIG. 3, when the word line selection voltage VCH is set to 2.25 V, the high voltage VPP is set to a high voltage such as 2.6 V. An extra high voltage is formed with respect to the required voltage VCH, and the reference voltage generation circuit RGFP is operated based on the high voltage VPP. This reference voltage generating circuit RGFP converts a constant current Ip to a P-channel type M
The current flows to a resistor Rp based on the internal voltage VDL (or the external power supply voltage Vext) via a current mirror circuit including OSFETs Q10 and Q11, and the address selection MO is controlled.
A voltage corresponding to the threshold voltage Vth of the SFET Qm is generated. Thus, the reference voltage VRH is set to a voltage corresponding to VDL (or Vext) + Vth.

The constant voltage generation circuit RGP is provided with the high voltage VP
A P-channel MOSFET Q12 as a variable resistance element provided between P and an internal high voltage VCH, and a differential amplifier circuit 4 receiving the reference voltage VRH and the internal high voltage VCH, and The output signal of the amplifier circuit 4 is supplied to the gate of the MOSFET Q12.
If the internal high voltage VCH is to be lowered with respect to the reference voltage VRH, a signal that changes to low level is formed to reduce the resistance value of the MOSFET Q12 so that they match each other. Internal high voltage V
When CH becomes high, a signal that changes to a high level is formed to increase the resistance value of the MOSFET Q12 and control the two so that they match.

The negative voltage VBB is applied to the negative voltage generation circuit VBBG
Formed by The negative voltage generation circuit VBBG includes the above-described oscillation circuit (OSC) 6, a charge pump circuit (Negative Charge pump circuit) 7, and a level sensor (Level Sensor) 8. The charge pump circuit 7 Upon receiving the oscillation pulse formed by the oscillation circuit 6, a negative voltage is generated by a charge pump operation. A level sensing operation is performed by the level sensor 8 so that the negative voltage VBB is stabilized at a desired negative voltage.
The operation of the oscillation circuit 6 is intermittently controlled. That is, when the negative voltage VBB reaches a desired negative voltage, the oscillating operation is stopped, and when the negative voltage decreases in absolute value, the oscillating circuit 6 is operated again.

The negative voltage VBB is set to a voltage which is absolutely higher than the negative voltage VNN corresponding to the non-selection level of the word line W1 or the like. For example, as shown in the operation waveform diagram of FIG.
If set to 75V, the negative voltage VBB is -1.1V
Is set to a voltage which is large in absolute value as shown in FIG. An extra large voltage is formed in the negative direction with respect to the necessary voltage VNN, and the reference voltage generating circuit RGFN is operated based on the negative voltage VBB in the same manner as described above. This reference voltage generating circuit RGFN supplies a constant current In to an N-channel type M
A current flows through a current mirror circuit composed of OSFETs Q13 and Q14 to a resistor Rn based on the ground potential VSS of the circuit to generate a reverse bias voltage VRN applied between the gate and source of the MOSFET Qm for address selection. In this embodiment, as described above, the voltage VRN is set to -0.0.
It is a negative voltage such as 75V.

The constant voltage generating circuit RGN is connected to the negative voltage VB.
B, an N-channel MOSFET Q15 as a variable resistance element provided between the internal negative voltage VNN and a differential amplifier circuit 9 receiving the reference voltage VRN and the internal negative voltage VNN. The output signal of the dynamic amplifier 9 is supplied to the gate of the MOSFET Q15. If the internal high voltage VNN is to be reduced in absolute value with respect to the reference voltage VRN, a signal that changes to a high level is formed to reduce the resistance value of the MOSFET Q15 so that the two match, and conversely, the reference voltage VRN In contrast, when the internal negative voltage VNN tends to increase in absolute value, a signal which changes to a low level is formed and the MOSF
The control is performed so that the resistance value of the ETQ 15 is increased and the two are made to coincide with each other.

Constant voltage generating circuit (Voltage regurator) 5
Receives the external voltage Vext supplied from the external terminal,
The internal step-down voltage VDL is generated by a circuit similar to the constant voltage generation circuit RGP. This constant voltage generation circuit 5 is not always required. Peripheral circuits such as the sense amplifier and the address selection circuit may be operated by an external voltage Vext supplied from an external terminal. In this case, the level of the internal high voltage VCH is formed based on the external voltage Vext as described above. Even when the constant voltage generating circuit 5 is provided, the constant voltage VDL may be used as an operating voltage of the sense amplifier, and internal circuits such as an address buffer and an address decoder may be operated by the external voltage Vext.

The charge pump circuit 2 or 7 as described above
The voltages VPP and VBB formed in the steps (1) and (2) are held in the electric charge accumulated in the parasitic capacitance or the like. sometimes,
As described above, the current greatly varies depending on a current for charging up or discharging a word line having a relatively large parasitic capacitance due to the connection of a large number of memory cells. In consideration of such a voltage fluctuation, when the selection level or the non-selection level of the word line is set, a gate insulating film of an address selection MOSFET connected to the word line and a word driver for driving the word line are formed. It is necessary to increase the breakdown voltage in response to the application of a large voltage to the gate insulating film of the output MOSFET by the amount of the above-mentioned level fluctuation.

On the other hand, in the present invention, when the selection level and the non-selection level of the word line are formed through the above-described constant voltage circuits RGP and RGN, the word line is not selected as described above. When switching from a selected level to a selected level or vice versa, a large number of memory cells are connected to charge or discharge a word line having a relatively large parasitic capacitance. VPP and VBB fluctuate in the same manner depending on the current, but the MOSFET Q as a variable resistor of the constant voltage circuit RGP or RGN is used.
12 and Q15 change to absorb the voltage fluctuation, so that the substantially constant voltages VCH and VN
N can be secured.

The internal high voltage VCH and the high voltage VPP
, The internal negative voltage VNN and the negative voltage VBB
Are formed so as to compensate for output voltage fluctuations of the charge pump circuits 2 and 7 corresponding to the word line drive current, respectively. Thereby, the output MOSFET of the word driver WD and the address selection M of the memory cell are selected.
The voltage applied to the gate insulating film of the OSFET is a relatively small voltage determined by the stabilized voltages VCH and VNN, so that it is not necessary to perform extra high withstand voltage in consideration of the above-described voltage fluctuation.

FIG. 14 is a waveform chart for explaining a schematic operation of the dynamic RAM according to the present invention. FIG. 2 mainly shows a memory cell selecting operation. The equalizing signal EQ is at a high level such as the internal high voltage VCH when the memory cell is in the information holding state. Thereby, the MOSFET Q1
To Q3 are turned on, and complementary bit lines bit, / bit
And the half precharge voltage VDL
/ 2. Since the complementary bit lines bit and / bit are set to the half precharge voltage VDL / 2, the level of the equalize signal EQ is not problematic for the operation itself even at a low potential such as VDL. By using the voltage VCH, the MOSF
The on-resistance of the ETQ1 can be reduced to short-circuit the high level / low level of the complementary bit lines bit and / bit in a short time to set the intermediate potential VDL / 2.

At the time of memory access, the equalize signal EQ changes from high level to low level. At this time, the low level of the equalize signal EQ is not the ground potential of the circuit but the negative voltage VNN. The reason for this is
The gate insulating films of the MOSFETs Q1 to Q3 are formed to be thinner than the gate insulating films of the address selection MOSFETs, and the threshold voltage thereof is reduced. The voltage VNN is supplied to prevent a leak current flowing between the drain and the source.

As described above, sense amplifier activation signal SA
In the case of N, the sense amplifier is set to the above-mentioned negative voltage VNN when the sense amplifier is not operating, thereby preventing a leak current from flowing to the power switch MOSFET Q8 to which the negative voltage is supplied.
That is, the gate insulating film of the MOSFET Q8 is also formed to be thin as described above, and has a low threshold voltage. By using such a MOSFET having a low threshold voltage, a relatively large current can flow when the MOSFET is put into an operation state, and the amplification operation of the sense amplifier is speeded up. This means that the P-channel MOSFET Q
Similarly, when the sense amplifier is in a non-operation state, the internal high voltage VCH is set to prevent the leakage current from flowing to the power switch MOSFET Q9 to which the voltage is supplied.

After the equalizing signal EQ is set to a non-selection level such as the negative voltage VNN, the word line Wi is set to a high-level selection state such as the internal high voltage VCH. Thereby, the memory cell address selection MOSFE
TQm is turned on, and charge is dispersed between the information storage capacitor Cs and the parasitic capacitance of the bit line bit or / bit at the half precharge potential VDL / 2. For example, the charge is stored in the information storage capacitor Cs. When there is no state, the potential of the bit line connected to the memory cell decreases as shown in FIG.

The sense amplifier activation signal SAN rises from the negative voltage VNN to the internal step-down voltage VDL as described above, turns on the M-channel MOSFET Q8, and gives a low-level operating voltage such as the ground potential of the circuit. The sense amplifier activation signal SAP falls from the internal high voltage VCH to a low level such as the ground potential VSS of the circuit, and turns on the P-channel MOSFET Q9 to turn on a high-level operating voltage such as the internal step-down voltage VDL. give. As described above, the MOSFETs Q8 and Q
Reference numeral 9 designates a low threshold voltage due to the thin gate insulating film, so that when turned on, a relatively large current flows to speed up the amplification operation of the sense amplifier. Due to the amplification operation of the sense amplifier, the potentials of the complementary bit lines bit and / bit are amplified to a high level such as the internal step-down voltage VDL and a low level such as the ground potential of the circuit due to an increase in the potential difference read from the memory cell. Is done.

By the amplification operation of the sense amplifier as described above, the word line Wi is connected to the bit line bit or / bit by the operation of selecting the word line Wi in accordance with the high level and the low level of the complementary bit lines bit and / bit. The low level corresponding to the original storage charge state is rewritten to the storage capacitor Cs of the memory cell in which the memory cell is located. Upon completion of the memory access, the word line Wi falls from the internal high voltage VCH to the negative voltage VNN, and thereafter, the equalizing signal EQ rises from the negative voltage VNN to the internal high voltage VCH, and the complementary bit lines bit and / b
The high level / low level of it is short-circuited to the half precharge voltage VDL / 2. In order to prevent the half precharge voltage VDL / 2 formed as described above from fluctuating due to the leak current, the MOSFETs Q2 and Q
3 is provided, and the half precharge voltage VDL / 2 is changed by the ON state to the complementary bit lines bit and / b.
It tells it.

When the selection / non-selection level of the word line is set by the internal voltages VCH and VNN as described above, for example, if an insulation failure occurs between the word line and the bit line, a connection to a spare word line (not shown) is made. Even if the defect is relieved by switching, a direct current flows through the defect and the load of the negative voltage VNN is increased. In the worst case, it is difficult to secure the necessary level. If the potential of VNN rises, the leakage current of the memory cell increases, so that a necessary information holding time cannot be secured. Therefore, in this embodiment,
The wiring program element HP is provided for the word lines W1 to Wn and the like, and the word line having the above-described defect is cut off.

FIG. 15 is a circuit diagram showing one embodiment of the word driver in the hierarchical word DRAM according to the present invention. The word driver of this embodiment includes a row decoder MWL (main word line) control circuit, a main word driver MWD, and a sub-word driver SWD. When there is no defect in sub word line SWL, MW
The wiring program element HP1 provided in the L control circuit and the wiring program element HP2 provided in the negative voltage VNN of the main word driver MWD are not disconnected.

Since the wiring program element HP1 provided in the MWL control circuit is not disconnected, the power supply voltage VCC
Is transmitted to the input of the inverter circuit, and the output signal is set to the low level. Therefore, MOSFET Q11 is turned off. The P-channel MOSFET Q13 is turned on and the N-channel MOSFET Q12 is turned off by the low level of the output signal of the inverter circuit. The N-channel MOSFET Q1 is turned on by the high-level output of the inverter circuit receiving the low-level signal.
4 is turned on. As a result, the row decoder selection signal MD is transmitted to the input of the main word driver MWD through the MOSFETs Q13 and Q14.

In the main word driver MWD, the high level side of the row decode signal MD consisting of a high level such as VDL and a low level such as VSS is applied by a level conversion circuit comprising MOSFETs Q15 to Q20 provided on the input side. The level is converted to a high level such as VCH. The output signal of the input side level conversion circuit is converted from a low level such as VSS to a low level corresponding to the negative voltage VNN by a level conversion circuit provided on the output side and including MOSFETs Q21 to Q26. Accordingly, the output signal of the level conversion circuit on the output side has a signal amplitude corresponding to the VCH and VNN,
Inverter circuit IN operating at the above voltages VCH and VNN
V2 is transmitted to drive the main word line MWLB.

When the main word line MW is not selected,
LB becomes a high level such as VCH, the N-channel MOSFET Q27 of the sub-word driver SWD is turned on, and the sub-word line SWL is set to a negative voltage such as the negative voltage VNN. For example, the main word line MW
When LB is at a selection level such as a low level, the P-channel MOSFET Q29 is turned on. At this time, if the sub-word selection line FX is at a low level and FXB is at a high level, the N-channel MOSFET Q28 is turned on and the sub-word line SWL is turned on. Is set to the negative voltage VNN.

When the main word line MWLB is at a low level such as the negative voltage VNN as described above, the N-channel MOSFET Q27 of the sub-word driver SWD
Is turned off, the P-channel MOSFET Q29 is turned on, and a high level such as VCH of the sub-word select line FX is transmitted to the sub-word line SWL through the on-state MOSFET Q29. At this time, the N-channel MOSFET Q28 is turned off by the low level of the FXB.

When there is a defect in main word line MWLB, the defective main word line is replaced with a redundant main word line by row replacement (not shown). Further, the wiring program elements HP1 and HP2 are disconnected. After the signal LR of the MWL control circuit has been input from the RAS signal,
It becomes a high level like CC and is temporarily turned on. As a result, if the wiring program element HP1 is disconnected, the input signal of the inverter circuit goes low, the output signal goes high, and the N-channel MOSFET Q11 is turned on to latch the low level. Thereby, the MOSFET Q12
Is turned on, the signal input to the main word driver MWD is fixed at a low level, and the MO
The SFETs Q13 and Q14 are turned off.

The main word line MWLB is set to a high level such as VCH in response to the low level input signal. As a result, the P-channel MOSFET Q29 of the sub-word driver SWD is turned off, and the output is put into the high impedance state. A wiring for supplying a negative voltage to the sub-word driver SWD extends in parallel with the main word line MWLB, and receives a negative voltage VNN from the main word driver. The wiring program element HP2 is provided in the supply path of the negative voltage VNN, and is cut off in response to a defect of the main word line. Thereby, even if insulation failure exists between the sub-word line SWL and the complementary bit line crossing it,
Since the current path as described above is interrupted, the VCH generation circuit and the VNN generation circuit are not affected at all.

The effects obtained from the above embodiment are as follows. That is, (1) a semiconductor integrated circuit device including an electronic circuit having a desired circuit function and a pad used for inputting and outputting an operating voltage and a signal of the electronic circuit. A first insulating film formed of an uppermost wiring layer, the wiring program element forming a part of a wiring path and being selectively cut in accordance with an electrical test result of the electronic circuit; A surface of the first insulating film excluding a program wiring portion having a cut surface etched and removed by using the selective opening portion and an upper surface of the pad;
The cut surface of the program wiring portion, and the opening portion formed by using a resist film opening corresponding to the photosensitive portion by irradiating an electron beam or a light spot corresponding to the test result used for cutting the same. By being configured with the second insulating film covering the opening surface, it is configured with a fine element size,
The effect is obtained that a semiconductor integrated circuit device equipped with a wiring program element that can be selectively cut in a short time can be obtained.

(2) Since the uppermost wiring layer is a metal wiring layer and utilizes a wiring layer formed in the same step as the bonding pad, the processing size is relatively large, and the EB lithography is used. Cutting (programming) can be easily performed, and water resistance as a surface protection film can be ensured by using the second insulating film as a final passivation film.

(3) By using a dry etching technique for selectively cutting the program wiring portion in the wiring program element, the plasma power can be reduced because the wiring portion is the uppermost metal layer,
The effect that the damage to the device can be reduced is obtained.

(4) One end of the wiring program element is connected to the bit line, and the other end is connected to the ground potential of the circuit through the drain-source path of the MOSFET.
The gate of the OSFET is connected to a word line, and the plurality of word lines and the plurality of bit lines are arranged so as to be orthogonal to each other.
By providing a ROM array by providing a memory cell composed of the following, an effect that a program corresponding to an operation test result of an electronic circuit can be performed at high density can be obtained.

(5) A plurality of dynamic memory cells each having a length divided in the direction of extension of a main word line and a plurality of bit lines arranged in the direction of a bit line intersecting the main word line. Sense amplifier, redundant input / output line, and main amplifier in which an input / output terminal is connected to the redundant complementary bit line pair in the hierarchical word line type dynamic RAM having a sub-word line to which the address selection terminal is connected. And geometrically extending the address of the bit line where the defective cell exists among the sub-word lines corresponding to the main word line to the ROM address line for defective address storage which is geometrically extended. A plurality of memory cells for storing are provided, and a read signal and a bit line selection address signal are compared with each other by a match detection signal. By controlling the letter and outputting the signal of the redundant main amplifier in place of the normal main amplifier, a defective address can be obtained by using a relatively large size ROM cell using the relatively wide pitch of the main word line. The effect of being able to memorize is obtained.

(6) By using the wiring program element as a memory cell for storing the address of the defective bit line, the ROM can be formed with a sufficient margin, and the selective cutting thereof can be easily performed. The effect is obtained.

(7) A plurality of ROM bit lines and ROM word lines are provided corresponding to the sub-word selection lines, and a plurality of ROM outputs are selected through a selector controlled by the sub-word selection lines. By supplying the data to the comparison circuit, it is possible to obtain an effect that the defect can be relieved for each sub-word line.

(8) A main word driver is disposed at one end of the main word line, and a ROM storing the defective address is disposed at the other end of the main word line.
The effect that wiring at the boundary between the section and the ROM section can be easily performed is obtained.

(9) Since the wiring program element is used to cut off a DC current path due to insulation failure between wirings, the effect that DC failure can be remedied can be obtained.

(10) By using a silicon oxide film, a silicon nitride film laminated on the surface thereof, and a PIQ film laminated on the surface of the second insulating film, sufficient water resistance can be obtained. Is obtained.

(11) As a method of manufacturing a wiring program element, (1) a circuit having a desired circuit function is provided.
A semiconductor circuit is provided in which a wiring path to be selectively cut is guided to a program wiring portion composed of an uppermost wiring layer and is covered with a first insulating film except for a pad portion leading to an external terminal. (2) input and output of operating voltage and signal through the pad portion, and test whether the electronic circuit formed on the semiconductor wafer has a desired circuit function, (3) (4) forming a resist film on the surface of the electronic circuit and selectively removing the resist film by irradiating an electron beam or a light spot on the program wiring portion in accordance with the test result; Forming an opening in the first insulating film using the film as a mask, and (5) etching away the program wiring portion corresponding to the opening using the first insulating film as a mask and cutting it.
(6) By forming a second insulating film that covers the first insulating film and the opening surface thereof and the cut surface of the program wiring portion except for the surface of the pad portion and has water resistance,
An effect is obtained that a wiring program element configured with a fine element size and capable of selectively cutting in a relatively short time can be formed.

(12) In the etching of the program wiring portion in the above step (6), by using a dry etching technique using plasma, the effect is obtained that the plasma power can be reduced and the damage to the device can be reduced.

(13) The second insulating film is formed of plasma C
A silicon nitride film is deposited by a plasma CVD method on a silicon oxide film deposited by the VD method, and P
By forming an IQ stacked film, an effect that a sufficient function as a surface protective film can be obtained can be obtained.

The invention made by the present inventor has been specifically described based on the embodiments. However, the invention of the present application is not limited to the above-described embodiments, and can be variously modified without departing from the gist of the invention. Needless to say. For example, the wiring program element uses the fourth metal wiring layer if a four-layer metal wiring structure is adopted, in addition to the third metal layer,
If a five-layer metal wiring structure is adopted, a fifth metal wiring layer may be used. The metal wiring material employs various embodiments in which, in addition to aluminum, an alloy containing another metal as a main component or a multilayer structure in which another metal layer is formed above or below the aluminum layer. Can be. Means for selectively exposing a resist used to form an opening in the insulating film formed on the uppermost wiring layer includes those using the electron beam (EB) as well as those using the electron beam (EB). The irradiation may be performed by irradiating a laser beam in a spot shape.

The wiring program element is used for the above-described defect remedy technique, for adjusting the delay time of a delay circuit or the like, or for adjusting the resistance value of a resistor element or the capacitance value of a capacitor, or a dynamic type. RAM
In semiconductor memory devices such as the above, it is used for wiring switching to determine the input / output bit configuration, or used as a ROM for storing product information, operating conditions, product lots, etc. of the semiconductor integrated circuit device, and address terminals or data terminals are used. It may be used to read it out by using it. The setting of the storage information reading mode may be performed by a combination of control signals or by setting a specific control terminal to a high voltage that is not normally used. INDUSTRIAL APPLICABILITY The present invention can be widely used as a semiconductor integrated circuit device equipped with a wiring program element and a method of manufacturing the same.

[0109]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a semiconductor integrated circuit device including an electronic circuit having a desired circuit function and a pad used for inputting and outputting an operation voltage and a signal of the electronic circuit, a wiring path of the electronic circuit is provided. A wiring program element, which forms a part and is selectively cut in accordance with an electrical test result of the electronic circuit, is constituted by an uppermost wiring layer, and is selectively provided by a first insulating film formed thereon. The surface of the first insulating film excluding the upper surface of the program wiring portion and the pad, the cutting surface of the program wiring portion, and A second insulating film covering the opening surface of the opening formed by using a resist film opening corresponding to the photosensitive portion by irradiating an electron beam or a light spot in accordance with a test result. More, consists of a fine element size, it is possible to obtain a semiconductor integrated circuit device equipped with the wiring program elements that are possible in a short time be selectively cleaved.

[Brief description of the drawings]

FIG. 1 is an element sectional view showing an example for explaining a method of manufacturing a wiring program element according to the present invention.

FIG. 2 is a schematic layout diagram showing one embodiment of a dynamic RAM to which the present invention is applied.

FIG. 3 is a schematic circuit diagram showing one embodiment of a dynamic RAM to which the present invention is applied.

FIG. 4 is a circuit diagram showing an embodiment in which the defective column address ROM of FIG. 3 is configured using the wiring program element.

FIG. 5 is a schematic circuit diagram showing another embodiment of the dynamic RAM to which the present invention is applied.

FIG. 6 is a graph showing an R value using the wiring program element according to the present invention;
It is a top view which shows one Example of OM.

FIG. 7 is a sectional view of the element structure corresponding to the plan view of FIG. 6;

FIG. 8 is a sectional view showing one embodiment of a DRAM memory cell to which the present invention is applied;

FIG. 9 is a flowchart for explaining a method of manufacturing a semiconductor integrated circuit device provided with a wiring program element according to the present invention.

FIG. 10 is a circuit diagram of a wiring program type variable delay circuit showing another embodiment of the present invention.

11 is a block diagram of an SMD circuit using the wiring program type variable delay circuit of FIG.

FIG. 12 is a schematic circuit diagram showing a memory array section of another embodiment of the dynamic RAM according to the present invention.

FIG. 13 is a schematic circuit diagram of a power supply circuit unit showing another embodiment of the power supply circuit unit of the dynamic RAM according to the present invention.

FIG. 14 is a waveform chart for explaining a schematic operation of the dynamic RAM according to the present invention.

FIG. 15 is a circuit diagram showing one embodiment of a word driver in the hierarchical word DRAM according to the present invention.

[Explanation of symbols]

M1 to M3: metal wiring layer, INS1 to INS6: insulating film, MC: memory cell, CB: cell block, DL: data line, SWL: sub-word line, MWL: main word line, SA: sense amplifier, SWD: sub-word driver , I / O: input / output line, YS: Y selection line, RI / O: redundant input / output line, RYS: redundant Y selection line, RMC: ROM
Memory cells, RSA… ROM sense amplifiers, BL…
ROM bit line, HRE: ROM activation wiring program element, PC: precharge signal, HP: wiring program element, FX: sub word selection line, MCA: memory cell array, XDEC: X decoder, WD: word driver, AC ... Array control circuit, SAND, SAPD: Driver for sense amplifier, W1 to Wn: Word line, 1: VP
P oscillation circuit, 2 ... VPP charge pump circuit, 3 ...
VPP level sensor, 5 ... internal step-down circuit, 6 ... VBB
Oscillation circuit, 7 ... VBB charge pump circuit, 8 ... V
BB level sensor, Q1-Q29 ... MOSFET, G
1 to G8: unit circuit, C1 to C8: capacitor, INV
1 to INV2: an inverter circuit.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification symbol FI H01L 21/8242 (72) Inventor Shinichiro Kimura 1-280 Higashi Koigakubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. (72) Inventor Hitoshi Tanaka 5-20-1, Josuihoncho, Kodaira-shi, Tokyo Inside Hitachi SLS Engineering Co., Ltd. (72) Inventor Hiromasa Noda 5-2-1, Josuihoncho, Kodaira-shi, Tokyo Stock Company (72) Inventor Masakazu Aoki 5-2-1, Kamizuhoncho, Kodaira-shi, Tokyo Inventor Hiroshi Kawamoto 5-72 Kamimizuhonmachi, Kodaira-shi, Tokyo No. 20 No. 1 Semiconductor Division, Hitachi, Ltd.

Claims (13)

[Claims] 1. An electronic circuit having a desired circuit function, a pad used to input and output an operating voltage and a signal to and from the electronic circuit, and a wiring path of the electronic circuit And a wiring program element that is selectively cut off in accordance with an electrical test result of the electronic circuit, wherein the wiring program element is configured by an uppermost wiring layer, and A program wiring portion having a cut surface etched and removed using a selective opening of the formed first insulating film; a surface of the first insulating film excluding an upper surface of the pad; A second surface covering the cut surface, and an opening surface of the opening portion formed by using a resist film opening corresponding to the photosensitive portion by irradiating an electron beam or a light spot corresponding to the test result used for the cutting; The semiconductor integrated circuit device, characterized in that it is made consists of a Enmaku. 2. The semiconductor integrated circuit device according to claim 1, wherein said uppermost wiring layer is a metal wiring layer, and said second insulating film is a final passivation film. 3. The semiconductor integrated circuit device according to claim 1, wherein said selective cutting of said program wiring portion is performed by a dry etching technique. 4. One end of the wiring program element is connected to a bit line, and the other end of the program element is connected to a ground potential of a circuit through a drain-source path of a MOSFET. The gate of the MOSFET is connected to a word line. The plurality of word lines and the plurality of bit lines are arranged so as to be orthogonal to each other.
2. The semiconductor integrated circuit device according to claim 1, wherein a memory cell comprising an OSFET is provided to form a ROM array. 5. A plurality of dynamic word lines each having a length divided in a direction in which the main word line extends and a plurality of dynamic word lines arranged in a bit line direction intersecting the main word line. A sub-word line to which an address selection terminal of a type memory cell is connected; a sub-word selection line to which a selection signal for selecting one of a plurality of sub-word lines assigned to the one main word line is transmitted; A plurality of sub-word line driving circuits for receiving the word line selection signal and the selection signal transmitted through the sub-word selection line and forming the sub-word line selection signal; A plurality of normal complementary bits arranged and having an input / output terminal of the dynamic memory cell connected to one of the input / output terminals; A pair of a plurality of sub-word lines, a redundant complementary bit line pair arranged so as to be orthogonal to the sub-word lines, and an input / output terminal of the dynamic memory cell connected to one of the sub-word lines, and a plurality of the normal complementary bit line pairs. A plurality of normal sense amplifiers having output terminals connected thereto; a redundant sense amplifier having input / output terminals connected to the redundant complementary bit line pairs; and a normal column selection circuit corresponding to the plurality of normal sense amplifiers. A normal input / output line and a normal main amplifier provided in common with the above, a redundant input / output line and a redundant main amplifier provided corresponding to the redundant sense amplifier, and electrically connected to the main word line, and And a ROM word line for storing a defective address, which is provided in the extension direction of the main word line. A plurality of memory cells each storing an address of a bit line in which a defective cell exists among sub word lines corresponding to the main word line; and a plurality of memory cells arranged in a direction orthogonal to the ROM word line, A connected ROM bit line, a sense amplifier for amplifying a read signal of the ROM bit line, a comparison circuit for detecting a comparison match between an output signal of the sense amplifier and a bit line selection address signal, and a match of the comparison circuit A selector for outputting a signal of the redundant main amplifier in place of the regular main amplifier in accordance with a detection signal; A semiconductor integrated circuit device comprising a dynamic RAM comprising: 6. The ROM bit line has one end connected to the wiring program element and the other end connected to a circuit ground potential through a drain-source path of a MOSFET. 5. The semiconductor integrated circuit device according to claim 4, wherein a line is connected to a gate of said MOSFET. 7. A plurality of ROM bit lines and ROM word lines are provided corresponding to the sub-word selection lines, and a plurality of ROM outputs are selected via a selector controlled by the sub-word selection lines. 7. The semiconductor integrated circuit device according to claim 6, wherein the address is supplied to the comparison circuit as a stored defective address. 8. The semiconductor according to claim 6, wherein a main word driver is arranged at one end of the main word line, and a ROM storing the defective address is arranged at the other end. Integrated circuit device. 9. The semiconductor integrated circuit device according to claim 1, wherein said wiring program element is used for cutting off a DC current path due to insulation failure between wirings. 10. The method according to claim 10, wherein the second insulating film is a silicon oxide film,
2. The semiconductor integrated circuit device according to claim 1, comprising a silicon nitride film laminated on the surface and a PIQ film laminated on the surface. (1) A circuit path having a desired circuit function is provided, and a wiring path to be selectively cut is led to a program wiring portion composed of an uppermost wiring layer. A step of forming on a semiconductor wafer an electronic circuit which is to be covered with a first insulating film except for a leading pad portion, (2) input and output of an operating voltage and a signal through the pad portion, and (3) forming a resist film on the surface of the electronic circuit, and forming an electron on the program wiring portion in accordance with the test result; Selectively removing the resist film by irradiating a line or a light spot; (4) forming an opening in the first insulating film using the resist film as a mask; and (5) using the first insulating film as a mask. That (6) a step of etching and removing the program wiring portion corresponding to the opening portion and cutting the same, and (6) covering the first insulating film and its opening surface and the cut surface of the program wiring portion except for the surface of the pad portion, and water-resistant Forming a second insulating film having a property. A method for manufacturing a wiring program element used in a semiconductor integrated circuit device. 12. The method according to claim 11, wherein the etching of the program wiring portion in the step (6) is performed by a dry etching technique using plasma.
Manufacturing method of a wiring program element used in a semiconductor integrated circuit device of the present invention. 13. The method according to claim 13, wherein the second insulating film is formed by depositing a plasma CVD method on a silicon oxide film deposited by a plasma CVD method.
13. The method for manufacturing a wiring program element used in a semiconductor integrated circuit device according to claim 12, wherein a silicon nitride film is laminated by a method, and a PIQ laminated film is formed thereon.