JPH11168652A - Electronic zoom circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain high-definition zoomed video by performing zoom processing, based on both information of even line information and odd line information which are outputted from a solid-state image-pickup device of a all pixel reading system. SOLUTION: Continuous line data for three lines of even line video information which is processed by (a) channel processing systems and for three lines of odd line video information which is processed by (b) channel processing systems are inputted to a vertical interpolation data selector 20. The selector 20 outputs luminance signal data for four lines that are inputted to terminals (c) to (f), e.g. to a vertical spline interpolation circuit 21 via terminals k to n and outputs luminance signal data for four lines that are inputted to terminal (b) to (e) to a vertical spline interpolation circuit 22 via terminals g to j. In such a case, only 8-bit luminance signals are outputted to the circuits 21 and 22. Zoom processing in vertical and horizontal directions are performed based on a luminance information signal and a color difference information signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an electronic zoom circuit for electronically enlarging a digital video signal input from a camera unit or a digital video signal reproduced from a video unit in, for example, a video camera apparatus. .

[0002]

2. Description of the Related Art Generally, a video camera apparatus achieves high-magnification zoom processing by using both an optical zoom and an electronic zoom. In these video camera devices,
An analog field video signal output for each field from the individual imaging device is amplified with an appropriate gain and converted to a digital video signal.

[0003] The converted digital video signal is processed into a luminance signal and a color difference signal suitable for recording on a digital video tape, and electronic zoom control is performed by an electronic zoom circuit based on a user's instruction. . The video signal that has been subjected to the electronic zoom control is recorded on a digital video tape after performing a predetermined video process process.

[0004] In this way, the video signal captured from the solid-state image sensor is enlarged by the electronic zoom circuit,
Although recorded on a digital video tape, the electronic zoom control can also be performed on a video signal reproduced from the digital video tape.

FIG. 7 is a block diagram for explaining an electronic zoom circuit for processing a luminance signal by a spline interpolation method and a chrominance signal by a linear interpolation method. A 12-bit video signal captured from an element or a 12-bit video signal reproduced from a digital video tape is input. Where 12
Among the bit input signals, the upper 8 bits indicate a luminance signal and the lower 4 bits indicate a color difference signal.

In FIG. 7, L1, L2, L3, and L4 are line memories which store video signals for one line and sequentially output the signals with a delay of one horizontal scanning period.
The video signals for one line are input from the line memories L1 to L4, and the upper eight bits of the luminance signal and the lower four
A luminance / color difference signal separation circuit that separates and outputs a bit color difference signal.

Reference numeral 11 denotes a vertical spline interpolation circuit for performing vertical spline interpolation processing based on four lines of luminance signals output from the luminance / color difference signal separation circuit 10, and 12 denotes the luminance / color difference signal separation circuit 10. Is a vertical linear interpolation circuit that performs vertical linear interpolation processing based on the color difference signals for two lines output from.

Reference numeral 13 denotes a horizontal spline interpolation circuit for horizontally expanding a luminance signal which has been vertically expanded by the vertical spline interpolation circuit 11, and reference numeral 14 denotes a vertical expansion process for the vertical linear interpolation circuit 12. This is a horizontal linear interpolation circuit for expanding the color difference signal in the horizontal direction.

With the above configuration, the input terminal In
The output of the 12-bit video signal is selected or adjusted in the line memories L1 to L4, and is input to the luminance / color difference signal separation circuit 10 as a continuous 4-line video signal. .

Then, the luminance signal 8 bits and the color difference signal 4
The bits are processed by vertical and horizontal interpolators, respectively.
Here, the color difference signal is output as 4-bit data, but after being replaced with 8-bit data by a color difference 8-bit conversion circuit (not shown), it is recorded on a digital video tape via a video processing system.

When a video signal recorded on the digital video tape is reproduced and zoom processing is performed on the reproduced video signal, the reproduced video signal is an 8-bit luminance signal and a 4-bit color difference signal. Therefore, the electronic zoom circuit can perform zoom processing in the same manner.

[0012]

However, in recent years, one frame of pixel information taken in every one field period is divided into a channel as even line information and b channel as odd line information and output every one field period. The solid-state image sensor of the all-pixel readout method capable of performing the operation has been developed and is being adopted also in a video camera device.
In the electronic zoom circuit, zoom processing cannot be performed based on both information of the even-numbered line information and the odd-numbered line information output from the solid-state image sensor of the all-pixel readout method.

Therefore, the electronic zoom processing is performed based on either the even-line information or the odd-line information, and the conventional solid-state imaging device outputs even-line information or odd-line information for each field. In this case, only a zoom image of the same quality as in the case where the electronic zoom processing is performed by using is obtained.

[0014]

In order to solve the above-mentioned problems, an electronic zoom circuit according to the present invention provides first and second image information signals forming image information for one frame every one field period. The first and second image information signals are output from the solid-state image sensor that outputs the first and second image information signals, and the first and second image information signals in the form of digital signals are generated from the first and second image information signals. First and second input means to which the first and second video information signals are input, and a first line information signal comprising a plurality of horizontal scanning line information signals included in the first video information signal; A second line information signal included in the second video information signal and configured by a plurality of horizontal scanning line information signals vertically adjacent to the horizontal scanning line information signal of the first line information signal; Is input, and the first and second Selecting and outputting a plurality of horizontal scanning line information signals adjacent in the vertical direction among the line information signals, and separating and outputting a luminance information signal and a color difference information signal from the selected plurality of horizontal scanning line information signals; and Pixel interpolating means for performing vertical and horizontal zoom processing based on the luminance information signal and the color difference information signal output from the selection / separation output means. The first and second input to the input means
Is a 12-bit digital information signal composed of 8 bits of luminance information and 4 bits of chrominance information.
And outputting 8-bit color difference information in which 4 bits of color difference information of a 2-bit digital information signal are combined with each other, and the selection / separation output means outputs the luminance from the first and second video signals. Separating and outputting an information signal into a first luminance information signal and a second luminance information signal; separating and outputting a chrominance signal from the first and second video signals; Means for performing zoom processing on the first luminance information signal by the first luminance information signal interpolation means, and performing zoom processing on the second luminance information signal by the second luminance information signal interpolation means; The chrominance information signal is zoomed by the chrominance information signal interpolating means, and the chrominance information signal interpolating means is a chrominance information signal for a pixel to be zoomed by the first luminance information signal interpolating means. Zoom It is characterized in that for processing and zoom processing of the color difference information signals for the pixel which is zoom processing by physical and the second luminance information signal interpolation means in time series alternately.

Further, the electronic zoom circuit according to the present invention can selectively input a video information signal in the form of a digital signal reproduced from a recording medium to the first input means. It is characterized in that zoom processing can be performed on a video information signal in the form of a digital signal to be reproduced.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An electronic zoom circuit according to the present invention comprises:
In a video camera device using an individual image pickup device of an all-pixel independent readout method, a high-quality zoom image is obtained, and this is achieved with a small circuit scale.

FIG. 1 is a block diagram showing a video camera device using an electronic zoom circuit according to the present invention. In FIG. 1, reference numeral 100 denotes a unit which divides pixel information of one frame taken in every one field period of a video signal into an a-line as even line information and a b-channel as odd line information, and outputs them every one field period. Solid-state image sensor with all pixel independent readout method (“all pixel readout CCD”)
The signals to be output are 101 to 10
A-channel processing system comprising 104 and 104 to 1
06 are independently processed in a b-channel processing system.

Here, on the all-pixel reading CCD 100, a plurality of solid-state imaging devices are arranged on one horizontal line, and when these are repeated in a vertical direction by a plurality of lines, a matrix is formed. One even-numbered line in the direction is processed by the a-channel processing system, and one odd-numbered line forming a pair with the one even-numbered line is processed by the b-channel system.

101 in the a-channel processing system
Is an automatic gain control circuit (also referred to as “AGC”) for amplifying an analog video signal from the all-pixel read CCD 100 with an appropriate gain.
A that converts the video signal from the camera into a digital video signal
A / D converter 103 and the A / D converter 102
A signal processing circuit for processing a video signal in a digital form from a digital video tape into a luminance signal and a color difference signal suitable for recording on a digital video tape. The signal processing circuit 103 outputs a luminance signal of higher 8 bits and a luminance signal of lower 4 bits A 12-bit digital video signal composed of color difference signals is output. Also, 104 to 1 of the b-channel processing system
Also in 06, the same processing as 101 to 103 in the a-channel system is performed, and a 12-bit digital video signal is output.

Here, the signal processing circuit 103 is connected to the A / D converter 10 input to the signal processing circuit 106.
5 to output the 12-bit digital video signal with reference to the output signal from the signal processing circuit 106.
Outputs the 12-bit digital video signal with reference to the output signal from the A / D converter 102 input to the signal processing circuit 103.

The signal processing circuits 103 and 106
The luminance signal Y, the chrominance signals BY and RY included in the digital video signal output from the LCD have a sampling frequency ratio of 4: 1: 1, and each has an information amount of 8 bits. Regarding the digital information signal, the signal processing circuits 103 and 106 combine the 8 bits of the luminance signal and the upper or lower 4 bits of the color difference signal to output a 12-bit digital video signal.

Therefore, the 8-bit color difference signal is formed by, for example, the upper 4 bits of the color difference signal combined with 8 bits of the luminance signal and the lower 4 bits of the color difference signal combined with the next 8 bits of the luminance signal. You. The arrangement of the color difference signals will be described later with reference to FIG.

Here, the signal processing circuit 103
And 106 are provided separately in the a-channel processing system and the b-channel processing system.
03 and 106 are provided as one signal processing circuit, and the 1
It may be configured to output a 2-bit digital video signal.

Reference numeral 107 denotes the a channel processing system and b
An electronic zoom circuit for enlarging a digital video signal output from a channel processing system based on a user's instruction. The input digital video signal is supplied to a frame memory 108 via the electronic zoom circuit 107.
The electronic zoom circuit 107 performs zoom processing by sequentially reading out necessary line data from the frame memory 108.

The video signal processed by the electronic zoom circuit 107 is converted into a field signal by a frame / field conversion circuit 109, and then recorded on a digital video tape via a video processing system (not shown). .

FIG. 2 is a block diagram for explaining the electronic zoom circuit 107. As shown in FIG. 2, the electronic zoom circuit 107 includes input terminals Ina and Inb, a line memory block, a vertical data selector, and an interpolation block. The line memory blocks are line memories La1, La2, La3, Lb1, and Lb2. , Lb3 and switches SW1 to SW3.

Here, the input terminal Ina is connected to the a
A 12-bit video signal processed by the channel processing system is input from the frame memory 108, and a 12-bit video signal processed by the b-channel processing system is input to the input terminal Inb from the frame memory 108. Input, the line memories La1, La2,
La3 stores data for one line of a 12-bit video signal processed by the a-channel processing system, respectively.
The line memories Lb1, Lb2, and Lb3 store one of the 12-bit video signals processed by the b-channel processing system.
Each line of data can be stored.

That is, the line memories La1, La2,
La3, Lb1, Lb2, and Lb3 store video signals for one line and output signals delayed by one horizontal scanning period. The video signals for three lines are output by the line memories La1 to La3. The video signals for three lines are taken out by the line memories Lb1 to Lb3.

The line memories La1 and Lb1
Outputs only a part of the stored data for one line so that the video signal indicated by the hatched portion in FIG. 3A is expanded in the horizontal direction by a horizontal interpolation circuit described later. As shown in FIG. 3B, La2, La3, Lb2, and Lb3 are input signals in one line memory in each line memory so that a video signal indicated by oblique lines is enlarged in a vertical direction by a vertical interpolation circuit described later. The output is delayed by the scanning period.

The switch SW1 selectively outputs the video signals from the line memories Lb1 and La1 to the line memory Lb2, and the switch SW2 transmits the video signals from the line memories La1 and Lb2 to the line memory La2. And the switch SW
Reference numeral 3 selectively outputs video signals from the line memories Lb2 and La2 to the line memory Lb3.

Here, when the inputs of the switches SW1 to SW3 are switched to the terminal A, three line signals from the video signals input from the input terminals Ina and Inb, ie, a total of six lines When the input of the switches SW1 to SW3 is switched to the terminal B side, four line signals are obtained from the video signal input from the input terminal Ina.

The terminals a to f of the vertical data selector 20 are connected to the line memories Lb1, La1, L
The video signals from b2, La2, Lb3, and La3 are input, and among the input video signals for the six lines, only the data of the lines necessary for the electronic zoom processing described later are selectively output. Therefore, if the line data required for the electronic zoom process does not change every horizontal scanning period,
The line memories Lb2, La2, Lb3, La3 do not perform the accumulation operation and continue to output the same line data.

The interpolation block includes vertical spline interpolation circuits 21 and 22 for performing vertical zoom processing of the luminance signal.
A vertical linear interpolation circuit 23 for performing a vertical zoom process of the color difference signal, horizontal spline interpolation circuits 24 and 25 for performing a horizontal zoom process of the luminance signal, and a horizontal spline interpolation circuit 26 for performing a horizontal zoom process of the color difference signal. Be composed.

Here, the vertical spline interpolation circuit 21
Are terminals n, m, and n of the vertical interpolation data selector 20.
8-bit luminance signals for four adjacent lines of the a-channel processing system and the b-channel processing system are input from l and k, and vertical spline interpolation processing is performed. Also, the vertical spline interpolation circuit 22 receives eight lines of four adjacent lines of the a-channel processing system and the b-channel processing system from the terminals j, i, h, and g of the vertical interpolation data selector 20.
A bit luminance signal is input and vertical spline interpolation processing is performed. Further, the vertical linear interpolation circuit 23 includes:
An 8-bit color difference signal is input for two lines by combining upper and lower bits from the terminals p and o of the vertical interpolation data selector 20 and subjected to vertical linear interpolation processing. The a-channel processing system and the b-channel processing system A line signal processed in step (1) is generated.

The horizontal spline interpolation circuit 24
The horizontal spline interpolation circuit 25 receives the luminance signal after the vertical interpolation processing, inputs the luminance signal after the vertical interpolation processing, and outputs the luminance signal after the horizontal interpolation processing. Then, it is subjected to horizontal interpolation processing and output. Further, the color difference signal which has been subjected to the vertical interpolation processing is input to the horizontal interpolation circuit 26, subjected to horizontal interpolation processing, and output.

Next, the operation of the electronic zoom circuit 107 will be described with reference to FIG. First, the all-pixel reading C
When an electronic zoom process is performed on a video signal captured by the CD 100, a 12-bit digital video signal processed by the a-channel processing system is input to the input terminal Ina, and the input terminal Inb , A 12-bit digital video signal processed by the b-channel processing system is input, and the inputs of the switches SW1 to SW3 are respectively switched to the terminal A side.

The 12-bit digital video signal processed by the a-channel processing system is supplied to the input terminal Ina.
, And one line of data is first stored in the line memory La1. The line memory La1
As described with reference to FIG. 3A, instead of outputting all the data for one line, only part of the data for one line is slowly output over one horizontal scanning period in accordance with the zoom magnification. Is output.

Here, since the input of the switch SW2 is switched to the terminal A side, the line memory La
1. The paths of the switch SW2, the line memory La2, and the line memory La3 are connected,
The signal from the line memory La1 is delayed by one horizontal scanning period in each line memory, and is input to the terminals b, d, and f of the vertical interpolation data selector 20, respectively.

On the other hand, a 12-bit digital video signal processed by the b-channel processing system is input via the input terminal Inb, and data for one line is first stored in the line memory Lb1.

Here, the switches SW1 and SW
3 has been switched to the terminal A, the line memory Lb1, the switch SW1, the line memory Lb2, the switch SW3, and the line memory Lb.
3 are connected, and the line memory L
The signal from b1 is delayed by one horizontal scanning period in each line memory and input to the terminals a, c, and e of the vertical interpolation data selector 20, respectively.

FIG. 4 shows the vertical interpolation data selector 20.
3 is a schematic diagram showing signals input to terminals a to f of FIG.
Thus, the vertical interpolation data selector 20 has a
Video information 3 of even line processed by channel processing system 3
Continuous line data of a total of six lines, that is, three lines of video information of odd lines processed by the b-channel processing system and lines, is input.

The vertical interpolation data selector 20
Selects the data of four adjacent lines of the a-channel system and the b-channel system from the data of these six consecutive lines as data necessary for the zoom processing. That is, the vertical interpolation data selector 20 is connected to the terminal c
To f, and outputs a luminance signal of four lines of data to the vertical spline interpolation circuit 21 via terminals k to n, and outputs a luminance signal of four lines of data input to terminals b to e. Output to the vertical spline interpolation circuit 22 via g to j. At this time, only 8-bit luminance signals are output to the spline interpolation circuits 21 and 22.

The vertical interpolation data selector 20
Is used to appropriately select two lines of data excluding the first line and the last line from among the four lines of data output to the spline interpolation circuits 21 and 22 from among these six consecutive lines of data. The vertical linear interpolation circuit 23
Output to At this time, the vertical linear interpolation circuit 23
Outputs only an 8-bit color difference signal.

Here, the vertical spline interpolation circuit 21
And 22 and the vertical linear interpolation performed by the vertical linear interpolation circuit 23,
This will be described with reference to FIG. FIGS. 5A to 5C are used to describe vertical spline interpolation, and FIG. 5D is used to describe vertical linear interpolation.

FIG. 5A shows an example in which image information consisting of five consecutive lines LN1 to LN5 is doubled in the vertical direction centering on the line LN3. In the vertical spline interpolation performed at this time, the luminance value of the pixels constituting each line is referred to, and the data of the pixel to be interpolated based on the luminance values of the four pixels arranged continuously in the vertical direction is obtained.
By sequentially performing this for each pixel arranged in the horizontal direction, data for one line is obtained.

The pixels on LN1 to LN5 are denoted by DT1 to D
T5, when the pixels after the enlargement processing are DT1 'to DT5', as shown in (b), DT1 ', DT3', DT
The 5 'luminance data can be interpolated with the DT2, DT3, and DT4 luminance data, respectively, but the DT2' and DT4 'luminance data require calculations, respectively.

At this time, the luminance data Y in DT2 '
2 ′ is DT1, DT2, DT3, as shown in FIG.
It is obtained by a curve obtained when the values of the luminance values Y1, Y2, Y3, and Y4 in DT4 are connected by a smooth curve.
The luminance values Y2 at DT2, DT3, DT4, DT5,
It is obtained by a curve obtained when the values of Y3, Y4, and Y5 are connected by a smooth curve.

That is, in the vertical spline interpolation at this time,
In order to obtain pixel data to be interpolated on the basis of luminance data of four pixels arranged in the vertical direction closest to the pixel to be interpolated, line information for four consecutive lines is required.

On the other hand, as shown in (d), when performing linear interpolation, the color difference values at DT2 'are obtained by connecting the color difference values at DT2 and DT3 with a straight line. That is, in order to obtain pixel data to be interpolated based on color difference data of two pixels that are consecutively arranged in the vertical direction closest to the pixel to be interpolated, line information for two consecutive lines is required. Although not described in detail here, interpolation data is similarly obtained for horizontal spline interpolation and linear interpolation.

Here, vertical spline interpolation is performed on the luminance signal, and vertical linear interpolation is performed on the chrominance signal. The interpolation data of the chrominance signal is the interpolation signal of the luminance signal. Although the data has poor zoom interpolation reproducibility as compared with the data, human eyes are not so sensitive to changes in fine colors, so that the obtained zoom image is good.

For the above-described spline interpolation and linear interpolation, the vertical interpolation data selector 20
A line necessary for interpolation is selected from among the input six lines of data, and an 8-bit luminance signal and a 4-bit luminance signal of a 12-bit video signal are separated and output.

Next, the operation of separating the luminance signal and the chrominance signal in the vertical interpolation data selector 20 will be described in detail with reference to FIG. As shown in FIG. 6A, here, the terminals f,
It is assumed that a 12-bit video signal is input to each of e, d, c, and b. As already explained, the terminals f, d,
A video signal processed in the a-channel system is input to b, and a video signal processed in the b-channel system is input to terminals e and c.

The video signal input at this time is obtained by combining the 8 bits of the luminance signal and the upper or lower 4 bits of the color difference signal in the signal control circuits 103 and 106.
It is a 12-bit video signal as shown in FIG.

Here, the luminance signal is represented by Y, the color difference signal BY is represented by B, and the color difference signal RY is represented by R.
The first 12-bit pixel signal input from the pixel signal is composed of 8 bits of the luminance signal for the pixel of pixel number 0 and the lower 4 bits of the color difference signal BY for the pixel of pixel number 0, and the next 12-bit pixel signal is And the upper 4 bits of the color difference signal BY for the pixel of pixel number 0 and the luminance signal of 8 bits for the pixel of pixel number 1.

The vertical interpolation data selector 20 supplies terminals f, e, d,
When the line information input to c is output and the line information input to terminals e, d, c, and b is output to the vertical spline interpolation circuit 22, each line is output as shown in FIG. Of the video signal is a terminal n,
m, l, and k are sequentially selected and output to the vertical spline interpolation circuit 21. As shown in FIG. 6C, an 8-bit luminance signal of the video signal of each line is output from the terminals j, i, h, and g to the vertical spline interpolation circuit 21. The signals are sequentially selected and output to the interpolation circuit 22.

FIG. 6D shows an output signal to the vertical linear interpolation circuit 23 at this time. The vertical interpolation data selector 20 combines the lower 4 bits and the upper 4 bits of the color difference signal of each line input from the terminals a, b, c, d, e, and f to form an 8-bit color difference signal. From p and o, color difference signals required for zoom processing in the a-channel system and color difference signals required for zoom processing in the b-channel system are alternately output in time series. Here, the terminal p
And the first 8 bits output from o indicate a color difference signal necessary for the zoom processing in the a-channel system.
The bit indicates a color difference signal required for zoom processing in the b-channel system.

Therefore, from the terminals p and o, the terminals f,
e, d, and c, two lines excluding the leading line and the last line of the four lines input from the terminals e and d, that is, the two lines of color difference signals BY (B
e0 and Bd0), and then two lines excluding the first and last lines of the four lines input from the terminals e, d, c, and b, that is, two lines input from the terminals d and c. Color difference signals BY (Bd0 and Bc0),
Next, two lines of color difference signals RY (Re0 and Rd0) input from terminals e and d, and two lines of color difference signals RY (Rd0 and Rd) input from terminals d and c.
Signals are output in the order of c0).

As described above, different lines may be selectively output to the vertical spline interpolation circuits 21 and 22, but the same four lines are selected depending on the zoom magnification specified by the user. It may be done.

Next, a case where zoom processing is performed on a video signal reproduced from a digital video tape will be described. The video signal reproduced from the digital video tape is a 12-bit video signal composed of an 8-bit luminance signal and a 4-bit color difference signal.
This is the same as the video signal processed in the a-channel system or the b-channel system.

When a zoom process is performed on a video signal reproduced from the digital video tape, a switch (not shown) provided before the input terminal Ina shown in FIG. The input is switched to a reproduction signal from a digital video tape, and the input terminal I
A 12-bit video signal composed of an 8-bit luminance signal and a 4-bit color difference signal is input to na. The video signal reproduced from the digital video tape is supplied to the terminal Inb
Is not entered.

At this time, the inputs of the switches SW1 to SW3 are respectively switched to the terminal B side, and the line memory La1, switch SW1, line memory Lb2,
Switch SW2, line memory La2, switch SW
3. The path of the line memory Lb3 is connected.

The video signal for one line input from the input terminal Ina is stored in the line memory La1, and the line memory La1 does not output all the data for one line as described above, Only a part of the data for one line is output slowly over one horizontal scanning period according to the magnification.

Then, each line memory is delayed by one horizontal scanning period, and
To four terminals e, d, c, and d. Accordingly, the vertical interpolation data selector 20 extracts only an 8-bit luminance signal from the input video signals of four lines and outputs the luminance signal to at least one of the vertical spline interpolation circuits 21 and 22. Only four-bit color difference signals are extracted from two lines of the input four lines excluding the first line and the last line, that is, two lines of video signals input from terminals d and c. By combining the lower bit and the upper bit of the signal, the signal is output to the vertical linear interpolation circuit 23 as an 8-bit color difference signal.

As described above, the vertical spline interpolation circuit 21 or 22, the vertical linear interpolation circuit 2
3. The same interpolation processing is performed by the horizontal spline interpolation circuit 24 or 25 and the horizontal linear interpolation circuit 26, and then output to the frame / field conversion circuit 109.

The video signals output from the all-pixel readout CCD 100 at the same timing are processed by the a-channel processing system and the b-channel processing system. When a still image recorded in the progressive mode in which an image is formed and recorded on the digital video tape is reproduced from the digital video tape, video signals for two fields to be reproduced are input to the input terminals Ina and Ina in FIG. Inb at the same timing, and the all-pixel read C
An electronic zoom process can be performed by performing the same process as the zoom process on the video signal from the CD 100.

[0066]

As described above, the electronic zoom circuit according to the present invention performs the zoom process based on both the even-line information and the odd-line information output from the solid-state image pickup device of the all-pixel reading system. Therefore, a high-quality zoom image can be obtained.

The vertical interpolation data selector 20
Is output as an 8-bit color difference signal by combining the upper 4 bits and the lower 4 bits of the input color difference signal, so that the color difference signal is zoomed by two 4-bit information signals because it is 8 bits. The zoom accuracy can be improved as compared with.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a video camera device using an electronic zoom circuit according to the present invention.

FIG. 2 is a block diagram showing an electronic zoom circuit according to the present invention.

FIG. 3 is a schematic diagram showing an example of a case where an input video signal is doubled;

FIG. 4 is a schematic diagram for explaining signals input to a vertical interpolation data selector.

FIG. 5 is a schematic diagram for explaining vertical spline interpolation and linear spline interpolation.

FIG. 6 is a diagram illustrating a video signal input to the vertical interpolation data selector or a video signal output by the vertical interpolation data selector.

FIG. 7 is a block diagram showing a conventional electronic zoom circuit.

[Description of Signs] 10: luminance / color difference signal separation circuit 11, 21, 22 ... vertical spline interpolation circuit 12, 23 ... vertical linear interpolation circuit 13, 24, 25 ... horizontal spline interpolation circuit 14, 26 ... horizontal linear interpolation circuit 20 ... Vertical interpolation data selector 100. All pixel read CCDs 101 and 104. Automatic gain control circuits (AGC) 102 and 105. A / D converters 103 and 106. Signal processing circuit 107. Electronic zoom circuit 108. / Field conversion circuit L1, L2, L3, L4, La1, La2, La3, L
b1, Lb2, Lb3 ... line memories SW1, SW2, SW3 ... switches In, Ina, Inb ... input terminals

Claims (5)

[Claims] A first image information signal which outputs first and second image information signals forming one frame of image information every one field period; a first image information signal and a second image information signal; First and second input means for generating first and second video information signals in the form of digital signals from the first and second image information signals, and receiving the first and second video information signals; A first line information signal including a plurality of horizontal scanning line information signals included in the first video information signal; and a horizontal line information signal included in the second video information signal. A scanning line information signal and a second line information signal composed of a plurality of vertically adjacent horizontal scanning line information signals are input, and the first and second line information signals are vertically adjacent to each other. Select multiple horizontal scanning line information signals A selective separation output unit that separates and outputs a luminance information signal and a color difference information signal from the selected plurality of horizontal scanning line information signals; and a vertical separation based on the luminance information signal and the color difference information signal output from the selective separation output unit. An electronic zoom circuit including pixel interpolation means for performing a horizontal and horizontal zoom process. 2. The first and second video information signals input to the first and second input means are 12-bit digital information signals comprising 8 bits of luminance information and 4 bits of color difference information. 2. The apparatus according to claim 1, wherein the selection / separation output unit outputs 8-bit luminance information and 8-bit color difference information obtained by combining 4 bits of color difference information of an adjacent 12-bit digital information signal. Electronic zoom circuit. 3. The selective separation output means separates the luminance information signal from the first and second video signals into a first luminance information signal and a second luminance information signal, and outputs the separated luminance information signal. Separating and outputting a color difference signal from the first and second video signals, and thereafter, the pixel interpolating means performs a zoom process on the first luminance information signal by the first luminance information signal interpolating means; 3. A zoom processing of the second luminance information signal by the second luminance information signal interpolating means, and a zoom processing of the color difference information signal by the color difference information signal interpolating means. Electronic zoom circuit. 4. The color difference information signal interpolating means includes a zoom processing of a color difference information signal for a pixel to be zoomed by the first luminance information signal interpolating means, and a zoom processing by the second luminance information signal interpolating means. 4. The electronic zoom circuit according to claim 3, wherein the zoom processing of the color difference information signal for the pixel to be performed is alternately processed in a time series. 5. A digital signal format video information signal reproduced from a recording medium can be selectively input to the first input means, and a digital signal format reproduced from the recording medium can be selectively inputted. The electronic zoom circuit according to claim 1, wherein zoom processing can be performed on a video information signal.