JPH11168381A - Control signal compensation method, compensation control system and analog/digital processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To compensate the effect of correction waiting time without reducing a loop gain by storing correction executed by a controller and permitting the controller to execute evaluation with a monitor circuit connected to the controller. SOLUTION: A correction value added to a control loop is stored so that the value can be used without waiting for the transmission of the correction through the control loop. A compensation control system 11 contains a controller 5 and the monitor circuit 4, which are connected in series. The monitor circuit 4 has a local feed back loop 12 parallel to the regular correction flow of the compensation control system so that additional waiting time is not introduced. The compensation circuit 14 receives a detected signal In and transmits a compensation signal Φn at time t=nt (T is clock period). The compensation circuit 14 connects the compensation signal Φn to plural adder nodes Σ2 through an adder node, plural delay blocks and plural reduced connection blocks, which are connected in series.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a compensation method for a control system, that is to say a compensation method having a large latency.

More particularly, the present invention relates to a control signal compensation method for an analog / digital processing system, particularly with a control loop including a controller and a monitoring circuit.

The present invention also includes a controller and a monitoring circuit connected in series between an input terminal and an output terminal of the compensation control system, wherein the monitoring circuit includes an input terminal connected to an input terminal of the compensation control system. A compensation control system of the type having a terminal and an output terminal connected to the input terminal of the controller, wherein the controller has an output terminal connected to the output terminal of the compensation control system.

Finally, the invention relates to an analog / digital processing system incorporating the above compensation control system.

The invention relates in particular to a control signal compensation method and a compensation control system for analog / digital processing systems. However, it is not limited to these. The following description refers to this application for the sake of explanation.

[0006]

BACKGROUND OF THE INVENTION As is well recognized, a problem introduced by mixed sampling data analog / digital systems is that of controlling the characteristics of the processed signal for processing optimization. Errors in the width of the predicted signal, as well as biasing and sampling errors, are usually estimated by specific monitoring circuits that modify parameters of the overall processing system by acting on sections specifically allocated to analog preprocessing steps. Is done.

A conventional analog / digital processing system is shown schematically in FIG. The analog / digital processing system has an input terminal IN1 for receiving an input signal S _in to be processed and an output terminal OUT1 for transmitting a processed output signal S _out . The analog / digital processing system 1 includes an analog filter circuit 2 and a digital processing circuit 3 connected in series between an input terminal IN1 and an output terminal OUT1.

In particular, the analog filter circuit 2 includes an input terminal I2 connected to the input terminal IN1 of the analog / digital processing system and an input terminal I2 of the digital processing circuit 3.
3 connected to an output terminal O2. The digital processing circuit 3 has an output terminal O3 connected to the output terminal OUT1 of the analog / digital processing system 1. The output terminal O2 of the analog filter circuit 2 is connected to its control terminal TC2 via a series of monitoring circuits 4 and a controller 5.

More specifically, the output terminal O2 of the analog filter circuit 2 is connected to the input terminal I4 of the monitoring circuit 4. The monitoring circuit 4 is connected to the input terminal I5 of the controller 5
Has an output terminal O4 connected to the terminal. Controller 5
Has an output terminal O5 connected to the control terminal TC2 of the analog filter circuit 2.

Generally, the controller 5 includes a PID circuit,
That is, a corresponding signal S proportional to the combination of the first derivative and the integral of the error signal S4 generated by the monitoring circuit 4.
5 and a circuit that can generate a term proportional to the error signal S4.

Since the characteristics of the signal S _in to be processed are usually known, this simple class of PID controllers is sufficiently versatile. In fact, different monitoring circuits can be used for the phase, offset and gain signals from the analog / digital processing system 1. The monitoring circuits do not interact with one another, so that a separate controller is obtained, in particular adapted to act independently on different parameters of the analog part of the analog / digital processing system 1.

[0012] monitoring circuit 4 receives the filtered signal S2, a non-linear function of the input signal, and outputs an error signal S4 proportional to the estimated characteristics of the processed signal S _out. Integrating the monitoring circuit 4 and the controller 5 in the digital domain is a convenient choice. However, it should be noted that for systems operating at higher frequencies, the processing of the signal S _in to be processed must be split over several clock cycles.

Thus, a waiting time is introduced into the control loop formed by the monitoring circuit 4 and the controller 5. This latency places a limit on the loop gain of the analog / digital processing system 1, thereby impairing its overall performance. Latency here means a predetermined delay during the transmission of data through the control loop, ie the delay between the application of a stimulus or disturbance to the control loop input and its first correction output from the control loop. I do. This delay is usually expressed in clock cycles.

It is conceivable to employ a more sophisticated design for the controller 5 to compensate for the degraded performance of the analog / digital processing system 1. However, as a practical matter, this will result in a further increase in latency in the control loop.

In particular, because of the need to keep the latency perceived in applications where clock cycles are very short,
A compromise would be made by using a less versatile controller that would give the system long enough time to focus on the optimal parameters. This implies that during the processing steps, the data is led by a preamble long enough to stabilize the supervisory controller loop. A first prior art solution to the problem of reducing control loop latency is to use a phase locked loop or PL.
That is, the controller 5 including L6 is used.

FIG. 2 schematically illustrates a linear model of such a conventional PLL controller 5 including a phase locked loop generally indicated by reference numeral 6. Purely by way of explanation, reference is made in particular to the example of the sampling step controller 5. The considerations made below are of more general value.

When the signal is processed specifically, the PLL
The controller 5 should be applied to the phase detector as operating in linear mode for simplicity, ie close to lock.

The PLL controller 5, to the input to receive the second signal VCO _n of the first signal i _n and subtraction terminal of the adder terminal, and the adjusted phase signal Φn on the output terminal O1 It has an adder node # ₁ to transmit. P
The LL controller 5 is modeled as a simple integrator and a loop filter 7 formed from a simple controller PI connected in series between the output terminal O1 and the subtraction terminal of the adder # ₁ . And a voltage / frequency converter 8. The PLL controller 5 has a waiting time block 9
And a loop gain vco ga schematically represented by the gain block 10.
in.

The loop filter 7 has a first A characteristic parameter and a second B characteristic parameter which are an integral gain and a proportional gain, respectively. Those changes are PL
An L controller 5 governs the stability of the analog / digital processing system 1 applied thereto. In particular, as the latency M increases, the range in which the analog / digital processing system 1 remains stable for changing characteristic parameters A and B becomes increasingly narrower, and the choice of these integral A and proportional B gains is The results are greatly limited.

When using this type of PLL controller 5, for example, it is not possible to optimize the control time concentrated during the preamble. It should be noted that instead of the PI filter 7, a substantial improvement in system performance can be achieved by using any general purpose filter of greater complexity characterized by a frequency response with two poles and two zeros. . The reason for such a deep influence of the latency M on the performance of the controller 5 formed by the phase locked loop 6 can be understood by examining the position of the root of the controller 5, as shown in FIG.

The controller 5 has M poles at the origin for a waiting time M, two poles at +1 and 1-A /
B has 0. These are coupled to a loop filter voltage / frequency converter combination.

Analysis of the root location in FIG. 3 shows that the pole that tends to exit the unit circle first is the pole of the location branch with the origin at +1. Also, since such a pole is defined in a sector (defined by polar coordinates (θ, r)), the loop gain vco ga of the phase locked loop 6
The slowest mode of the PLL controller 5 is generated at an arbitrary value of in.

[0023]

(Equation 3)

Since the ratio A / B is close to 1 for the PLL controller 5 to stabilize, the usable range is obviously limited. However, in any case,
Note that if a value greater than 5 for the latency M must be tolerated for design reasons, increasing the latency unit does not change the characteristics of the PLL controller 5 to any significant extent.

FIG. 4 shows the form of the amplitude response of the PLL controller 5. In particular, the graph of FIG. 4 is plotted against a log scale. Value 1 is frequency f = 1 / 2T
It is located at. T is the clock cycle of the analog / digital processing system 1, and the waiting time M = 8
Associated with the PLL controller 5. According to the above, this pattern is substantially invariant over the right half when the characteristic parameters A and B of the loop filter 7 change.

FIG. 5 shows the PLL for parameter A along with the normalized value of parameter B along the abscissa axis.
4 shows a band limit pattern of the controller 5 at −3 dB. In particular, the band limit is marked along the ordinate as a percentage of 1 / 2T.

From the graphs of FIGS. 4 and 5, the only part of the frequency response of the PLL controller 5 that is affected by changes in the characteristic parameters A and B of the loop filter 7 of the phase locked loop 6 is the remainder of the response. Depends on the position of the pole introduced by the waiting time M, so that it can be concluded that this is a low frequency part. The positions of these poles are substantially defined only by the loop gain vcogain of the phase locked loop 6.

If a loop filter having a more complex architecture than that shown in FIG. 2 is used, controller versatility cannot be increased to a satisfactory degree.
Also note that the analog / digital processing system 1 cannot be enhanced as a whole. The analog / digital processing system 1 derives its inherent limitations from the above equation (1).

In particular, a rough equation can be easily derived for the upper band limit of the analog / digital processing system 1 which is substantially unrelated to the controller architecture. The branches generated from +1 are angularly coupled as shown in Equation 2, so that Equation 3 holds.

[0030]

(Equation 4)

[0031]

(Equation 5)

Here, ＴT is the extreme band of the system 1 in the clock period T, and it is not only obvious that the controller 5 can only “shape” a part of the useful band, but also that Confirmed by (3). It is also understood that the stability range of the controller 5 decreases as the latency M increases in the phase locked loop 6 since the effect of the correction is only noticeable after a duration equal to the latency M. I want to. During this time, the system is under the influence of this control. For the same characteristic of the controller 5, as the waiting time M increases, the correction effect lasts longer, so there is a clear need to reduce the loop gain vcogain.

[0033]

The technical problem underlying the present invention is to compensate for the effects of correction latency without reducing loop gain, thereby overcoming the limitations inherent in conventional controllers. It is to provide a controller having such a structure and functional characteristics.

[0034]

The idea of the solution behind the invention is that the corrections made by the controller are stored and the controller evaluates it by means of a monitoring circuit connected to it.

In particular, effective compensation can be implemented by giving the monitoring circuit the ability to store previous corrections. In this way, the monitoring circuit is not forced to wait for the effect of the correction to propagate through the control loop of the analog / digital processing system incorporating the monitoring circuit and controller.

Thus, after the controller latency is known, the effect can be compensated for by the monitoring circuit providing a wider range of changes to the controller loop gain.

Based on the idea of this solution, this technical problem is solved by the compensation method which has been set forth above and defined in the characterizing part of claim 1. This problem is also solved by a compensation control system as set forth above and defined in the characterizing part of claim 4. This problem is further solved by an analog / digital processing system as set forth above and defined in the characterizing part of claim 10.

The features and advantages of the compensation method, the compensation control system and the analog / digital processing system according to the invention will be described in more detail in the following description of an embodiment of the invention, given by way of non-limiting example, with reference to the accompanying drawings, in which: It will be clear from the explanation.

[0039]

DETAILED DESCRIPTION OF THE INVENTION In the method of compensating a correction signal according to the present invention, a correction value applied to a control loop is stored such that the correction value can be used without waiting for the correction to propagate through the control loop. You.

In particular, in connection with an analog / digital processing system having a control loop including a controller and a monitoring circuit, the compensation method of the present invention transfers the corrections made by the controller to the monitoring circuit to which the controller is connected. Storing and processing such corrections without waiting for the effects of the corrections to propagate through the control loop of the analog / digital processing system incorporating the monitoring circuit and the controller; and negative feedback at the monitoring circuit. Using a loop to generate a compensation signal for the latency effect of the controller. In the present invention, the compensation signal Φn (T is a clock cycle) at time t = nT is

[0041]

(Equation 6)

Advantageously, The above formula
In (4), I _n is the detected signal at the input of the compensation circuit, a _k is the compensation parameters. The compensation method of the present invention performs the z-transformation of the above equation (4).

[0043]

(Equation 7)

We introduce N zeros at the origin and N poles, which are the roots of the polynomial of the coefficient a _k that can be verified by obtaining Therefore, the pole introduced by the waiting time is
They are referred to as compensation parameters a ₁ , a ₂ ,. . . , A _N by "shifting" to a new position selected by the user.

With reference to such a diagram, and in particular to FIG. 6, a compensation control system for implementing the compensation method of the present invention is indicated generally at 11. For clarity, functionally identical elements to corresponding elements of the analog / digital processing system 1 described in connection with the prior art are denoted by the same reference numerals.

The compensation control system 11 includes a controller 5 and a monitoring circuit 4 connected in series between the input terminal I11 and the output terminal O11 of the compensation control system 11. The monitoring circuit 4 has a local feedback loop 12 parallel to the normal correction flow of the compensation control system 11 so as not to introduce additional latency.

In particular, the monitoring circuit 4 includes an input terminal I1 connected to an input terminal I4 of the monitoring circuit inside the monitoring circuit 4.
3, comprises a linear detector 13 and an adder node sigma ₂ of summing terminal connected to an output terminal O13. Monitoring circuit 4
Further, the output terminal O4 of the monitoring circuit 4 and the adder node Σ
₂ includes a compensating circuit 14 that is feedback-connected between the _two subtracting terminals.

It should be noted that linear detector 13 can generally be implemented by those skilled in the art. FIG. 7 shows an embodiment of the compensation circuit 14. In particular, the compensation circuit 14 detects the detected signal I
n connected in series with each other between an input terminal I14 of the compensating circuit 14 for receiving n and an output terminal O14 of the compensating circuit 14 for transmitting the compensation signal Φn at time t = nT (T is a clock cycle). Adder node Σ ₃₁ ,
Σ ₃₂ ,. . . , Σ _3N .

The output terminal O14 of the compensation circuit 14 is
A plurality of delay blocks b ₁ connected in series with each other,
b ₂ ,. . . , B _N to its input terminal I14 and a plurality of decoupling blocks a ₁ , a ₂ ,. . . ,
a _N through a plurality of adder nodes _{３１ 31} ,
Σ ₃₂ ,. . . , Σ _3N . According to the architecture of FIG.

[0050]

(Equation 8)

The compensation signal Φn given by is obtained. The Z-transform is as in the following equation.

[0052]

(Equation 9)

That is, the compensation signal obtained by the equations (4) and (5) specified above for the compensation method of the present invention. Therefore, the compensation circuit 14 shown in FIG.
The poles which have N zeros in the poles and are introduced by the latency cause them to be decoupled blocks a ₁ , a _1
2 ,. . . , A _N to a new position selected through the control.

Therefore, according to the present invention, the monitoring circuit 4 that acts on the control parameters from the “outside” and includes the compensation circuit 14
It is advantageous that such a circuit can be used to optimize the control of the analog / digital processing system 1 connected to it.

8, 9 and 10 show the same loop gain vco gai with and without compensation.
7 shows a comparison between the response of the conventional controller shown in FIG. 2 and the response of the compensation control system of the present invention shown in FIG. In particular, FIGS. 8 and 9 plot the integral of the output signal, the output signal, and the phase error at the output of the linear detector 13 versus the base number of the input sample on the abscissa axis. 8 and 9 show that M =
8, the compensation control system 11 when A = 12 (maximum) and B = 6 (50%).

From the comparison in FIG. 10, the different lengths of the transient phase of the output signal from the linear detector 13 can be clearly understood. The applicant has the following formula 6

[0057]

(Equation 10)

In a simulation performed using the "phase step + frequency step" signal type, the compensation circuit 14 embodying the present invention selected the following values. N = 3 a ₀ = −0.056 a ₂ = 0.48 a ₃ = 1

These values can be compared to an analog / digital processing system (system 1A) with a phase locked loop or PLL controller as described with respect to the prior art, and with a compensation circuit 14 at the output of the loop filter 7 according to the invention. The following convergence time is obtained by adding the following convergence time to the analog / digital processing system (system 1B).

[0060]

[Table 1]

In Table 1, delta_dac is the loop
The difference between the instantaneous value of the filter output and its steady state value,
T is the clock period of the analog / digital processing system. Table 1 relates to a simple (and thus non-optimized) example of a compensation control system according to the invention applied to an analog / digital processing system. This shows that a controller with a compensation circuit according to the invention provides a significant reduction in preamble length while already in a non-optimal state.

In the digital version of the controller with the compensation circuit according to the invention, the contents of the N memories are added to the input signal using a single adder node. Although this compensation circuit does not add latency to the control loop of the analog / digital processing system, an adder node with N + 1 inputs requires an additional clock cycle to complete the process.

In a preferred digital embodiment of the compensation control system according to the present invention, a two-input adder is used for applications involving a carry-save type stage that introduces the delay of Equation 7 below. In Equation 7, τ _adder is the delay of the two-input adder and τ _carrys is the delay of the carry-preserving type adder stage.

Δ = τ _adder + (N + 1-2) · τ _carryries (7)

In this way, the compensation control system 11
The resolution of the error signal at the output of the linear detector 13 of the monitoring circuit 14 is kept low and a smaller size adder can be used. Furthermore, it is advisable to increase the waiting time M by one when the Nth order of the compensation circuit 14 of the compensation control system according to the invention increases. However, in view of the fact that the controller having the compensation circuit 14 can be used only when the waiting time is long, the performance of the analog / digital processing system without compensation is not significantly reduced. On the contrary, this is offset by the increased effectiveness of the control with compensation.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing a conventional analog / digital processing system.

FIG. 2 is a schematic diagram illustrating a controller used in the analog / digital processing system of FIG.

FIG. 3 is a diagram illustrating a position of a root of the controller in FIG. 2;

FIG. 4 shows the shape of the amplitude response on a log scale of the controller of FIG. 2;

5 shows the behavior of the controller of FIG. 2 in the -3 dB band limit with respect to the change of its parameters.

FIG. 6 is a schematic diagram showing a compensation control system according to the present invention.

FIG. 7 is a detailed diagram of the compensation control system shown in FIG. 6;

FIG. 8 is a diagram showing a response of the conventional controller of FIG. 2;

FIG. 9 is a diagram showing a response of the compensation control system shown in FIG. 6;

FIG. 10 is a diagram comparing the responses of the controllers shown in FIGS. 2 and 6;

[Explanation of symbols]

1 analog / digital processing system, 2 analog filter circuit, 3 digital processing circuit, 4 monitoring circuit, 5 controller, 11 compensation control system,
12 local feedback loop, 13 linear detector, 14 compensation circuit, a ₁ decoupling block, a
₂ decoupling block, a _N decoupling block, b ₁
Delay block, _{b 2} delay block, _{b N} delay blocks, sigma ₂ adder node, sigma ₃₁ adder node, sigma ₃₂ adder node, sigma _3N adder node, I11 input terminals, I13 input terminals, I1
4 input terminal, I2 input terminal, I3 input terminal,
I4 input terminal, I5 input terminal, IN1 input terminal, O1 output terminal, O11 output terminal, O13
Output terminal, O14 output terminal, O2 output terminal,
O3 output terminal, O4 output terminal, O5 output terminal.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Ivan Bietti 46040 Casal Romano, Via Fossa Reja 43

Claims (10)

[Claims] 1. A method for compensating a control signal for an analog / digital processing system having a control loop including a controller and a monitoring circuit, comprising: storing a correction made by the controller; and transmitting the correction into the control loop. Control signal compensation using a negative feedback loop at the supervisory circuit level to generate a compensation signal for the latency effect of the controller. Method. 2. The compensation signal (Φn) is obtained by using In as a signal detected at the input of the compensation circuit and a _k as a compensation parameter. The control signal compensation method according to claim 1, wherein: 3. The method according to claim 2, wherein the compensation signal (Φn) is a root of a polynomial of the coefficient a _k and thus introduces N zeros at the origin and N poles which can be controlled by the compensation parameter (a _k ). The control signal compensation method according to claim 2, wherein 4. An input terminal (I11) and an output terminal (O1).
1) a compensation control system comprising a controller (5) and a monitoring circuit (4) connected in series with each other, wherein the monitoring circuit (4) is connected to the input terminal (I1).
1) and the output terminal (O) connected to the input terminal (I5) of the controller (5).
4), wherein the controller (5) has an output terminal (O5) connected to the output terminal (O11), wherein the monitoring circuit (4) includes the compensation control system. (11)
Local feedback parallel to the normal control flow of
A compensation control system comprising a loop (12). 5. The local feedback loop (1)
2) includes a compensation circuit (14), and the compensation circuit (14) includes an input terminal (I14) connected to an output terminal (O4) of the monitoring circuit (4) and a subtraction terminal of an adder node (# 2). The compensation control system according to claim 4, further comprising an output terminal (O14) connected to the control terminal. 6. The monitoring circuit (4) further comprises a linear detector (13), wherein the linear detector (13) is connected to an input terminal (I13) of the monitoring circuit.
The compensation control system according to claim 5, further comprising an output terminal (O13) connected to an addition terminal of the adder node (# 2). 7. The compensation circuit (14) transmits a compensation signal (Φn) and an input terminal (I14) of the compensation circuit (14) arranged to receive the detected signal (In). Output terminals of the compensating circuit (O
14. The compensation control system according to claim 5, further comprising a plurality of adder nodes (Σ ₃₁ , Σ ₃₂ ,..., _{３ 3N} ) connected in series with each other. 8. A plurality of delay blocks (14) connected between an output terminal (O14) of the compensation circuit (14) and an input terminal (I14) of the compensation circuit (14). b ₁ , b ₂ ,..., b _N ), and the plurality of delay blocks (b ₁ , b ₂ ,..., b _N ) themselves form a plurality of decoupling blocks (a ₁ , a _2). , ...,
a _N ) via a plurality of adder nodes (Σ ₃₁ ,
Σ ₃₂ ,. . . , Σ _{3 N} ), and thereby In
Is a detection signal received at an input terminal (I14) of the compensation circuit (14), and ak is a characteristic parameter of the plurality of decoupling blocks (a ₁ , a ₂ ,..., A _N ). The compensation control system according to claim 7, wherein a compensation signal (Φn) given by the following formula is generated. 9. The compensation circuit (14) is implemented in digital form and comprises a plurality of memories and a single two-input adder, wherein the two-input adder _reduces τ _adder to the delay of the two-input adder, τ _{6. A} carry-preserving type stage which introduces a delay given by [Delta] = [tau] _adder + (N + 1-2) * [tau] _carrys (7) as carrys is the delay of the carry-preserving _adder stage. 3. The compensation control system according to 1. 10. An input terminal (IN1) and an output terminal (OU).
An analog / digital processing system (1) comprising at least one analog filter circuit (2) and a digital processing circuit (3) connected in series with each other between the analog filter circuit (T1) and the analog filter circuit (2). 2)
Is an input terminal (I) connected to the input terminal (IN1).
2) and an output terminal (O1) connected to an input terminal (I3) of the analog / digital processing circuit (3), wherein the analog / digital processing circuit (3) is connected to the output terminal (OUT1). An analog / digital processing system of the type having an integrated output terminal (O3), wherein said output terminal (O3) of said analog filter circuit (2) is
2) further has its control terminal (TC) via a compensation control system (11) according to any one of claims 4 to 9.
An analog / digital processing system, which is connected to 2).