JPH11167526A - Memory read and write method and device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent an outsider from analyzing the program stored in a memory and also transforming wrong the program by switching a bus to a pattern different from the normal one when a CPU writes the data into the memory and switching again the bus to the normal pattern when the CPU reads the data out of the memory. SOLUTION: The scramble value is set to a data scramble/descramble circuit 5 and an address scramble circuit 6 which are contained in a scramble circuit 7. Thus, a data bus DB and an address bus AB are partly scrambled and connected to a data terminal DT and an address terminal AD of an SRAM 3 or a flash memory 4 as a scramble data bus SQDB and a scramble address bus SQAB respectively. A CPU 1 writes the scramble value into a non-scramble area of the memory 4. Then the CPU 1 copies an application program of the SRAM 3 to the memory 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a memory read / write method for writing data to a memory and an apparatus therefor.

[0002]

2. Description of the Related Art Generally, when a memory such as a ROM or a RAM is connected to a CPU, an address bus from the CPU is connected to the memory in order from an upper address bit line AB15 to a lower address bit line AB0. The data bus is also connected in order from the upper data bit line DB7 to the lower data bit line DB0. Therefore, when a program is stored in the memory, the program is stored in order from a lower address to an upper address of the memory.

[0003]

As described above, since the programs of the memory are stored in order from the lower address to the upper address, for example, a ROM writer is connected to the memory in the same address order as the CPU. And using an in-circuit emulator, etc.
The program in the memory can be easily read. The program read from the memory in this way is analyzed by a third party, and there is a problem that the program may be illegally rewritten by the third party. Therefore, an object of the present invention is to prevent a program stored in a memory from being analyzed by a third party and prevent unauthorized modification of the program.

[0004]

SUMMARY OF THE INVENTION In order to solve such a problem, the present invention comprises a CPU and a memory connected to the CPU via a bus including an address bus and a data bus. In a memory read / write device that writes data via a bus,
A first step of switching the bus to a pattern different from the normal pattern when U writes data to the memory;
A second step of restoring the bus to a normal pattern when the CPU reads data from the memory. Further, between the CPU and the memory, when the CPU writes data to the memory, the data bus switches to a pattern different from the normal pattern.
And a second circuit for restoring the data bus to a normal pattern when the CPU reads data from the memory.
And a descrambling circuit. Also,
A second scramble circuit for switching an address bus to a pattern different from a normal pattern when the CPU writes data to the memory, and a second descramble circuit for restoring the address bus to the normal pattern when the CPU reads data from the memory At least one of which is provided. Further, between the CPU and the memory, the first scramble circuit and the first descramble circuit are provided, and at least one of the second scramble circuit and the second descramble circuit is provided. Further, a writing means for writing program data to the memory and a scramble circuit provided between the CPU and the memory for switching the bus are provided. When the CPU receives the program data, the CPU switches the bus to the scramble circuit based on a predetermined pattern. The program data is written into the memory via the scramble circuit by the writing means.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a memory read / write device according to the present invention. In this figure, this device comprises a CPU 1, a ROM 2, a scramble target memory such as an SRAM 3 and a flash memory 4 which are scrambled when data is written,
A scramble circuit 7 is connected between the CPU 1 and the memory to be scrambled and includes a data scramble / descramble circuit 5 for scrambling and descrambling the data bus DB and an address scramble circuit 6 for scrambling the address bus AB. .

Here, a ROM writer (not shown)
A program, SR, which is started immediately after resetting the apparatus and is used to initialize the apparatus (initialization process)
A program for scrambling a bus of a memory to be scrambled such as AM3 and a program for downloading an application program to SRAM3 or the like are stored, and the R0M2 is stored in the CPU1 or SRAM3.
Are mounted on a board (not shown) on which the board is mounted, and the board is connected to the host device 8 which is a download device such as a personal computer, and the power is turned on to the board. In this case, CP
Immediately after power is supplied and reset and the reset is released, U1 first executes a program in the ROM 2 to perform initialization processing of the device, and then checks whether or not the program has been written in the flash memory 4. In the initial state, since no program is stored in the flash memory 4, the state shifts to a program download waiting state. Thereafter, the CPU 1 sets a scramble value in a scramble key register described later and scrambles the bus to the SRAM 3 or the flash memory 4.

That is, a part of the data bus DB and the address bus A are set by setting scramble values for the data scramble / descramble circuit 5 and the address scramble circuit 6 in the scramble circuit 7, respectively.
A part of B is scrambled so as to be connected to a data terminal DT and an address terminal AD of the SRAM 3 or the flash memory 4 as a scramble data bus SQDB and a scramble address bus SQAB. Thereafter, the CPU 1 writes the scramble value in the non-scramble area of the flash memory 4. In addition,
If a scramble value has already been set in the flash memory 4, this set value is read out and set in the scramble key register. After such scrambling, C
When the PU 1 continuously executes the program in the ROM 2 and receives the application program downloaded from the host device 8, the PU 1 sequentially writes the program data into the SRAM 3 via a partially scrambled bus. Thereafter, the CPU 1 copies the application program in the SRAM 3 to the flash memory 4 and executes the program in the flash memory 4 to perform application processing.

FIG. 2 is a circuit diagram showing an example of the address scramble circuit 6, which comprises a scramble key register 6A and a bus connection switching section 6B. In addition,
The bus connection switching unit 6B includes AND gates 81 to 84 and OR gates 85 and 86. Immediately after the reset signal RESET is input, the scramble key register 6A outputs the output terminals SEL1 and SEL2.
Are H level (ie, “1”) and L level (ie, “0”), respectively.

The scramble key register 6A
Is an input terminal of one of AND gates 81 and 83 of the bus connection switching unit 6B, and an output terminal SEL2 of the scramble key register 6A is one input terminal of AND gates 82 and 84 of the bus connection switching unit 6B. It is connected to the. Here, as shown in FIG. 2, the uppermost address bit line A of the address bus AB from the CPU 1
Bn is connected to the other input terminal of the AND gates 81 and 82, and the next address bit line ABn-1 is connected to the AND gate 8
3 and 84 are connected to the other input terminals, so that when each of the address bit lines ABn and ABn-1 is "0" and "0", respectively, each AND gate 81
The output of .about.84 becomes "0", so that the OR gate 8
5 and 86, the corresponding scramble address bit line S output to the SRAM 3 or the flash memory 4
QABn and SQABn-1 are also "0" and "0", respectively.

Further, each address bit line ABn, ABn
When -1 is "0" and "1" respectively, the output terminal SEL of the scramble key register 6A immediately after the reset.
1 and SEL2 are “1” and “0”, respectively.
Is "1", and the output of the OR gate 86 connected to this is "1". As a result, the SRA
M3 or corresponding scramble address bit lines SQABn, SQABn-1 output to flash memory 4
Are "0" and "1", respectively. When the address bit lines ABn and ABn-1 are "1" and "0", respectively, only the output of the AND gate 81 becomes "1" immediately after resetting. Alternatively, the corresponding scramble address bit lines SQABn, S output to the flash memory 4
QABn-1 is "1" and "0", respectively.

Further, each address bit line ABn, AB
When n-1 is "1" and "1", respectively, only the outputs of the AND gates 81 and 83 become "1" immediately after the reset.
The corresponding scramble address bit lines SQABn, SQABn- output to the AM 3 or the flash memory 4
1 is “1” and “1”, respectively. Thus, immediately after the reset, the values corresponding to the values of the address bit lines ABn and ABn-1 output from the CPU 1 are respectively set to the scramble address bit lines SQABn and SQABn-1.
Is output to the SRAM 3 or the flash memory 4.

Immediately after the reset, the CPU 1 designates the scramble key register 6A by the address bus AB, sets a predetermined value to the designated scramble key register 6A via the data bus DB, and sets its output terminals SEL1, SEL2 is "0",
If it becomes "1", each address bit line ABn,
When ABn-1 is "0" and "0", respectively, the corresponding scramble address bit lines SQABn, SQABn
-1 are "0" and "0", respectively. When the address bit lines ABn and ABn-1 are "0" and "1" respectively, only the output of the AND gate 84 becomes "1".
Therefore, the output of the OR gate 85 connected thereto is "1".
Therefore, the SRAM 3 or the flash memory 4
Corresponding scramble address bit line SQ output to
ABn and SQABn-1 are "1" and "0", respectively.

Each address bit line ABn, ABn
When -1 is "1" and "0", respectively, only the output of the AND gate 82 becomes "1", and the output of the OR gate 86 connected thereto becomes "1".
M3 or corresponding scramble address bit lines SQABn, SQABn-1 output to flash memory 4
Are "0" and "1", respectively. By setting a predetermined value in the scramble key register 6A immediately after the reset, the address bit line ABn output from the CPU 1 is changed to the scramble address bit line SQABn-1 input to the SRAM 3 or the flash memory 4.
And the address bit line ABn-1 output from the CPU 1 is switched to the SRAM 3 or the flash memory 4.
Address bit line SQABn input to
Can be switched to

Therefore, the program data written by the CPU 1 to the SRAM 3 or the flash memory 4 through the address bit line ABn is the scramble address bit line SQABn of the SRAM 3 or the flash memory 4.
It is written to the area corresponding to -1. CPU1
Is written to the SRAM 3 or the flash memory 4 by the address bit line ABn-1.
The data is written to an area of the RAM 3 or the flash memory 4 corresponding to the scramble address bit line SQABn. As a result, even if a third party reads out the program data written in the flash memory 4 through the address bus AB and the data bus DB, for example, a program to be continued is divided from the flash memory 4 and another program is read out. Since random program data such as the one following the program is read, program analysis by a third party becomes impossible.

In the example shown in FIG. 2, the upper address bit lines ABn and ABn-1 of the address bit lines AB0 to ABn of the address bus AB from the CPU 1 are scrambled, and the other address bit lines AB0 to ABn are scrambled.
Bn-2 SRAM3 without scrambling
Alternatively, although an example of direct connection to the flash memory 4 has been described, scrambling may be applied to all the address bit lines AB0 to ABn.

FIG. 3 is a circuit diagram showing a specific configuration of the data scramble / descramble circuit 5 shown in FIG. This circuit 5 has a scramble key register 5A.
And a bus connection switching unit 5B. The bus connection switching unit 6B includes a scramble circuit 5B1 and a descramble circuit 5B2. The scramble circuit 5B1 includes AND gates 51 to 54 and an OR gate 5
5 and 56, and gate circuits 57 and 58.
The descramble circuit 5B2 includes an AND gate 6
1 to 64, OR gates 65 and 66, and gate circuit 6
7, 68.

The gate circuit 71 in the bus connection switching section 6B receives an "L" level (= "0") from the CPU 1 when writing data to the SRAM 3 or the flash memory 4.
Is output when the chip select signal CS is output, and each gate circuit 57 of the scramble circuit 5B1 is output.
The signal is passed to the gate circuit 58 to turn on the respective gate circuits 57 and 58 to pass the signal. Further, the gate circuit 72 in the bus connection switching unit 6B receives the “L” level (= “0”) chip select signal C from the CPU 1 when reading data from the SRAM 3 or the flash memory 4.
When the read signal S and the read signal RD are output, “0” is output and each gate circuit 67 of the descrambling circuit 5B2,
The signal is passed to the gate circuit 68 to turn on the gate circuits 67 and 68. In the scramble key register 5A, just like the scramble key register 6A of the address scramble circuit 6 in FIG. 2, the output terminals SEL1 and SEL2 become "1" and "0", respectively, immediately after being reset by the input of the reset signal RESET. I have.

The output terminal SEL1 of the scramble key register 5A is connected to one of the input terminals of the AND gates 51 and 53 of the scramble circuit 5B1 and the AND gates 61 and 63 of the descramble circuit 5B2, and the output terminal of the scramble key register 5A. SEL2 is connected to one input terminal of the AND gates 52, 54 of the scramble circuit 5B1 and one of the AND gates 62, 64 of the descramble circuit 5B2. Here, as shown in FIG.
The uppermost data bit line DBn of the data bus DB from the CPU 1 is connected to the other input terminal of the AND gates 51 and 52, and the next data bit line DBn-1 is connected to the other input terminal of the AND gates 53 and 54. When the CPU 1 selects the SRAM 3 or the flash memory 4 and writes data via the data bus DB, the data bit lines DBn and DBn−1 are “0” and “0”, respectively. In the case of, each AND gate 51-
The output of the OR gate 5 becomes "0", and
SRAM via the gate circuits 5 and 56 and the gate circuits 57 and 58
3 or the corresponding scrambled data bit lines SQDBn and SQDBn-1 output to the flash memory 4 also become "0" and "0", respectively.

Each data bit line DBn, DBn-
When 1 is “0” and “1”, respectively, the output terminals SEL1 and SEL1 of the scramble key register 5A immediately after reset.
Since SEL2 is "1" and "0", only the output of the AND gate 53 among the AND gates 51 to 54 becomes "1", and the output of the OR gate 56 connected thereto becomes "1". As a result, the corresponding scrambled data bit lines SQDBn and SQDBn-1 output to the SRAM 3 or the flash memory 4 also become "0" and "1", respectively. Also, each data bit line DB
When n and DBn-1 are "1" and "0", respectively, only the output of the AND gate 51 becomes "1" immediately after reset, and therefore, the corresponding scrambled data bit line SQD
Bn and SQDBn-1 are also "1" and "0", respectively. Further, when the data bit lines DBn and DBn-1 are "1" and "1", respectively, only the outputs of the AND gates 51 and 53 become "1" immediately after the reset, and accordingly, the corresponding scrambled data bit lines SQDBn, SQ
DBn-1 is "1" and "1", respectively. Thus, immediately after the reset, the scramble circuit 5B1 does not function, and when the CPU 1 outputs data via the data bus DB, the values corresponding to the values of the data bit lines DBn and DBn-1 are respectively scrambled data bits. Line SQD
Bn and SQDBn−1 are output to the SRAM 3 or the flash memory 4.

When data is read from the SRAM 3 or the flash memory 4 via the scrambled data bit lines SQDBn and SQDBn-1 immediately after the reset, the scrambled data bit lines SQDBn and SQDB
When DBn-1 is "0" and "0" respectively, the output of each of the AND gates 61 to 64 of the descramble circuit 5B2 becomes "0", and therefore, via the OR gates 65 and 66 and the gate circuits 67 and 68. The corresponding data bit lines DBn and DBn-1 output to the CPU 1 also become "0" and "0", respectively.

Each scramble data bit line SQ
When DBn and SQDBn-1 are "0" and "1", respectively, only the output of the AND gate 63 becomes "1" immediately after the reset, and therefore, the OR gate 66 connected thereto is provided.
Also becomes "1", the corresponding data bit lines DBn and DBn-1 outputted to the CPU 1 also become "0" and "1", respectively. Also, each of the scrambled data bit lines SQDBn and SQDBn-1 is "1",
In the case of "0", only the output of the AND gate 61 becomes "1" immediately after the reset, and therefore the output of the OR gate 65 connected thereto also becomes "1". Therefore, the corresponding data bit lines DBn, DBn -1 is also "1",
It becomes "0". Further, each of the scrambled data bit lines SQDBn and SQDBn-1 is "1" and "1", respectively.
In the case of, only the outputs of the AND gates 61 and 63 become "1" immediately after the reset, and the corresponding data bit lines DBn and DBn-1 become "1" and "1", respectively. Thus, immediately after the reset, the descramble circuit 5B2 also does not function, and when the CPU 1 inputs data from the SRAM 3 or the flash memory 4, the value corresponding to the value of each of the scrambled data bit lines SQDBn and SQDBn-1 is set to the data. Bit lines DBn, DBn-
1 to the CPU 1.

Immediately after the reset, the CPU 1 designates the scramble key register 5A by the address bus AB, sets a predetermined value to the designated scramble key register 5A via the data bus DB, and sets its output terminals SEL1, SEL2 is "0",
If it becomes "1", each data bit line DBn, D
When Bn-1 is "0" and "0", respectively, the corresponding scramble data bit line S of the scramble circuit 5B1
QDBn and SQDBn-1 are "0" and "0", respectively. When the data bit lines DBn and DBn-1 are "0" and "1", only the output of the AND gate 54 is "1". Therefore, the output of the OR gate 55 connected thereto becomes "1", so that the gate circuits 57, 5
8, the corresponding scrambled data bit line SQDB output to the SRAM 3 or the flash memory 4
n and SQDBn−1 are “1” and “0”, respectively.

Each data bit line DBn, DBn-
If 1 is “1” and “0” respectively, AND gate 5
2 becomes "1" and the output of the OR gate 56 connected thereto becomes "1". Therefore, the corresponding scrambled data output to the SRAM 3 or the flash memory 4 via the gate circuits 57 and 58 is output. Bit lines SQDBn and SQDBn−1 are “0” and “1”, respectively.
Becomes Thus, immediately after the reset, the predetermined value is set in the scramble key register 5A, and the scramble circuit 5A is set.
By making B1 function, the data output from the CPU 1 via the data bit line DBn is stored in the SRAM 3 or the flash memory 4 via the scrambled data bit line SQDBn-1, and the CPU 1
Is output from the RAM 3 or the flash memory 4 via the data bit line DBn-1 via the data bit line SQDBn. As a result, for example, even if the program data written in the flash memory 4 is read,
Stores scrambled program data different from the data output from the CPU 1 and thus cannot be decrypted by a third party.

Further, such scramble data is converted to SR
When reading from the AM 3 or the flash memory 4 via each of the scrambled data bit lines SQDBn, SQDBn-1, the scrambled data bit lines SQDBn,
If SQDBn-1 is "0" and "1", respectively, the AND gates 61 to 64 of the descramble circuit 5B2
Among them, only the output of the AND gate 64 becomes “1”,
Therefore, the output of the OR gate 65 connected thereto is "1".
CPU 1 through gate circuits 67 and 68
Corresponding data bit lines DBn, DBn-1 output to
Are "1" and "0", respectively. When the scrambled data bit lines SQDBn and SQDBn-1 are "1" and "0", respectively, the descramble circuit 5B
2 and only the output of the AND gate 62 becomes "1" and the output of the OR gate 66 connected thereto becomes "1". Therefore, the corresponding data bit lines DBn and DBn-1 are "0" and "1", respectively. ".

The data written in the SRAM 3 or the flash memory 4 from the CPU 1 through the scramble circuit 5B1 in this manner is transmitted to the descramble circuit 5B.
2 and output to the CPU 1. Note that FIG.
Of the data bit lines DB0 to DBn of the data bus DB from the CPU 1, the upper data bit line DB
n and DBn-1 are scrambled / descrambled, and the other data bit lines DB0 to DBn-2
, The above scramble / descramble processing is not performed, but all the data bit lines D
The scrambling / descrambling process may be performed on B0 to DBn.

Next, FIG. 5A shows the CPU 1 and the SRAM.
3 or the flash memory 4 via an address bus AB consisting of 18 address lines, of which the address bit lines to be scrambled are AB12 to AB15.
It is a figure showing the example in the case of having set it. In this case, an area of 4 Kbytes from address 0 to FFFH (hexadecimal) is a non-scramble area, in which a jump destination address at the time of reset and the above-described initialization program are stored. The area after the address 1000H (hexadecimal) is a scramble area, and the downloaded application program is stored in the scramble area. FIG. 5B shows the CPU.
Data bus DB consisting of 8 data lines between 1 and memory
FIG. 6 is a diagram showing an example in which the data bit lines to be scrambled are four bits DB4 to DB7.

In order to realize the area configuration shown in FIG. 5A, a decoder 5C for decoding an address bus is added to the data scramble / descramble circuit 5 shown in FIG. 3, as shown in FIG. This decoder 5C
Detects an unscrambled area of the address bus AB, and connects its output to one input terminal of an OR gate 73 and an AND gate 74. On the other hand, the other input terminals of the OR gate 73 and the AND gate 74 are connected to the respective output terminals SEL1, S1 of the scramble key register 5A.
EL2 is connected to each. The output of the OR gate 73 is supplied to the AND gates 51 and 53 of the scramble circuit 5B1.
And the AND gate 61 of the descramble circuit 5B2,
63 and the output of the AND gate 74 are connected to the AND gates 52 and 54 of the scramble circuit 5B1.
AND gate 62 of descramble circuit 5B2,
64, respectively.

With this configuration, the CPU 1 sets a predetermined value in the scramble key register 5A in order to scramble the data, and outputs the outputs SEL1 and SEL2.
Are "0" and "1", when the decoder 5C detects the non-scramble area and becomes "1", the outputs of the OR gate 73 and the AND gate 74 are both "1".
Therefore, the data bit lines DBn and DBn-1 are not scrambled by the scramble circuit 5B1 and are written in the memory as they are. The data read from the memory is also stored in the descramble circuit 5.
CP without performing descrambling by B2
U1.

As described above, the non-scramble area is detected by the address decoder 2, and the data of the detected non-scramble area is not subjected to the scramble / descramble processing.
As a result, the non-scramble area is allocated to a part of the flash memory 4, and an initialize program and a load program are stored in the area, and FIG.
Can be used like the ROM 2 of
OM2 can be omitted.

In the present embodiment, a predetermined scramble value is set in the scramble key registers 5A and 6A to perform address scrambling and data scrambling / descrambling.
The write protection for the scramble key register may be strengthened by setting the scramble key register 5A, 6A in such a manner that the setting becomes impossible unless other data of 2 bytes is set in addition to the fixed set value. Alternatively, a timer may be started after reset, and the setting may be prohibited except within a certain time of the timer.

[0031]

As described above, according to the present invention, C
A scrambling circuit between the PU and the memory for switching the data bus to a different pattern from the normal pattern when the CPU writes data to the memory; and a scramble circuit for switching the data bus from the different pattern to the normal pattern when the CPU reads data from the memory. Since a descrambling circuit for restoring the pattern is provided, when data is read from the memory, data that cannot be decrypted by a third party is read, and as a result, the program stored in the memory is read. It is possible to prevent unauthorized modification by three parties. Also, at least one of a scramble circuit for switching the address bus to a pattern different from the normal pattern when writing data and a descrambling circuit for restoring the address bus to the normal pattern when reading data is provided. Decryption of memory data can be disabled. Further, a writing means for writing program data to the memory and a scramble circuit for switching the bus are provided. When the CPU receives the program data, the CPU causes the scramble circuit to switch the bus based on a predetermined pattern. The program data is written to the memory via the memory, so that the scrambled data that cannot be decoded by a third party is written into the memory. As a result, even if the data in the memory is read, the data cannot be decoded by the third party. This makes it possible to prevent unauthorized modification of the program stored in the memory by a third party.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a memory read / write device according to the present invention.

FIG. 2 is a circuit diagram showing a configuration of an address scramble circuit in the device.

FIG. 3 is a circuit diagram showing a configuration of a data scramble / descramble circuit in the device.

FIG. 4 is a circuit diagram showing another configuration example of the data scramble / descramble circuit.

FIG. 5 is a diagram showing another example of address scrambling and data scrambling of the above device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... CPU, 2 ... ROM, 3 ... SRAM, 4 ... Flash memory, 5 ... Data scramble / descramble circuit, 5A, 6A ... Scramble key register, 5B,
6B: bus connection switching unit, 5B1: scramble circuit, 5
B2: descrambling circuit, 5C: decoder.

Claims (5)

[Claims] 1. A CPU comprising: a CPU; and a memory connected to the CPU via a bus including an address bus and a data bus, wherein the CPU writes data to the memory via the bus. In the apparatus, a first step of switching the bus to a pattern different from a normal pattern according to a predetermined condition when the CPU writes data to the memory; and a step of switching the bus to a normal pattern when the CPU reads data from the memory. And a second step of restoring to a pattern. 2. A memory read / write which comprises a CPU and a memory connected to the CPU via a bus including an address bus and a data bus, wherein the CPU writes data to the memory via the bus. In the apparatus, a first scramble circuit for switching the data bus to a pattern different from a normal pattern according to a predetermined condition between the CPU and the memory when the CPU writes data to the memory; And a first descramble circuit for restoring the data bus to a normal pattern when reading data from the memory. And a memory connected to the CPU via a bus including an address bus and a data bus, wherein the CPU writes data to the memory via the bus. In the device, a scramble circuit for switching the address bus to a pattern different from a normal pattern according to a predetermined condition when the CPU writes data to the memory between the CPU and the memory, and a CPU for reading data from the memory. A memory read / write device comprising at least one of a descramble circuit for restoring the address bus to a normal pattern. 4. The second scramble circuit according to claim 2, wherein, between the CPU and the memory, when the CPU writes data to the memory, the address bus switches to a pattern different from a normal pattern according to a predetermined condition. And a second method for restoring the address bus to a normal pattern when the CPU reads data from the memory.
A memory read / write device comprising at least one of the following descrambling circuits. 5. A memory read / write comprising a CPU and a memory connected to the CPU via a bus comprising an address bus and a data bus, wherein the CPU writes data to the memory via the bus. An apparatus, comprising: writing means for writing program data to the memory; and a scramble circuit provided between the CPU and the memory for switching a bus, wherein the CPU receives the program data and performs the scrambling based on a predetermined pattern. A memory read / write device, wherein a circuit switches the bus and program data is written to the memory by the writing means via the scramble circuit.