JPH11167522A - Data access method for information processor and semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the performance of an information processor by giving the main storage accesses issued by plural processors which can operate independently of each other to a single cache storage that is shared by the processors. SOLUTION: A CPU #0110 and a CPU #1111 operate independently of each other and separately send the main storage access requests and the main storage addresses to a BAA #0130 and a BAA #1131 included in a cache storage unit via the signal lines 193 and 194 respectively. Every CPU sends independently the write data to a cache storage 140 via a signal line 191 against a write access. A signal showing the presence or absence of a BAA entry based on the results of BAA entry index operations of both BAA #0130 and and BAA #1131 is sent to the storage 140 via a signal line 191. Then the contents of the BAA entry if exists and the main storage address are also sent to the storage 140 via a signal line 196.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data access method for an information processing apparatus and a semiconductor integrated circuit, and more particularly to a data access technique in a case where a plurality of processors share a cache memory and an application to realize this technique. Technology effective for semiconductor integrated circuits in multiprocessor system LSI with embedded memory

[0002]

2. Description of the Related Art In a conventional information processing apparatus, when a processor uses a cache memory, it is common that one processor incorporates one set of cache memory. Further, when implementing a multiprocessor system in which the information processing apparatus is constituted by a plurality of processors, one set of cache storage is provided for each processor, and the plurality of processors are connected to each other.
It was common to access and operate a set of shared main memories.

In a multiprocessor system of such an operation form, a situation in which copies of the same data in a shared main memory are present in separate cache memories built in different processors occurs very frequently. In this case, in order to operate the multiprocessor system normally, it is necessary to guarantee the consistency of copies of the same data in the shared main memory in different cache memories incorporated in different processors.

[0004] As a general means for guaranteeing the consistency of the above-mentioned copy of the same data, when an event occurs in which the consistency of the data is lost, the processor which has generated or detected this event is replaced by another processor or processor. A cancel request is issued for the data whose consistency has been lost to the group, and the other processors or the processor group are controlled so as not to use the data which has become inconsistent, thereby guaranteeing the consistency.

[0005] As a conventional technique for guaranteeing the coincidence, there is Japanese Patent No. 943867, for example. Other conventional techniques for guaranteeing the consistency include, for example, Da
vidA. Patterson and John L. He
Nesssy, Morgan Kaufmann P
published by Publishers, Inc. “ComputerAr
ticket A Quantitative
The details are described in “Approach Second Edition”.

Further, as a prior art in which a plurality of microprocessors are mounted in a one-chip semiconductor integrated circuit and a dedicated primary cache memory is connected to each of the microprocessors, for example, Japanese Patent Application Laid-Open No. 5-61768 discloses the prior art. As a conventional technique in which a processor and a dynamic random access memory (DRAM) are integrated in one chip, there is a technique disclosed in, for example, Japanese Patent Application Laid-Open No. 8-212185.

[0007]

When a dedicated cache memory is connected to each processor disclosed in the above-mentioned prior art and a multiprocessor system in which a plurality of processors are connected is constructed, as described above, coincidence of data copying is achieved. It is necessary to provide a means for ensuring the performance of the processor. Providing this means causes an increase in the number of control logic circuits of the processor, and executing the processing for causing the processor to function by the processor requires that the processor This leads directly to an increase in access time overhead when accessing the information processing device, which is a problem that cannot be ignored in improving the performance of the information processing apparatus.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned problems of the prior art by using a single cache shared by a plurality of processors for a main memory access issued from a plurality of independently operable processors. An object of the present invention is to provide a data access method and a semiconductor integrated circuit of an information processing apparatus, which can eliminate the problem of an increase in access time overhead when accessing the cache storage by performing the above operation on storage.

[0009] Here, the above-mentioned prior art No. 94
3867 and David A. Patterso
n and John L. Hennessy, Morga
Published by nKaufmann Publishers, Inc. “Computer Architecture A
Quantitative Approach Sec
On Edition "does not disclose a single cache memory shared by a plurality of processors integrated in one chip, and the above-mentioned other prior art, Japanese Patent Application Laid-Open No. Hei 5-61768, discloses: Although there is a disclosure about a dedicated cache storage accessed by a plurality of processors integrated in one chip, there is no disclosure about a single cache storage shared by a plurality of processors, and in the above-mentioned other prior arts. JP-A-8-21
Japanese Patent No. 2185 discloses a general DRAM accessed by a plurality of processors integrated in one chip, but does not disclose a single cache memory shared by a plurality of processors.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0011]

In order to achieve the above-mentioned object, the present invention provides a plurality of independently operable processors and a plurality of independently accessible memories integrated on the same chip. The memory includes a cache storage for temporarily storing data to be accessed by the processor, and the cache storage corresponds to a data address transmitted from the plurality of processors and a cache storage address. One or more block address arrays, each of which has a plurality of entries, and generally includes one or more block address arrays each including a block address storage unit for holding a data block address sent from the processor and a cache address storage unit for holding a corresponding cache storage address. It consists of a cache memory that holds a copy of the stored data, The cache storage is connected and configured as a single cache storage device commonly accessed by the plurality of independently operable processors, the cache storage device having a unique block address array for a plurality of processors, The unique block address array holds the entries corresponding to the data addresses accessed by the plurality of processors and the cache storage addresses for all the processors, and includes means for commonly using the data access requests from the plurality of processors. It is characterized by having.

Alternatively, the cache memory has a plurality of block address arrays respectively associated with the plurality of processors, and each block address array stores data corresponding to an access from each of the plurality of processors. It is also possible to have means for separately holding entries corresponding to addresses and cache storage addresses and processing data access requests from the plurality of processors corresponding to the processors. The accessible cache memory has a plurality of block address arrays corresponding to each of the plurality of processors, and each of the block address arrays stores a data address accessed from the plurality of processors and a cache memory. Address Means for storing all of the corresponding entries and processing means for processing data access requests from the plurality of processors corresponding to the processors, or the cache memory is provided in correspondence with each of the plurality of processors. Block address arrays,
Each block address array holds a corresponding entry of a data address and a cache storage address corresponding to each access from the plurality of processors, processes a data access request from the plurality of processors corresponding to the processor, If the corresponding entry of the data address and the cache storage address corresponding to the data access request from the processor does not exist in the block address array corresponding to this processor, the processor may have means for accessing the block address array corresponding to another processor. Alternatively, the cache memory has a plurality of sets of a plurality of block address arrays respectively associated with the plurality of processors, and each of the plurality of sets of the block address arrays is accessed by the plurality of processors. And holding the corresponding entry in the data address and the cache memory address corresponding to each
One of the plurality of sets of block address arrays processes a data access request from a corresponding one of the plurality of processors, and the plurality of sets of other block address arrays include the plurality of processors. May have means for processing data access requests from other processors.

By the above means, data access accompanying main memory access issued from a plurality of independently operable processors can be performed on a single cache memory shared by the plurality of processors. As a result, there is no need to provide a means for ensuring the consistency of data copying as described above, and as a result, the problem of an increase in access time overhead when accessing the cache memory can be eliminated. .

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings. Note that the same devices and members are denoted by the same reference numerals throughout the drawings for describing the embodiments, and the repeated description thereof may be omitted.

FIG. 1 is a block diagram showing an embodiment of a data access method and a semiconductor integrated circuit of an information processing apparatus according to the present invention. In particular, FIG. 1 shows a case where a processor accesses main storage data via cache storage. It shows the configuration of related parts.

In FIG. 1, a processor (hereinafter referred to as a CPU)
) Is composed of two units, each including a processor # 0 (hereinafter, referred to as CPU # 0) 110 and a processor # 1 (hereinafter, referred to as CPU # 1) 111. The CPU # 0110 and the CPU # 1111 are connected to a common cache storage unit 120, respectively. CPU # 0110 and CPU # 1111 are connected to signal line 1
The block address array (hereinafter referred to as BAA) in the cache storage unit 120 is connected to the cache storage 140 constituting the cache storage unit 120 via a signal line 193 and a signal line 193. BAA # 0130 and B
AA # 1131.

The cache storage unit 120 stores the C
Two BAAs holding a plurality of entries (hereinafter referred to as BAA entries) for associating data addresses sent from PU # 0110 and CPU # 1111 with cache storage addresses, and cache storage holding data actually used by the CPU. Consists of The two BAAs are respectively BAA # 0130 and BAA # 1131, and the cache storage 140 constitutes the cache storage unit 120. BAA # 0130 and BAA # 1131 are connected to each other via a signal line 192.
CPU # 0110 and CPU via signal line 93 and signal line 194
# 1 and further connected to the cache memory 140 via signal lines 195 and 196. The cache memory 140 is connected to the CPU # 0110 and the CPU # 1 via a signal line 191 respectively, and further connected to the BAA # 0130 and the BAA # 1131 via a signal line 195 and a signal line 196, respectively. Further, it is connected to a main memory (hereinafter, referred to as MS) 150 via a signal line 197.

The MS 150 is a main storage unit for storing data of the information processing apparatus according to the present invention.

Next, referring to FIG.
An operation in which PU # 1111 accesses MS 150 will be described.

The CPU # 0110 and the CPU # 1111 operate independently of each other, and independently transmit a main memory access request and a main memory address via a signal line 193 and a signal line 194 in the cache memory unit 120.
A # 0130 and BAA # 1131. In the case of write access, write data is sent to the cache memory 140 via the signal line 191 while being distinguished from each CPU. This distinction is realized by adding a CPU identification number and transmitting data if the signal line 191 is a shared path from each CPU. BAA # 0130 and BAA # 113 in the cache storage unit 120 which received the main storage access request and the main storage address from the CPU # 0110 and the CPU # 1111.
1 executes the indexing operation of each BAA entry and also outputs B to the other BAA via the signal line 192.
Send index request for AA entry. Then BAA # 0
As a result of the BAA entry indexing operation of 130 and BAA # 1131, a signal indicating whether or not the corresponding BAA entry exists, and if there is an approximate BAA entry, the contents of the entry and the main storage address are indicated by a signal line 195 and a signal line 195. 1
The data is sent to the cache memory 140 via the discrimination device 96.

The cache memory 140 receives the index result of each BAA entry sent via the signal line 195 and the signal line 196 and the main memory address, and, if the corresponding BAA entry exists, from the entry, The cache storage 140 is accessed using the extracted cache storage address. If the corresponding BAA entry does not exist, the cache storage 140 is not accessed, and the main storage address and the main storage access request are sent to the MS 150.

The cache memory 140 further stores the corresponding BAA.
If the entry exists, if the main memory access request from the CPU is a read request, the data is read out and transmitted to the requesting CPU via the signal line 191 in a distinguished manner.
If the request is a write request, the write data sent via the signal line 191 is stored in the cache memory 1.
Write to 40. If there is no corresponding BAA entry, normal MS access is performed.

The configuration of the embodiment of the data access method and the semiconductor integrated circuit of the information processing apparatus according to the present invention has been described with reference to FIG.

Next, an embodiment of a data access method and a semiconductor integrated circuit of an information processing apparatus according to the present invention based on FIG. 1 will be described in detail with reference to the drawings.

(Embodiment 1) FIG. 2 is a diagram showing a configuration of a data access method and a semiconductor integrated circuit of an information processing apparatus according to Embodiment 1 of the present invention. FIG. 3 is a diagram showing Embodiment 1 of the present invention. FIG. 4, FIG. 5, and FIG. 6 are schematic layout diagrams of a semiconductor integrated circuit of an information processing apparatus according to a first embodiment of the present invention.
13 is a schematic layout diagram of a semiconductor integrated circuit according to a modification example of FIG.

First, a schematic configuration of the data access method of the information processing apparatus according to the first embodiment will be described with reference to FIG.

In FIG. 2, the CPU comprises two units, CPU # 0210 and CPU # 1211, respectively.
Consists of This CPU # 0210 and CPU # 1211
Are connected to a common BAA 230 via signal lines 293 and 294, respectively. The CPU # 0210 and the CPU # 1211 are connected to each other via a signal line 291 and further connected to the cache memory 240 via a signal line 298 and a signal line 299.

In the first embodiment, BAA corresponds to CPU # 0.
210 and CPU # 1211 both of them
Indicates the shared BAA in which the entry is used. That is, the BAA entry generated with the main memory access issued from the CPU # 0210 and the CPU # 1211
Generated with main memory access issued from
A entries are registered in a mixed manner, and the BAA entries registered in a mixed manner are CPU # 0210 and CPU # 1.
It is used for accessing the cache storage 240 from both of the 211. BAA 230 includes signal line 293 and signal line 2
It is connected to the CPU # 0210 and the CPU # 1211 via the respective 94, and further connected to the cache memory 240 via the signal line 295.

The cache memory 240 is connected to the CPUs # 0210 and # 1 via signal lines 298 and 299, respectively.
It is connected to the AA 230 and is also connected to the MS (not shown).

Next, the operation and operation of the main memory access performed by CPUs # 0210 and # 1211 according to the first embodiment will be described with reference to FIG.

The CPUs # 0210 and # 1211 operate independently of each other, and independently transmit a main memory access request and a main memory address to the BAA 230 via the signal lines 293 and 294. In the case of a write access, the write data is transferred to the cache memory 240 via the signal lines 298 and 299 and the respective CPs
It is transmitted independently for each U. The distinction of the data affiliation when the write data is transmitted independently is determined by the signal line 1
If the path 98 and the signal line 299 are shared paths from the respective CPUs, the CPU identification numbers are used. BAA 230 receiving main memory access request and main memory address from CPU # 0210 and CPU # 1211
Performs the indexing operation of the BAA entry independently for each request. Next, as a result of the BAA entry indexing operation of the BAA 230, a signal indicating whether or not the corresponding BAA entry exists and, if an approximate BAA entry exists, the contents of the entry and the main storage address are indicated by a signal line 295.
And sends the request to the cache storage 240 independently for each request.

The cache memory 240 receives the index result of each BAA entry sent via the signal line 295 and the signal line 296 and the main memory address, and, if the corresponding BAA entry exists, from the entry, The cache storage 240 is accessed using the extracted cache storage address. If the corresponding BAA entry does not exist, the cache storage 240 is not accessed, and the main storage address and the main storage access request are transmitted.

The cache memory 240 further stores the corresponding BAA.
When the entry exists, if the main memory access request from the CPU is a read request, the data is read and the requesting CPU is read via the signal lines 298 and 299.
And if the request is a write request,
The write data sent via the signal line 291 is written to the cache memory 240. If the corresponding BAA entry does not exist, normal main memory access is performed.

Next, the BAA 230 according to the first embodiment is used.
Some embodiments will be described in which the index operation of the BAA entry is executed independently for each request of each CPU. In this mode, the same BAA is sent from two CPUs.
Is shared.

As an example in which the index operation of the BAA entry of the BAA 230 is executed independently and simultaneously for each request of each CPU, first, a cycle time which is a half of a main memory access request signal transmission cycle transmitted from each CPU. The BAA 230 accepts the request signal,
In addition, there is a method in which the index operation of the BAA entry is operated in a cycle time that is half the cycle time. That is, B
CPU # 021 in the first cycle accepted by AA230
0, the request signal is received from the CPU # 1211 in the second cycle of receiving the request signal, and the receiving operation is repeatedly performed thereafter. The indexing operation of the BAA entry is performed in synchronization with the receiving operation. Also operates while switching the CPU one cycle at a time.

According to this method, an effect equivalent to operating each of the two CPUs while occupying the BAA can be obtained. Further, since the same BAA can be almost completely shared by the two CPUs, the use of the BAA There is a feature that the efficiency is high and the physical capacity of the BAA can be reduced.

As another example in which the indexing operation of the BAA entry of the BAA 230 is executed independently and simultaneously for each request of each CPU, first, the cycle time of the main memory access request signal transmitted from each CPU and There is a method in which the BAA 230 receives the request signal in the same cycle time and the index operation of the BAA entry is operated in the same cycle time as the cycle time. That is, the BAA 230 receives the request signal from the CPU # 0210 and the request signal from the CPU # 1211 in the same cycle time, and further operates the BAA entry indexing operation in the same cycle time in synchronization with the receiving operation. . In this example, a case may occur in which the main memory access request signals from both CPUs are sent at the same time.
The index operation of the AA entry is made to operate after waiting for one cycle.

In this method, when the main memory access request signals from both CPUs are sent simultaneously, one C
The index operation of the BAA entry corresponding to the main memory access request of the PU is waited for one cycle, but an effect substantially equivalent to the operation of each of the two CPUs while occupying the BAA is obtained. BAA with two CPUs
, The BAA is used efficiently and the physical capacity of the BAA can be reduced.

Further, as another example in which the indexing operation of the BAA entry of the BAA 230 is executed independently and simultaneously for each request of each CPU, a plurality of BAA entries are pointed from a part of the main storage address. The BAA is composed of a plurality of independently operable storage banks, and the BAA 230 receives the request signal in the same cycle time as that of the main memory access request signal transmitted from each CPU, In addition, there is a method of operating the BAA entry in the same cycle time as the above-mentioned cycle time. That is, BAA
230 is the request signal from CPU # 0210 and CP
The request signal from U # 1211 is received in the same cycle time, and the index operation of the BAA entry is also operated in the same cycle time in synchronization with this reception operation. Also in this example, the main memory access request signals from both CPUs may be sent at the same time. However, if an index operation is performed on a BAA entry of a different bank in the BAA, two sets of BAA entries are executed in the same cycle time. And if the index operation is for an BAA entry in the same bank, the BA corresponding to the main memory access request of one of the CPUs
The indexing operation of the A entry is operated with one cycle wait.

In this method, when the main memory access request signals from both CPUs are sent at the same time, one C
It is possible to reduce the frequency of waiting for one cycle of the index operation of the BAA entry corresponding to the main memory access request of the PU, and to obtain an effect substantially equivalent to that when each of the two CPUs operates while occupying the BAA. And
BAA because the same BAA can be shared by two CPUs
Is characterized in that the use efficiency of the BAA is high and the physical capacity of the BAA can be reduced.

In this method, the BAA is replaced with a plurality of CPs.
To share from U, in order to ensure sufficient processing performance, it is necessary to implement a BAA entry index sequence that can follow a cycle of sending a main memory access request signal from a plurality of CPUs by means of a logical circuit. . Next, a layout method of the CPU, the BAA, and the cache storage, which is a feature of the semiconductor integrated circuit of the information processing device according to the first embodiment, will be described.

First, a schematic configuration of the semiconductor integrated circuit of the information processing apparatus according to the first embodiment will be described.

The semiconductor integrated circuit of the information processing apparatus according to the first embodiment is, for example, a memory-embedded system LSI composed of a so-called independently accessible memory group, and includes a plurality of independently accessible memory cells and an independent memory cell. This is a multiprocessor system composed of a plurality of operable CPUs, and these are integrated on the same chip to form a system LSI integrated into one chip.

The plurality of memory cell regions are constituted by a group of memory cells having the same or different physical structures for each region. For example, a plurality of memory cells arranged in a lattice and a column / row for selecting the memory cells are provided. A decoder, a sense amplifier for amplifying read data, and the like are provided.

Next, Embodiment 1 of the present invention will be described with reference to FIG.
An example of a layout method in a semiconductor integrated circuit will be described.

FIG. 3 is a schematic layout diagram of a semiconductor integrated circuit as one example according to the first embodiment of the present invention. In the first embodiment, as shown in FIG.
3 illustrates a shared BAA in which all the BAA entries are used by both the CPU # 1211 and the memory cell area of the BAA 230 in the center of the chip as shown in FIG. The logic circuit area of # 1211 is arranged so that both CPUs are adjacent to the memory cell area of the BAA 230. The memory cell area of the cache memory 240 is BAA as shown in FIG.
CPU # 0210 adjacent to the memory cell area 230
And the CPU # 1211 on the opposite side of the logic circuit area.

By arranging the logic circuit area of CPU # 0210 and CPU # 1211 and the memory cell area of BAA 230 adjacent to each other, the contact surface between CPU and BAA can be increased, and as a result, data between CPU and BAA can be increased. The width of the path can be widened and the path length can be shortened. Similarly, by arranging the memory cell area of the cache memory 240 adjacent to the memory cell area of the BAA 230, the contact area between the BAA and the cache memory can be increased, and as a result, the width of the data path between the BAA and the cache memory can be increased. Can be widened and the path length can be shortened.

As described above, increasing the width of the data path between the areas means that the number of signal lines between the areas can be increased, and the data transfer amount per unit time can be increased. Further, the data transfer delay time between the areas can be reduced by shortening the path length between the areas.

In the arrangement shown in FIG.
The area of the cache memory 240 is cut into both ends or the center of the 230, and the area of the cache memory 240 is
There is also a method of laying out the area adjacent to the area of # 0210 and CPU # 1211.

Next, Embodiment 1 of the present invention will be described with reference to FIG.
Another example of the layout method in the semiconductor integrated circuit will be described.

FIG. 4 is a schematic layout diagram of a semiconductor integrated circuit which is one example of the shared BAA method shown in FIG. 2 according to the first embodiment of the present invention. In the first embodiment, as described above,
Since both the CPUs # 0210 and # 1211 exemplify a shared BAA in which all of the BAA entries are used, the BAA2 is located at the center of the chip as shown in FIG.
30 memory cell areas are arranged, and CPU # 0210 and C #
In the logic circuit area of PU # 1211, both CPUs
It is arranged adjacent to and surrounding the memory cell area of A230. The memory cell area of the cache memory 240 is arranged adjacent to and surrounding the memory cell area of the BAA 230 as shown in FIG.
10 and the logic circuit area of the CPU # 1211 are also arranged adjacent to each other. Then, they are arranged on the opposite side of the logic circuit area of CPU # 0210 and CPU # 1211.

As shown in FIG. 4, when the regions are adjacent to each other with a refracted surface, the contact surface between the regions can be made larger. As a result, the width of the data path between the CPU and the BAA and the width of the data path between the BAA and the cache memory can be made wider, and the positioning of the data path when arranging the data path within a large contact surface is flexible. , The variation in the data transfer delay time due to the arrangement position between the regions can be suppressed, and an efficient data path layout can be realized. Furthermore, CPU
And the cache storage are arranged adjacent to each other, the width of the data path between the quantity areas can be made wider and shorter. As described above, the contact surface can be widened and the data path length can be shortened.

Next, Embodiment 1 of the present invention will be described with reference to FIG.
Another example of the layout method in the semiconductor integrated circuit will be described.

FIG. 5 is a schematic layout diagram of a semiconductor integrated circuit which is an example of the shared BAA method shown in FIG. 2 according to the first embodiment of the present invention. In the first embodiment, as described above,
Since both the CPUs # 0210 and # 1211 exemplify a shared BAA in which all of the BAA entries are used, the BAA2 is located at the center of the chip as shown in FIG.
The memory cell area of the cache memory 240 is divided into two memory cell areas.
In the logic circuit area of # 1211, both CPUs are BAA2
It is arranged adjacent to 30 memory cell areas. Then, the memory cell area of the cache memory 240 is arranged adjacent to both sides of the memory cell area of the BAA 230 as shown in FIG.

As shown in FIG. 5, the cache storage 240
By halving and adjoining each other, and enabling each of the halved cache memories to operate independently, BA
The width of the data path between the cache memory A and the cache memory can be made wider, and the simultaneous access operation to the two cache memories becomes possible.
Efficient processing of the main memory access request from the server 211 can be performed. Further, by dividing the cache memory into two and symmetrically arranging them from the BAA, it is possible to suppress a variation in the data transfer delay time depending on the arrangement position between the respective areas.

Next, Embodiment 1 of the present invention will be described with reference to FIG.
Another example of the layout method in the semiconductor integrated circuit will be described.

FIG. 6 is a schematic layout diagram of a semiconductor integrated circuit which is one example of the shared BAA method shown in FIG. 2 according to the first embodiment of the present invention. In the first embodiment, as described above,
Since both the CPUs # 0210 and # 1211 exemplify a shared BAA in which all of the BAA entries are used, the BAA2 is located at the center of the chip as shown in FIG.
30 memory cell areas are arranged, and CPU # 0210 and CPU # 12 are arranged on both sides of the memory cell area of BAA 230.
11 are arranged adjacent to each other, and the BAA 23
Cache memory 2 bisected on both sides of memory cell area 0
40 are arranged adjacent to each other.

As shown in FIG.
By halving and adjoining each other, and enabling each of the halved cache memories to operate independently, BA
The width of the data path between the cache memory A and the cache memory can be made wider, and the simultaneous access operation to the two cache memories becomes possible.
Efficient processing of the main memory access request from the server 211 can be performed. In addition, by dividing the cache memory into two and symmetrically arranging them from the BAA, an effect is obtained that variation in the data transfer delay time due to the arrangement position between the respective areas can be suppressed.

(Embodiment 2) FIG. 7 shows a configuration of a data access method and a semiconductor integrated circuit of an information processing apparatus according to Embodiment 2 of the present invention. FIG. 8 shows Embodiment 2 of the present invention. FIGS. 9, 10, 11 and 12 are schematic layout diagrams of a semiconductor integrated circuit according to a modification of the second embodiment of the present invention.

First, a schematic configuration of the data access method of the information processing apparatus according to the second embodiment will be described with reference to FIG.

In FIG. 7, the CPU comprises two units, CPU # 0710 and CPU # 1711, respectively.
Consists of The CPU # 0710 and the CPU # 1711
Are respectively connected to BAA # 0730 and BAA # 1731 via signal lines 793 and 794, respectively. The CPU # 0710 and the CPU # 1711 are connected to each other via a signal line 791.
8 and a cache memory 740 via a signal line 799, respectively.

In the second embodiment, BAA corresponds to CPU # 0.
BAA from both 710 and CPU # 1711
The entry is used exclusively. That is, CPU # 07
The BAA entry generated with the main memory access issued from the CPU # 1711 and the BAA entry generated with the main memory access issued from the CPU # 1711 are separately registered in the respective BAAs, and these are separately registered. The registered BAA entries are CPU # 0710 and CPU # 17.
11 is used to access the cache storage 740 from both sides. BAA # 0730 and BAA # 1731 are connected to CPU # 0710 and CPU # 1711 via signal lines 793 and 794, respectively.
95 and a signal line 796 to the cache storage 740.

The cache memory 740 stores data in the CPUs # 0710 and # 17 via signal lines 798 and 799, respectively.
11 respectively, and BAA # 0730 and BAA # 17 via signal lines 795 and 796, respectively.
31 and MS (not shown)
Is also connected.

Next, the operation and operation of the main memory access performed by CPUs # 0710 and # 1711 according to the second embodiment will be described with reference to FIG. In this mode, two CPUs occupy different BAAs.

CPU # 0710 and CPU # 1711 operate independently, and independently transmit main memory access requests and main memory addresses to BAA # 0730 and BAA # 1731 via signal lines 793 and 794, respectively. I do. In the case of write access, write data is sent to the cache memory 740 via the signal line 798 and the signal line 798 independently for each CPU.

B receiving the main memory access request and the main memory address from CPU # 0710 and CPU # 1711
The AA # 0730 and the BAA # 1731 independently execute a BAA entry indexing operation for each request.
Next, as a result of the BAA entry indexing operation of BAA # 0730 and BAA # 1731, a signal indicating whether or not the corresponding BAA entry exists, and if there is an approximate BAA entry, the contents of the entry and the main storage address are transferred to signal line 7.
The request is sent independently to the cache storage 740 via the signal line 95 and the signal line 796.

The cache memory 740 receives the index result of each BAA entry sent via the signal line 795 and the signal line 796 and the main memory address. The cache storage 740 is accessed using the extracted cache storage address. If the corresponding BAA entry does not exist, the cache storage 740 is not accessed, and the main storage address and the main storage access request are transmitted.

The cache memory 740 further stores the corresponding BAA.
If the entry exists, if the main memory access request from the CPU is a read request, the data is read and the requesting CPU is read via signal lines 798 and 799.
If the request is a write request, the write data sent via the signal line 791 is written to the cache memory 740. If the corresponding BAA entry does not exist, normal main memory access is performed.

In this mode, the two CPUs have separate BAA
In this method, two CPUs are used.
Are operating while occupying the BAA,
Even if the main memory access request signals from both CPUs are sent at the same time, the index operation of the BAA entry corresponding to the main memory access request of one of the CPUs does not wait, and the efficient BAA entry of the BAA entry is not waited. There is a feature that an indexing operation can be realized.

Further, according to this method, even when the target data exists in the cache storage, the target BAA entry does not exist in the BAA exclusively used by the CPU that issued the main storage access request, and the cache storage is performed. In some cases, main memory access is executed without access. Next, a layout method of the CPU, the BAA, and the cache storage, which is a feature of the semiconductor integrated circuit of the information processing device according to the second embodiment, will be described.

First, a second embodiment of the present invention will be described with reference to FIG.
An example of a layout method in a semiconductor integrated circuit will be described.

FIG. 8 is a schematic layout diagram of a semiconductor integrated circuit as one example according to the second embodiment of the present invention. In the second embodiment, as shown in FIG.
FIG. 8 illustrates a dedicated BAA used exclusively by each of the BAA entries from both the CPU and the CPU # 1711. Therefore, as shown in FIG.
0 and a memory cell area of BAA # 1731
The logic circuit areas of U # 0710 and CPU # 1711 are arranged so that both CPUs are adjacent to the memory cell areas of BAA # 0730 and BAA # 1731. Then, as shown in FIG.
It is arranged adjacent to the memory cell area of AA # 0730 and BAA # 1731 and opposite to the logic circuit area of CPU # 0710 and CPU # 1711.

Logic Circuit Area of CPU # 0710 and BAA
730 is arranged adjacent to the memory cell area, and the CPU #
By arranging the logic circuit area 1711 and the memory cell area of the BAA 731 adjacent to each other,
By arranging the BAA occupied and used by the CPU adjacent to the CPU, the width of the data path between the CPU and the BAA can be widened and the path length can be shortened. Similarly, by arranging the memory cell area of the cache memory 740 adjacent to the memory cell areas of BAA # 0730 and BAA # 1731, the contact surface between the BAA and the cache memory can be increased, and as a result, the BAA and the cache memory can be stored. The width of the data path between them can be widened and this path length can be shortened.

As described in the first embodiment of the present invention, increasing the width of the data path between the areas means
This means that the number of signal lines between the areas can be increased, and the data transfer amount per unit time can be increased. Further, the data transfer delay time between the areas can be reduced by shortening the path length between the areas.

In the arrangement shown in FIG.
The area of the cache memory 740 is cut into both ends or the center of # 0730 and BAA # 1731, and the area of the cache memory 740 is changed to the CPU # 0710 and the CPU # 1711.
There is also a method of taking a layout that is adjacent to the region of FIG.

Next, a second embodiment of the present invention will be described with reference to FIG.
Another example of the layout method in the semiconductor integrated circuit will be described.

In the second embodiment, as shown in FIG.
0710 and CPU # 1711 from both BA
Since a dedicated BAA used exclusively by the A entry is illustrated, as shown in FIG.
0730 and a memory cell area of BAA # 1731 are arranged, and a logic circuit area of CPU # 0710 and CPU # 1711 is provided with both CPUs BAA # 0730 and BAA # 17.
31 are arranged adjacent to one side of the memory cell area. The memory cell area of the cache memory 740 is disposed adjacent to the memory cell area of BAA # 0730 and BAA # 1731, as shown in FIG.
And the logic circuit area of the CPU # 1711.

When the regions are adjacent to each other as shown in FIG. 9, the contact area between the regions can be increased. As a result, the width of the data path between the CPU and the BAA and the width of the data path between the BAA and the cache storage can be made wider. Can be made wider and shorter. As described above, the contact surface can be widened and the data path length can be shortened.

Further, as shown in FIG. 9, BAA # 073
0 and BAA # 1731 are arranged at both ends of the chip, and the logic circuit areas of CPU # 0710 and CPU # 1711 are both CPUs BAA # 0730 and BAA # 1731.
A # 1731 is arranged adjacent to one side of the memory cell area and symmetrically, and the cache memory is stored in two B
By symmetrically arranging them between AA, it is possible to obtain an effect that variation in the data transfer delay time due to the arrangement position between the respective regions can be suppressed.

Next, another example of the layout method in the semiconductor integrated circuit according to the second embodiment of the present invention will be described with reference to FIG.

In the second embodiment, as described above, the CPU
B from both # 0710 and CPU # 1711
Since a dedicated BAA used exclusively by the AA entry is illustrated, the memory cell area of the cache memory 740 is arranged at the center of the chip as shown in FIG. BAA # 073
0 and the memory cell areas of BAA # 1731 are arranged adjacent to each other, and the CPU # 0710 and CPU # 1711 are located outside the memory cell areas of BAA # 0730 and BAA # 1731.
Are arranged adjacent to each other.

As shown in FIG. 10, by arranging the two BAAs and the two CPUs symmetrically with the cache memory at the center, the variation in the data transfer delay time depending on the arrangement position between the areas can be suppressed. Is obtained.

Next, another example of the layout method in the semiconductor integrated circuit according to the second embodiment of the present invention will be described with reference to FIG.

In the second embodiment, as described above, the CPU
B from both # 0710 and CPU # 1711
Since a dedicated BAA used exclusively by the AA entry is illustrated, as shown in FIG.
A # 0730 and BAA # 1731 memory cell areas are arranged adjacent to each other, and CPU # 0710 and CPU # 0710 are located on both sides of the memory cell areas of BAA # 0730 and BAA # 1731.
The logic circuit area of # 1711 is arranged adjacently, and BA
The cache memory 740 divided into two is arranged adjacent to both sides of the memory cell area of A # 0730 and BAA # 1731.

As shown in FIG.
0 by bisecting and adjoining, and enabling each of the bisected caches to operate independently, B
The width of the data path between the AA and the cache memory can be made wider and the simultaneous access operation to the two cache memories becomes possible.
The efficient processing of the main memory access request from 1711 can be performed. In addition, by dividing the cache memory into two and symmetrically arranging them from the BAA, an effect is obtained that variation in the data transfer delay time due to the arrangement position between the respective areas can be suppressed.

Next, another example of the layout method in the semiconductor integrated circuit according to the second embodiment of the present invention will be described with reference to FIG.

In the second embodiment, as described above, the CPU
B from both # 0710 and CPU # 1711
Since the dedicated BAA used exclusively by the AA entry is illustrated, as shown in FIG.
The logic circuit areas of U # 0710 and CPU # 1711 are arranged adjacent to each other, and CPU # 0710 and CPU # 1710 are arranged.
BAA # 0730 and BAA on both sides of the 11th logic circuit area
The memory cell area of # 1731 is arranged adjacently, and
The two separate cache memories 740 are arranged adjacent to both sides of the logic circuit area of PU # 0710 and CPU # 1711.

As shown in FIG.
0 by bisecting and adjoining, and enabling each of the bisected caches to operate independently, B
The width of the data path between the AA and the cache memory can be made wider and the simultaneous access operation to the two cache memories becomes possible.
The efficient processing of the main memory access request from 1711 can be performed. In addition, by dividing the cache memory into two and symmetrically arranging them from the BAA, an effect is obtained that variation in the data transfer delay time due to the arrangement position between the respective areas can be suppressed.

(Embodiment 3) FIG. 13 is a diagram showing a configuration of a data access method and a semiconductor integrated circuit of an information processing apparatus according to Embodiment 3 of the present invention, and FIG. 14 is Embodiment 3 of the present invention. FIG. 15 is a schematic layout diagram of a semiconductor integrated circuit according to a modification of the third embodiment of the present invention.

First, the schematic configuration of the data access method of the information processing apparatus according to the third embodiment will be described with reference to FIG.

In FIG. 13, the CPU comprises two units, CPU # 01310 and CPU # 11, respectively.
311. This CPU # 01310 and CPU # 1
1311 is a signal line 1393 and a signal line 1394, respectively.
BAA # 01330 and BAA # 113 via
31. CPU # 01310 and CPU #
11311 are mutually connected via a signal line 1391, and further connected to the cache memory 1340 via a signal line 1398 and a signal line 1399, respectively.

In the third embodiment, BAA corresponds to CPU # 0.
The BAA is exclusively used for reference access to the respective BAA entries from both the 1310 and the CPU # 11311. That is, the BAA entry generated with the main memory access issued from the CPU # 01310 and the BAA entry generated with the main memory access issued from the CPU # 11311 are B respectively.
AA # 01330 and BAA # 11331 are registered in both, and the BAA entry registered in both of them is a CPU #
It is used for accessing the cache storage 1340 from both the 01310 and the CPU # 11311. BAA # 01
330 and BAA # 11331 are connected to CPU # 01310 and CPU # 11 via signal line 1393 and signal line 1394, respectively.
311, and further connected to the cache memory 1340 via signal lines 1395 and 1396.

The cache memory 1340 includes a signal line 139
8 and the signal line 1399 to the CPU # 01310 and the CP
U # 11311, and BAA # 0133 via a signal line 1395 and a signal line 1396.
0 and BAA # 11331, and is also connected to an MS (not shown).

Next, the operation and operation of the main memory access by CPU # 01310 and CPU # 11311 according to the third embodiment will be described with reference to FIG. In this mode, two CPUs occupy different BAAs.

CPU # 01310 and CPU # 1131
1 operate independently of each other, and independently transmit a main memory access request and a main memory address via signal lines 1393 and 1394 to BAA # 01330 and BAA #.
11331. In the case of write access, write data is sent to the cache memory 1340 via the signal line 1398 and the signal line 1398 independently for each CPU.

CPU # 01310 and CPU # 1131
BAA # 01330 and BAA # 11331 that have received the main storage access request and the main storage address from
Perform entry indexing operations independently for each request. Then BAA # 01330 and BAA # 1133
As a result of the BAA entry index operation of No. 1, if there is a signal indicating whether or not the corresponding BAA entry exists and if there is an approximate BAA entry, the contents of the entry and the main storage address are transmitted via signal lines 1395 and 1396. The request is sent to the cache memory 1340 independently for each request.

The cache memory 1340 includes a signal line 139
5 and each B sent via signal line 1396
It receives the index result of the AA entry and the main storage address, accesses the cache storage 1340 using the cache storage address extracted from the entry if the relevant BAA entry exists, and caches the cache if the relevant BAA entry does not exist. Without accessing the storage 1340, the main storage address and the main storage access
Send to S. As a result of the main memory access to the MS, one block of the data in the main memory is stored in the cache memory 13.
40 and written into a predetermined block in the cache storage, and the main storage address and the cache storage address corresponding to the block are set to BAA # 01330 and BA
A is registered in both predetermined BAA entries of A # 11331.

The cache memory 1340 further stores the corresponding BA
If the A entry exists, and if the main memory access request from the CPU is a read request, the data is read out and sent to the requesting CPU via signal lines 1398 and 1399, and the request is written. If so, the write data sent via the signal line 1391 is written to the cache memory 1340. Applicable BA
If the A entry does not exist, normal main memory access is performed. At the time of this main storage access, one block of the main storage data is transferred to the cache storage 1340 and written in a predetermined cache storage block, and the main storage address and the cache storage address corresponding to the block are set to BAA # 01330. It is registered in both predetermined BAA entries of BAA # 11331. That is, BA
The BAA entry groups of both A # 01330 and BAA # 11331 have the same contents.

In this mode, the two CPUs have separate BAA
In this method, two CPUs are used.
Are operating while occupying the BAA,
Even if the main memory access request signals from both CPUs are sent at the same time, the index operation of the BAA entry corresponding to the main memory access request of one of the CPUs does not wait, and the efficient BAA entry of the BAA entry is not waited. An indexing operation can be realized, and furthermore, an effect equivalent to a case where the same BAA is completely shared by two CPUs is obtained.

Next, a layout method of the CPU, the BAA, and the cache storage, which is a feature of the semiconductor integrated circuit of the information processing apparatus according to the third embodiment, will be described.

First, an example of a layout method in a semiconductor integrated circuit according to the third embodiment of the present invention will be described with reference to FIG.

FIG. 14 is a schematic layout diagram of a semiconductor integrated circuit as one example according to the third embodiment of the present invention. In the third embodiment, as shown in FIG.
Each BA from both 310 and CPU # 11311
A illustrates a dedicated BAA used exclusively by A,
Each BAA has a BAA entry generated along with a main memory access issued from CPU # 01310 and a CP.
A BAA entry generated from the main memory access issued from U # 11311 is registered in each BAA, and the BAA entries registered in both are used for accessing cache storage from both of the two CPUs. Therefore, as shown in FIG.
1330 and the memory cell area of BAA1331 are arranged,
The logic circuit area of CPU # 01310 and CPU # 11311 is such that both CPUs are BAA1330 and BAA1331.
Are arranged adjacent to the memory cell region of The memory cell area of the cache memory 1340 is adjacent to the memory cell area of the BAA 1330 and the BAA 1331 as shown in FIG.
It is arranged on the opposite side of one logic circuit area.

Logic Circuit Area of CPU # 01310 and BA
A1330 and a memory cell area adjacent to each other.
By arranging the logic circuit area of U # 11311 and the memory cell area of the BAA 1331 adjacent to each other, the CPU and the BAA occupied by the CPU are arranged adjacent to each other, so that the data between the CPU and the BAA is arranged. The width of the path can be widened and the path length can be shortened. Further, by arranging the memory cell areas of BAA 1330 and BAA 1331 adjacent to each other, BAA 1
The contact surface between 330 and BAA 1331 can be increased, and as a result, the width of the data path between BAAs can be widened and the path length can be shortened. As a result, B
The registration operation for registering the same BAA entry in the memory cell areas of the AA 1330 and the BAA 1331 can be speeded up.

Similarly, by arranging the memory cell area of the cache memory 1340 adjacent to the memory cell area of the BAA 1330 and the BAA 1331, the contact area between the BAA and the cache memory can be increased. Can be widened and the path length can be shortened.

As described in the first embodiment of the present invention, increasing the width of the data path between the areas means
This means that the number of signal lines between the areas can be increased, and the data transfer amount per unit time can be increased. Further, the data transfer delay time between the areas can be reduced by shortening the path length between the areas.

In the arrangement shown in FIG.
The area of the cache memory 1340 is cut into both ends or the center of the A1330 and the BAA 1331, and the area of the cache memory 1340 is changed to the CPU # 01310 and the CPU # 11.
There is also a method of taking a layout that is adjacent to the area 311.

Next, another example of the layout method in the semiconductor integrated circuit according to the third embodiment of the present invention will be described with reference to FIG.

In the third embodiment, as described above, the CPU
Since a dedicated BAA used exclusively by each of the BAA entries from both # 01310 and CPU # 11311 is illustrated, the memory cell areas of BAA 1330 and BAA 1331 are adjacent to the center of the chip as shown in FIG. CPU # 01310 and CPU # 01310 on both sides of the memory cell area of BAA1330 and BAA1331.
The logic circuit area of # 11311 is arranged adjacent to
The cache memory 1340 divided into two is arranged adjacent to both sides of the memory cell area of the AA 1330 and the BAA 1331.

Therefore, as described above, by arranging the memory cell areas of BAA 1330 and BAA 1331 adjacent to each other, the contact area between BAA 1330 and BAA 1331 can be increased, and as a result, the width of the data path between BAA and cache memory can be increased. Can be widened and the path length can be shortened. As a result, BAA1330 and B
It is possible to speed up the registration operation when registering the same BAA entry in the memory cell area of the AA1331.

Further, as shown in FIG. 15, the cache memory 1340 is divided into two and arranged adjacent to each other, and each of the two divided cache memories can be operated independently. The width of the data path can be made wider and the simultaneous access operation to the two cache memories becomes possible.
0 and efficient processing of the main memory access request from the CPU # 11311 can be performed. In addition, by dividing the cache memory into two and symmetrically arranging them from the BAA, an effect is obtained that variation in the data transfer delay time due to the arrangement position between the respective areas can be suppressed.

(Embodiment 4) FIG. 16 is a diagram showing a configuration of a data access method and a semiconductor integrated circuit of an information processing apparatus according to Embodiment 4 of the present invention. FIG. 17 is a diagram showing Embodiment 4 of the present invention. 18 and 19 are schematic layout diagrams of a semiconductor integrated circuit according to a modification of the fourth embodiment of the present invention.

First, a schematic configuration of the data access method of the information processing apparatus according to the fourth embodiment will be described with reference to FIG.

In FIG. 16, the CPU is composed of two units, CPU # 01610 and CPU # 11, respectively.
611. This CPU # 01610 and CPU # 1
1611 is a signal line 1693 and a signal line 1694, respectively.
BAA # 01630 and BAA # 116 via
31. CPU # 01610 and CPU #
11611 are connected to each other via a signal line 1691, and further connected to the cache memory 1640 via a signal line 1698 and a signal line 1699.

In the fourth embodiment, BAA corresponds to CPU # 0.
1610 and CPU # 11611 from both B
AA entries are used in a combination of occupancy and sharing.
In other words, the BAA entry generated along with the main memory access issued from the CPU # 01610 and the CPU # 1
1611 and a BAA entry generated with the main memory access issued from the main memory 1611 are separately registered in the respective BAAs, and the separately registered BAA entries are
It is used for accessing the cache storage 1640 from both # 01610 and CPU # 11611. BAA # 0
1630 and BAA # 11631 are connected to each other via signal line 1692, and signal line 1693 and signal line 1694 are connected.
Are connected to the CPU # 01610 and the CPU # 11611 via a signal line 1695 and a signal line 169, respectively.
6 is connected to the cache storage 1640.

The cache memory 1640 stores the signal line 169
8 and the CPU # 01610 via the signal line 1699 and the CP
U # 11611, and BAA # 0163 via a signal line 1695 and a signal line 1696.
0 and BAA # 11631, and is also connected to an MS (not shown).

Next, the operation and operation of the main memory access performed by CPU # 01610 and CPU # 11611 according to the fourth embodiment will be described with reference to FIG. In this embodiment, two CPUs occupy different BAAs and are shared.

CPU # 01610 and CPU # 1161
1 operate independently of each other, and independently transmit a main memory access request and a main memory address via signal lines 1693 and 1694 to BAA # 01630 and BAA #.
To 11631. In the case of write access, write data is sent to the cache memory 1640 via the signal line 1698 and the signal line 1698 independently for each CPU.

CPU # 01610 and CPU # 1161
BAA # 01630 and BAA # 11631 that have received the main storage access request and the main storage address from
Perform entry indexing operations independently for each request. Then BAA # 01630 and BAA # 1163
As a result of the BAA entry index operation of No. 1, a signal indicating whether or not the corresponding BAA entry exists and, if a general BAA entry exists, the contents of the entry and the main storage address are transmitted via signal lines 1695 and 1696. The request is sent to the cache storage 1640 independently for each request. As a result of the BAA entry indexing operation of BAA # 01630 and BAA # 11631, if the corresponding BAA entry does not exist, the nonexistent BAA is also sent to the partner BAA via signal line 1692.
The entry index request and the main storage address are sent. In response to the index request, the partner BAA executes an indexing operation. As a result, when the BAA entry exists, the BAA on the side where the BAA entry exists signals the contents of the entry, the main storage address and the request source CPU number. Line 1
695 or cache storage 1 via signal line 1696
640 is sent independently for each request. When executing the BAA entry index request to the partner BAA, the signal line 1692 is in the busy state or the partner B
If the AA is in the busy state, the execution of the BAA index request is waited until the state is released.

The cache memory 1640 stores the signal line 169
5 and each B sent via signal line 1696
It receives the index result of the AA entry and the main storage address, and accesses the cache storage 1640 using the cache storage address extracted from the entry when the relevant BAA entry exists, and caches when the relevant BAA entry does not exist. The main memory address and the main memory access request are transmitted without accessing the memory 1640. After sending the main memory access request, when an access request to the cache memory 1640 indicating that the BAA exists in the partner BAA is sent via the signal line 1695 or the signal line 1696, the cache memory 1640 is sent. Performs processing for canceling the main memory access request.

The cache memory 1640 further stores the corresponding BA
If the A entry exists, and if the main memory access request from the CPU is a read request, the data is read and discriminated and transmitted to the requesting CPU via signal lines 1698 and 1699, and the request is written. If desired, sent over signal lines g98 and g99, this configuration is a combination of two CPUs occupying separate BAAs and sharing, but in this method two CPs are used.
Since each of U operates while occupying and sharing BAA, even if the main memory access request signals from both CPUs are sent at the same time, one C
The indexing operation of the BAA entry corresponding to the main memory access request of the PU is not waited, and an efficient indexing operation of the BAA entry can be realized, and the same BAA can be referred to by the two CPUs by referring to the partner BAA. There is a feature that the use efficiency of the BAA can be improved because it is shared by the users.

Further, according to this method, when an event in which the BAA is being used by the partner CPU occurs when referring to the partner BAA, the partner BAA reference operation is performed by the partner CPU. Is waited until the reference operation is completed. Next, a layout method of the CPU, the BAA, and the cache storage, which is a feature of the semiconductor integrated circuit of the information processing device according to the fourth embodiment, will be described.

First, an example of a layout method in a semiconductor integrated circuit according to the fourth embodiment of the present invention will be described with reference to FIG.

FIG. 17 is a schematic layout diagram of a semiconductor integrated circuit as one example according to the fourth embodiment of the present invention. In the fourth embodiment, as shown in FIG.
Each BA from both 610 and CPU # 11611
Since the A entry exemplifies a dedicated BAA used in a combination of occupancy and sharing, as shown in FIG. 17, memory cell areas of BAA # 01630 and BAA # 11631 are arranged in the center of the chip, and CPU # 01610 And CPU
In the logic circuit area of # 11611, both CPUs
They are arranged adjacent to the memory cell areas of # 01630 and BAA # 11631. And cache storage 1640
Memory area is BAA # 01 as shown in FIG.
630 and the memory cell area of BAA # 11631 and on the opposite side of the logic circuit area of CPU # 01610 and CPU # 11611.

Logic circuit area of CPU # 01610 and BA
A # 01630 is arranged adjacent to the memory cell area,
Logic circuit area of CPU # 11611 and BAA # 1163
By arranging one memory cell area adjacent to one memory cell area,
By arranging each CPU and the BAA used in a combination of exclusive use and common use for the CPU adjacent to each other, C
The width of the data path between the PU and the BAA can be widened and this path length can be shortened. Furthermore, BAA
By arranging the memory cell areas of # 01630 and BAA # 11631 adjacent to each other, BAA # 01630 and
The contact area between AA # 11631 can be increased, and as a result,
The width of the data path between BAAs can be widened and this path length can be shortened. As a result, BAA #
The data transfer operation between the memory cell areas of 01630 and BAA # 11631 can be speeded up.

Similarly, by arranging the memory cell area of the cache memory 1640 adjacent to the memory cell areas of BAA # 01630 and BAA # 11631,
And the contact area between the cache memory and the
The width of the data path between the BAA and the cache storage can be widened and this path length can be shortened.

As described in the first embodiment of the present invention, increasing the width of the data path between the areas means
This means that the number of signal lines between the areas can be increased, and the data transfer amount per unit time can be increased. Further, the data transfer delay time between the areas can be reduced by shortening the path length between the areas.

In the arrangement shown in FIG.
The area of the cache memory 1640 is cut into both ends or the center of A # 01630 and BAA # 11631, and the area of the cache memory 1640 is
There is also a method of laying out a region adjacent to the region of U # 11611.

Next, another example of a layout method in a semiconductor integrated circuit according to the fourth embodiment of the present invention will be described with reference to FIG.

In the fourth embodiment, as shown in FIG.
Since both BAA entries # 01610 and # 11611 exemplify dedicated BAAs used in a combination of occupancy and sharing, BAA # 01630 and BAA # 116 are provided at both ends of the chip as shown in FIG.
31 memory cell areas are arranged, and the logic circuit areas of CPU # 01610 and CPU # 11611 are arranged so that both CPUs are adjacent to one side of the memory cell area of BAA # 01630 and BAA # 11631. Then, the memory cell area of the cache memory 1640 has a BA
A # 01630 and BAA # 11631 are disposed adjacent to each other between the memory cell areas, and CPU # 01610 and CP #
It is also arranged adjacent to the logic circuit area of U # 11611.

When the regions are adjacent to each other as shown in FIG. 18, the contact area between the regions can be increased. As a result, the width of the data path between the CPU and the BAA and the BAA
The width of the data path between the memory and the cache memory can be made wider, and by arranging the CPU and the cache memory adjacent to each other, the width of the data path between the areas can be made wider and shorter. As described above, the contact surface can be widened and the data path length can be shortened.

Further, as shown in FIG.
630 and BAA # 11631 are arranged at both ends of the chip, and CPU # 01610 and CPU # 11
In the logic circuit area 611, both CPUs are BAA # 01.
630 and BAA # 11631 are arranged adjacently and symmetrically to one side of the memory cell area, and the cache memory is arranged symmetrically between the two BAAs, so that data transfer according to the arrangement position between each area is performed. The effect is obtained that the variation in the delay time can be suppressed.

Next, another example of a layout method in a semiconductor integrated circuit according to the fourth embodiment of the present invention will be described with reference to FIG.

In the fourth embodiment, as described above, the CPU
Since the respective BAA entries from both # 01610 and CPU # 11611 exemplify a dedicated BAA used in a combination of occupation and sharing, BAA # 01630 and BAA # 116 are provided at the center of the chip as shown in FIG.
31 memory cell areas are arranged adjacent to each other, and BAA # 01
The logic circuit areas of CPU # 01610 and CPU # 11611 are arranged adjacent to both sides of the memory cell area of 630 and BAA # 11631.
The cache memory 1640 divided into two is arranged adjacent to both sides of the memory cell area of AA # 11631.

As shown in FIG. 19, the cache memory 16
40 by bisecting and adjoining, and enabling each of the bisected caches to operate independently,
The width of the data path between the BAA and the cache memory can be made wider and the simultaneous access operation to the two cache memories becomes possible.
Efficient processing of a main memory access request from U # 11611 is made possible. Also, the cache memory is divided into two
By arranging symmetrically from AA, it is possible to obtain an effect that variation in the data transfer delay time due to the arrangement position between the respective regions can be suppressed.

(Embodiment 5) FIG. 20 is a diagram showing a configuration of a data access method and a semiconductor integrated circuit of an information processing apparatus according to Embodiment 5 of the present invention. FIG. 21 is a diagram showing Embodiment 5 of the present invention. 22, 23 and 24 are schematic layout diagrams of a semiconductor integrated circuit according to a modification of the fifth embodiment of the present invention. It is.

First, a schematic configuration of the data access method of the information processing apparatus according to the fifth embodiment will be described with reference to FIG.

In FIG. 20, the CPU is composed of two units, CPU # 02010 and CPU # 12, respectively.
011. This CPU # 02010 and CPU # 1
2011 denotes a signal line 2093 and a signal line 2094, respectively.
BAA # 02030 and BAA # 1 via
(C) 2033, BAA # 12031 and BAA # 0
(C) 2032. CPU # 02010
And the CPU # 12011 are connected to each other via a signal line 2091. Further, a signal line 2098 and a signal line 209 are connected to each other.
9 are respectively connected to the cache storage 2040.

In the fifth embodiment, BAA corresponds to CPU # 0.
B from both 2010 and CPU # 12011
AA entry is occupied and used. That is, CPU #
A BAA entry generated along with the main storage access issued from 02010 and a BAA entry generated along with the main storage access issued from the CPU # 12011 are separately registered in the respective BAAs. The registered BAA entries are CPU # 02010 and C #
Cache storage 2040 from both PU # 12011
Used for access. BAA # 0 (C) 2032 and BAA # 1 (C) 2033 are respectively BAA # 0203.
0 and a BAA having a copy of the contents of BAA # 12031.

BAA # 02030 and BAA # 12031
Is a CPU # via a signal line 2093 and a signal line 2094.
02010 and CPU # 12011, respectively.
Further, it is connected to the cache memory 2040 via a signal line 2095 and a signal line 2096, and is connected to BAA # 1.
(C) 2033 and BAA # 0 (C) 2032 are connected to the CPU # 02010 via the signal line 2093 and the signal line 2094.
And CPU # 12011, respectively, and further connected to cache storage 2040 via signal line 209b and signal line 209a.

The cache memory 2040 is connected to the signal line 209
And CPU # 02010 and CP via signal line 2099
U # 12011 and BAA # 02030 and BAA # 1 via signal lines 2095, 2096, 209a and 209b.
2031, BAA # 0 (C) 2032 and BAA # 1
(C) 2033, and is also connected to an MS (not shown).

Next, the operation and operation of the main memory access by CPU # 02010 and CPU # 12011 according to the fifth embodiment will be described with reference to FIG. In this mode, two CPUs occupy different BAAs.

CPU # 02010 and CPU # 1201
1 operate independently of each other, and independently transmit a main memory access request and a main memory address via a signal line 2093 and a signal line 2094 to BAA # 02030 and BAA #.
1 (C) 2033 and BAA # 12031 and BAA #
0 (C) 2032. In the case of write access, write data is sent to the cache memory 2040 via the signal line 2098 and the signal line 2098 independently for each CPU.

CPU # 02010 and CPU # 1201
BAA # 02030 and BAA # 1 (C) 2033 and BAA # 12031 and BAA # 0 (C) 2032 which have received the main storage access request and the main storage address from
The BAA entry indexing operation is performed independently for each request. Then BAA # 02030 and BAA # 1
(C) 2033, BAA # 12031 and BAA # 0
(C) As a result of the BAA entry indexing operation of 2032, a signal indicating whether or not there is a corresponding BAA entry and, if an approximate BAA entry exists, the contents of the entry and the main storage address are represented by signal lines 2095 and 209a. And the request is sent independently to the cache storage 2040 via the signal line 2096 and the signal line 209b.
BAA # 02030 and BA accompanying the main memory access request from CPU # 02010 and CPU # 12011
AA # 1 (C) 2033 and BAA # 12031 and B
The BAA entry indexing operation of AA # 0 (C) 2032 is executed independently.

The cache memory 2040 is connected to the signal line 209
5 or the signal line 209b and the index result of each BAA entry sent via the signal line 2096 or the signal line 209a and the main memory address, and
When the AA entry exists, the cache memory 2040 is accessed using the cache memory address extracted from the entry. When the corresponding BAA entry does not exist, the cache memory 2040 is not accessed. Send an access request to the MS.

The cache storage 2040 further stores the corresponding BA
If the A entry exists, and if the main memory access request from the CPU is a read request, the data is read and discriminated and sent to the requesting CPU via signal lines 2098 and 2099, and the request is written. If so, the write data sent via the signal lines 2098 and 2099 is written to the cache storage 2040. If the corresponding BAA entry does not exist,
Perform normal main memory access.

In this mode, the two CPUs have separate BAA
In this method, two CPUs are used.
Are operating while occupying the BAA,
Even if the main memory access request signals from both CPUs are sent at the same time, the index operation of the BAA entry corresponding to the main memory access request of one of the CPUs does not wait, and the efficient BAA entry of the BAA entry is not waited. The same BAA is shared by two CPUs by realizing the indexing operation and referring to the partner's BAA without being affected by the access of the CPU connected to the partner's BAA. Next, a method of connecting the CPU, the BAA, and the cache memory, which is one of the features of the fifth embodiment, will be described.

Next, a description will be given of a layout method of the CPU, the BAA, and the cache storage, which is a feature of the semiconductor integrated circuit of the information processing apparatus according to the fifth embodiment.

First, an example of a layout method in a semiconductor integrated circuit according to the fifth embodiment of the present invention will be described with reference to FIG.

FIG. 21 is a schematic layout diagram of a semiconductor integrated circuit as one example according to the fifth embodiment of the present invention. In the fifth embodiment, as shown in FIG.
010 and CPU # 12011 from both BA
Since the A entry exemplifies a dedicated BAA used exclusively, the BAA # is located at the center of the chip as shown in FIG.
02030, BAA # 12031, BAA # 0 (C) 2
032 and the memory cell area of BAA # 1 (C) 2033, and the logic circuit areas of CPU # 02010 and CPU # 12011
BAA # 12031, BAA # 0 (C) 2032 and B
AA # 1 (C) 2033 is arranged adjacent to the memory cell area. Then, as shown in FIG. 21, the memory cell area of the cache memory 2040 stores BAA # 02030,
AA # 12031, BAA # 0 (C) 2032 and BA
A # 1 (C) adjacent to the memory cell area of 2033 and C
It is arranged on the opposite side of the logic circuit area of PU # 02010 and CPU # 12011.

Logic Circuit Area of CPU # 02010 and BA
A # 02030 memory cell area is arranged adjacent to
Logic circuit area of CPU # 12011 and BAA # 1203
By arranging one memory cell area adjacent to one memory cell area,
By arranging each CPU and the BAA used in a combination of exclusive use and common use for the CPU adjacent to each other, C
The width of the data path between the PU and the BAA can be widened and this path length can be shortened. Furthermore, BAA
# 02030, BAA # 12031, BAA # 0 (C)
By arranging the memory cell areas of 2032 and BAA # 1 (C) 2033 adjacently, BAA # 0203
0, the contact surface between BAA # 12031, BAA # 0 (C) 2032 and BAA # 1 (C) 2033 can be increased,
As a result, the width of the data path between BAAs can be widened and the path length can be shortened. As a result, BAA # 02030, BAA # 12031, BAA
Data transfer between the memory cell areas of # 0 (C) 2032 and BAA # 1 (C) 2033 can be speeded up.

Similarly, the memory cell area of the cache storage 2040 is set to BAA # 02030, BAA # 12031,
BAA # 0 (C) 2032 and BAA # 1 (C) 203
3 adjacent to the memory cell area,
The contact area between the AA and the cache memory can be increased, and as a result, the width of the data path between the BAA and the cache memory can be increased and the path length can be shortened.

As described in the first embodiment of the present invention, increasing the width of the data path between the regions means
This means that the number of signal lines between the areas can be increased, and the data transfer amount per unit time can be increased. Further, the data transfer delay time between the areas can be reduced by shortening the path length between the areas.

In the arrangement shown in FIG.
A # 02030, BAA # 12031, BAA # 0
The area of the cache storage 2040 is cut into both ends or the center of (C) 2032 and BAA # 1 (C) 2033, and the area of the cache storage 2040 is changed to the CPU # 0201.
There is also a method of laying out the area adjacent to the area of CPU # 12011 and CPU # 12011.

Next, another example of a layout method in a semiconductor integrated circuit according to the fifth embodiment of the present invention will be described with reference to FIG.

FIG. 22 is a schematic layout diagram of a semiconductor integrated circuit as one example according to the fifth embodiment of the present invention. In the fifth embodiment, as shown in FIG.
010 and CPU # 12011 from both BA
Since the A entry exemplifies a dedicated BAA used exclusively, the BAA # is located at the center of the chip as shown in FIG.
02030, BAA # 12031, BAA # 0 (C) 2
032 and the memory cell area of BAA # 1 (C) 2033, and the logic circuit areas of CPU # 02010 and CPU # 12011
BAA # 12031, BAA # 0 (C) 2032 and B
AA # 1 (C) 2033 is arranged adjacent to the memory cell area. Then, as shown in FIG. 22, the memory cell area of the cache memory 2040 has BAA # 02030,
AA # 12031, BAA # 0 (C) 2032 and BA
A # 1 (C) adjacent to the memory cell area of 2033 and C
It is arranged on the opposite side of the logic circuit area of PU # 02010 and CPU # 12011.

Logic Circuit Area of CPU # 02010 and BA
The memory cell areas of A # 02030 and BAA # 1 (C) 2033 are arranged adjacent to each other, and the logic circuit area of CPU # 12011 and BAA # 12031 and BAA # 0 (C)
By arranging the 2032 memory cell areas adjacent to each other, by arranging each CPU and the BAA used in a combination of occupation and sharing for the CPU adjacent to each other, the width of the data path between the CPU and the BAA Can be widened and the path length can be shortened. Furthermore,
BAA # 02030 and BAA # 0 (C) 2032 and B
The memory cell areas of AA # 12031 and BAA # 1 (C) 2033 are arranged adjacent to each other, and additionally, BAA # 0 (C) 2
032 and BAA # 1 (C) 2033 are arranged adjacent to each other, so that BAA # 02030 and BAA # 0 (C) 2
032, BAA # 12031 and BAA # 1 (C) 20
The contact area between the 33 memory cell areas can be increased, and as a result, the width of the data path between BAAs having the same BAA entry can be increased and the path length can be shortened. As a result, BAA # 02030 and BAA #
0 (C) 2032 and BAA # 12031 and BAA # 1
(C) The data transfer operation relating to the memory cell area of 2033 can be speeded up.

Similarly, the memory cell area of the cache storage 2040 is set to BAA # 02030, BAA # 12031,
BAA # 0 (C) 2032 and BAA # 1 (C) 203
3 adjacent to the memory cell area,
The contact area between the AA and the cache memory can be increased, and as a result, the width of the data path between the BAA and the cache memory can be increased and the path length can be shortened.

Next, another example of the layout method in the semiconductor integrated circuit according to the fifth embodiment of the present invention will be described with reference to FIG.

In the fifth embodiment, as described above, the CPU
Since both # 02010 and CPU # 12011 exemplify a dedicated BAA whose respective BAA entry is used exclusively, as shown in FIG.
AA # 02030 and BAA # 0 (C) 2032, and B
The memory cell areas of AA # 12031 and BAA # 1 (C) 2033 are arranged adjacent to each other, and BAA # 02030, BAA # 02030
A # 12031, BAA # 0 (C) 2032 and BAA
The CPU # on both sides of the memory cell area of # 1 (C) 2033
02010 and the logic circuit area of CPU # 12011 are arranged adjacent to each other, and BAA # 02030, BAA # 1
2031, BAA # 0 (C) 2032 and BAA # 1
(C) The cache memory 2040 divided into two is arranged adjacent to both sides of the memory cell area of 2033.

As shown in FIG.
40 by bisecting and adjoining, and enabling each of the bisected caches to operate independently,
The width of the data path between the BAA and the cache memory can be made wider and the simultaneous access operation to the two cache memories becomes possible.
Efficient processing of a main memory access request from U # 12011 can be performed. Also, the cache memory is divided into two
By arranging symmetrically from AA, it is possible to obtain an effect that variation in the data transfer delay time due to the arrangement position between the respective regions can be suppressed.

Next, another example of a layout method in a semiconductor integrated circuit according to the fifth embodiment of the present invention will be described with reference to FIG.

In the fifth embodiment, as described above, the CPU
Since a dedicated BAA used exclusively by each of the BAA entries from both # 02010 and # 12011 is illustrated, a logic circuit of CPU # 02010 and CPU # 12011 is provided at the center of the chip as shown in FIG. Regions are arranged adjacent to each other, and CPU # 02010 and C #
BAA # 02 on both sides of the logic circuit area of PU # 12011
030 and BAA # 0 (C) 2032 and BAA # 1
A pair of memory cell areas 2031 and BAA # 1 (C) 2033 are arranged adjacent to each other, and further, a cache memory 2040 divided into two is arranged adjacent to both sides of the logic circuit area of CPU # 02010 and CPU # 12011.

As shown in FIG.
40 by bisecting and adjoining, and enabling each of the bisected caches to operate independently,
The width of the data path between the BAA and the cache memory can be made wider and the simultaneous access operation to the two cache memories becomes possible.
Efficient processing of a main memory access request from U # 12011 can be performed. Also, the cache memory is divided into two
By arranging symmetrically from AA, it is possible to obtain an effect that variation in the data transfer delay time due to the arrangement position between the respective regions can be suppressed.

As described above, the invention made by the inventor has been specifically described based on the first to fifth embodiments of the present invention. However, the present invention is not limited to the above-described embodiment.
It goes without saying that various changes can be made without departing from the gist of the invention. For example, in the above embodiment, C
In PU, BAA and the physical element form in realizing cache storage, in the CPU, processing and scientific processing by electromagnetic waves or magnetism or electrons or combinations of electromagnetic waves or magnetism or electrons are used as electronic circuits for controlling and controlling. In the BAA and cache memory, the electromagnetic wave or magnetism or the magnetic memory or the memory element using the connection of the electronic circuit or the memory element using the connection of the electronic circuit is used in the BAA and the cache memory. What is necessary is just to mount in a semiconductor chip by the processing by the combination of the scientific processing and the processing by each combination of an electron, an electromagnetic wave, magnetism, or an electron.

In the above embodiment, the logic circuit area of the CPU, the BAA, and the memory cell area of the cache memory are arranged so as to be joined to each other, and are mounted in one chip, thereby closing the inside of the chip. The drive circuit for driving the input / output terminals for the signal lines with respect to the signal lines can be eliminated. As a result, the signal transmission delay in the chip can be reduced. The limitation on the number of signal lines, which has been limited by the number, can be removed, and the power consumption of the information processing device can be reduced.

In the above description, the invention made mainly by the present inventor is applied to a data access technique in the case where a plurality of processors of an information processing apparatus, which is a technical field to which the present invention belongs, shares cache storage, and to the realization of this technique. So-called memory embedded multiprocessor system LSI
However, the present invention is not limited to this. For example, a general memory having an address reconfiguring function, a general processing device related to digital signal processing with cache storage, and a digital signal transmission device with cache storage It is widely applicable in general. Therefore, the information processing executed by the information processing apparatus is not limited to digital information processing by a computer, but is a process of converting an analog signal to a digital signal, or vice versa, or temporarily converting an analog signal to a digital signal. Needless to say, various embodiments such as a device for converting the digital information into an analog signal after processing the converted digital information can be adopted. When the configuration and means of the present invention are applied to an address translation buffer, the main points are as follows. That is, in a processing device including a processor, an address translation mechanism, and an address translation buffer, a plurality of processors have only one address translation buffer, and the only address translation buffer is accessed from the plurality of processors. A data access method for an information processing apparatus, wherein a corresponding entry belonging to all processors of a logical address and an absolute address is held and shared between data access requests from the plurality of processors.

Alternatively, a plurality of address translation buffers are provided in association with each of the plurality of processors, and each address translation buffer stores a logical address and an absolute address corresponding to an access from each of the plurality of processors. A data access method for an information processing apparatus, comprising: holding a corresponding entry; and processing data access requests from the plurality of processors in a processor-dependent manner.

Alternatively, a plurality of address translation buffers are provided in correspondence with each of the plurality of processors, and each of the address translation buffers stores all of the correspondence between the logical address and the absolute address accessed from the plurality of processors. A data access method for an information processing apparatus, comprising: holding an entry; and processing data access requests from the plurality of processors according to the processors.

Alternatively, a plurality of address translation buffers are provided in association with each of the plurality of processors, and each address translation buffer stores a logical address and an absolute address corresponding to an access from each of the plurality of processors. A corresponding entry is held, and data access requests from the plurality of processors are processed in accordance with the processor, and a corresponding entry of a logical address and an absolute address corresponding to a data access request from one processor is an address corresponding to the processor. If it does not exist in the translation buffer, a plurality of address translation buffers corresponding to other processors are provided, or a plurality of address translation buffers are respectively associated with the plurality of processors. Is the plurality An entry corresponding to a logical address and an absolute address corresponding to an access from each of the processors is held, and one of the plurality of sets of address translation buffers receives a data access request from a corresponding one of the plurality of processors. The plurality of sets of other address translation buffers that are processed can be applied to a data access method of an information processing apparatus, which processes a data access request from another processor among the plurality of processors.

[0170]

According to the invention disclosed in the present invention,
The effects obtained by typical ones will be summarized as follows. (1). As described above, by mounting the components including the storage element and the logic circuit on the same semiconductor chip, it is possible to eliminate input / output terminals for transmitting and receiving electric signals between the storage element chip and the logic circuit chip. I can do it. As a result, the data width of the electric signal between the storage element and the logic circuit can be greatly expanded, and the processing performance of the main memory access of the information processing device including a plurality of CPUs can be greatly improved.

(2). As described above, by mounting the components including the storage element and the logic circuit on the same semiconductor chip, the circuit for amplifying the electric signal passing between the storage element chip and the logic circuit chip and the circuit consumed by the circuit are amplified. Power and heat generation can be greatly reduced. as a result,
Power consumption and heat generation of the information processing apparatus including a plurality of CPUs can be significantly reduced.

(3). In a mode in which the same BAA is shared by a plurality of CPUs, a method of operating the BAA index operation in a half cycle time of a main memory access request signal transmission cycle transmitted from each CPU, or a method in which the BAA index operation is performed, respectively. The CPU operates in the same cycle time as the main memory access request signal transmission cycle transmitted from the CPU, but when the main memory access request signals from a plurality of CPUs are simultaneously transmitted, the BAA entry index corresponding to one of the CPUs is transmitted. In a method in which the operation waits for one cycle, it is possible to obtain an effect equivalent to the case where each of the plurality of CPUs operates while occupying the BAA.
BAA by sharing the same BAA from multiple CPUs
It is possible to improve the use efficiency of
The physical capacity of A can be reduced. (4). In a configuration in which the same BAA is shared by a plurality of CPUs and a configuration in which different BAAs are occupied by a plurality of CPUs, a plurality of CPUs and a single BAA and respective areas of cache storage are arranged adjacent to each other in a chip. Thus, the contact area between the respective areas is made larger by further increasing the contact area between the respective areas by means such as making the adjacent areas adjacent to each other with a refracted surface. Can be widened.
If the width of the data path between the regions in the chip is increased, the number of signal lines between the regions can be increased, and the data transfer amount per unit time of the data path can be increased.
Further, if the contact surface between the respective regions can be increased, the length of the data path arranged between the regions can be shortened, and the data transfer delay time between the respective regions can be reduced. (5). In a mode in which the same BAA is shared by a plurality of CPUs, the cache storage is divided and arranged adjacent to the BAA, and each of the divided cache storages can operate independently, so that the BAA and the cache storage can be operated independently. By making the contact area between the areas between the chips larger, the width of the data path between the areas in the chip can be made wider, and a plurality of access operations to the divided cache memory can be performed simultaneously. Become. As a result,
It is possible to improve the efficiency of main memory access request processing from the CPU. Further, by dividing the cache memory and arranging it symmetrically from the BAA, an effect is obtained in that the variation in the data transfer delay time due to the arrangement position between the areas can be suppressed.

(6). In a mode in which a plurality of CPUs occupy different BAAs, each of the plurality of CPUs
Since it operates while occupying A, even if a main memory access request signal from a plurality of CPUs is sent at the same time, B corresponding to the main memory access request of each CPU may be transmitted.
The indexing operation of the AA entry is executed without waiting, and the efficient indexing operation of the BAA entry can be realized. (7). In a mode in which separate BAAs are occupied by a plurality of CPUs, the memory cell areas of the plurality of BAAs are arranged symmetrically at the edge of the chip, and the logic circuit area of the CPU is adjacent to one side of the memory cell area of each BAA. In addition, by arranging the cache memory locations symmetrically from the plurality of BAAs, it is possible to suppress variations in the data transfer delay time due to the location between the respective areas. It becomes possible. Also, in this embodiment, the cache storage is divided and BAA
By arranging them in a symmetrical manner, it is possible to suppress variations in the data transfer delay time due to the arrangement positions between the respective regions. (8). There is provided a means for registering a BAA entry generated in response to a main memory access request from a plurality of CPUs with a plurality of BAAs, and in a mode in which the plurality of CPUs occupy the plurality of BAAs, each of the plurality of CPUs stores the BAA. Since it operates while being occupied, even if a main memory access request signal from a plurality of CPUs is sent at the same time, the BA corresponding to the main memory access request of each CPU may occur.
The indexing operation of the A entry is executed without waiting,
Further, an effect equivalent to the case where the same BAA is completely shared by a plurality of CPUs can be obtained, and an efficient BAA entry indexing operation can be realized. (9). A means for registering a BAA entry generated in response to a main memory access request from a plurality of CPUs with a plurality of BAAs is provided. In a mode in which a plurality of CPUs occupy the plurality of BAAs, a memory cell area of a plurality of BAAs is allocated. By arranging adjacently, the contact surface between BAA can be enlarged, and as a result, the width of the data path between BAA can be widened and this path length can be shortened. As a result, the same B for the memory cell areas of a plurality of BAAs
It is possible to speed up the AA entry registration operation. (10). In a form in which separate BAAs are accessed from a plurality of CPUs in a combination of exclusive use and shared use, a plurality of CPs are accessed.
Even if the main memory access request signal from U is sent at the same time, the index operation of the BAA entry corresponding to the main memory access request of one of the CPUs is not waited, and the efficient indexing of the BAA entry is not performed. The operation can be realized and the same BAA can be obtained by referring to the partner's BAA.
Since A is shared by two CPUs, it is possible to improve the use efficiency of BAA.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an embodiment of a data access method and a semiconductor integrated circuit of an information processing apparatus according to the present invention.

FIG. 2 is a diagram showing a configuration of a data access method and a semiconductor integrated circuit of the information processing apparatus according to the first embodiment of the present invention;

FIG. 3 is a schematic layout diagram showing a semiconductor integrated circuit of the information processing device according to the first embodiment of the present invention.

FIG. 4 is a schematic layout diagram showing a semiconductor integrated circuit according to a modification of the first embodiment of the present invention.

FIG. 5 is a schematic layout diagram showing a semiconductor integrated circuit according to another modification of the first embodiment of the present invention.

FIG. 6 is a schematic layout diagram showing a semiconductor integrated circuit according to still another modification of the first embodiment of the present invention.

FIG. 7 is a diagram illustrating a configuration of a data access method and a semiconductor integrated circuit of an information processing apparatus according to a second embodiment of the present invention;

FIG. 8 is a schematic layout diagram showing a semiconductor integrated circuit of an information processing device according to a second embodiment of the present invention.

FIG. 9 is a schematic layout diagram showing a semiconductor integrated circuit according to a modification of the second embodiment of the present invention.

FIG. 10 is a schematic layout diagram showing a semiconductor integrated circuit according to another modification of the second embodiment of the present invention.

FIG. 11 is a schematic layout diagram showing a semiconductor integrated circuit according to still another modification of the second embodiment of the present invention.

FIG. 12 is a schematic layout diagram showing a semiconductor integrated circuit according to still another modification of the second embodiment of the present invention.

FIG. 13 is a diagram illustrating a data access method of an information processing apparatus and a configuration of a semiconductor integrated circuit according to a third embodiment of the present invention;

FIG. 14 is a schematic layout diagram showing a semiconductor integrated circuit of an information processing device according to a third embodiment of the present invention.

FIG. 15 is a schematic layout diagram showing a semiconductor integrated circuit according to a modification of the third embodiment of the present invention.

FIG. 16 is a diagram illustrating a configuration of a data access method and a semiconductor integrated circuit of an information processing device according to a fourth embodiment of the present invention;

FIG. 17 is a schematic layout diagram showing a semiconductor integrated circuit of an information processing device according to a fourth embodiment of the present invention.

FIG. 18 is a schematic layout diagram showing a semiconductor integrated circuit according to a modification of the fourth embodiment of the present invention.

FIG. 19 is a schematic layout diagram showing a semiconductor integrated circuit according to still another modification of the fourth embodiment of the present invention.

FIG. 20 is a diagram illustrating a data access method of an information processing device and a configuration of a semiconductor integrated circuit according to a fifth embodiment of the present invention;

FIG. 21 is a schematic layout diagram showing a semiconductor integrated circuit of an information processing device according to a fifth embodiment of the present invention.

FIG. 22 is a schematic layout diagram showing a semiconductor integrated circuit according to a modification of the fifth embodiment of the present invention.

FIG. 23 is a schematic layout diagram showing a semiconductor integrated circuit according to still another modification of the fifth embodiment of the present invention.

FIG. 24 is a schematic layout diagram showing a semiconductor integrated circuit according to still another modification of the fifth embodiment of the present invention.

[Explanation of symbols]

 110, 111 Processor 120 Cache storage unit 130, 131 Block address array 140 Cache storage 150 Main storage

Claims (18)

[Claims] 1. A plurality of independently operable processors and a plurality of independently accessible memories are integrated on the same chip, and the plurality of memories temporarily store data to be accessed by the processors. The cache memory holds a plurality of entries corresponding to data addresses sent from the plurality of processors and cache memory addresses, and roughly stores the data sent from the processors. One or more block address arrays each including a block address storage unit that holds a block address and a cache address storage unit that holds a corresponding cache storage address, and a cache storage that holds a copy of main storage data; The memory stores the plurality of independently operable programs. A data access method for an information processing apparatus, wherein the data access method is connected and configured as a single cache storage device shared and accessed by a processor. 2. The information processing apparatus according to claim 1, wherein
Having a unique block address array for the plurality of processors, the unique block address array comprising:
Information characterized by having means for holding, for all processors, corresponding entries of data addresses and cache storage addresses accessed by the plurality of processors, and commonly using the data access requests from the plurality of processors. A data access method for the processing device. 3. The information processing apparatus according to claim 1, wherein
It has a plurality of block address arrays associated with each of the plurality of processors, and each block address array individually stores a corresponding entry of a data address and a cache storage address corresponding to an access from each of the plurality of processors. And processing the data access requests from the plurality of processors corresponding to the processors. 4. The information processing apparatus according to claim 1, wherein
A plurality of block address arrays are associated with each of the plurality of processors, and each of the block address arrays stores all corresponding entries of data addresses and cache storage addresses accessed from the plurality of processors. A data access method for an information processing apparatus, wherein the data access request is held by the plurality of processors and the data access requests from the plurality of processors are processed corresponding to the processors. 5. The information processing apparatus according to claim 1, wherein
A plurality of block address arrays are associated with each of the plurality of processors, and each block address array stores a corresponding entry of a data address and a cache storage address corresponding to each access from the plurality of processors. The processor holds the data access request from the plurality of processors corresponding to the processor, and a corresponding entry of the data address and the cache storage address corresponding to the data access request from the processor exists in the block address array corresponding to the processor. If not, a data access method for an information processing apparatus, wherein a block address array corresponding to another processor is accessed. 6. The information processing apparatus according to claim 1, wherein:
A plurality of sets of a plurality of block address arrays associated with each of the plurality of processors are provided, and each of the plurality of sets of the block address arrays stores a data address and a cache storage address corresponding to each of accesses from the plurality of processors. One of the plurality of sets of block address arrays holds all corresponding entries and processes a data access request from a corresponding one of the plurality of processors. The data access method of an information processing apparatus, wherein the array processes a data access request from another processor among the plurality of processors. 7. The information processing apparatus according to claim 2, wherein:
In a semiconductor integrated circuit in which a processor, a block address array, and a cache memory constituting the information processing device are integrated in the same chip, a memory cell area of the block address array is arranged in a central portion of the chip, and a logic circuit area of the processor is A plurality of processors are arranged adjacent to the memory cell area of the block address array, and the memory cell area of the cache memory is arranged adjacent to the memory cell area of the block address array and opposite to the logic circuit area of the processor. A semiconductor integrated circuit for an information processing apparatus. 8. The information processing apparatus according to claim 2, wherein
In a semiconductor integrated circuit in which a processor, a block address array, and a cache memory constituting the information processing apparatus are integrated in the same chip, a memory cell area of the block address array is arranged in a central portion of the chip, and a logic circuit area of a plurality of processors is provided. Are arranged so as to be adjacent to the memory cell area of the block address array and to surround the memory cell area of the block address array, and the memory cell area of the cache memory is adjacent to the memory cell area of the block address array and of the block address array. A semiconductor integrated circuit for an information processing device, wherein the semiconductor integrated circuit is arranged so as to surround a memory cell area, is adjacent to a logic circuit area of a processor, and is arranged on a side opposite to the logic circuit area of the processor. 9. The information processing apparatus according to claim 2, wherein
In a semiconductor integrated circuit in which a processor, a block address array, and a cache memory constituting the information processing apparatus are integrated in the same chip, a memory cell area of the block address array bisects a memory cell area of the cache memory at a central portion of the chip. The logic circuit areas of the plurality of processors are arranged to be adjacent to the memory cell area of the block address array, and the memory cell area of the cache memory is arranged to be adjacent to both sides of the memory cell area of the block address array. A semiconductor integrated circuit of an information processing device, characterized in that: 10. The information processing apparatus according to claim 2, wherein the processor, the block address array, and the cache memory constituting the information processing apparatus are integrated in the same chip. The memory cell area of the address array is arranged, the logic circuit area of the processor is arranged adjacent to both sides of the memory cell area of the block address array, and the memory cell area of cache storage is divided on both sides of the memory cell area of the block address array. A semiconductor integrated circuit for an information processing apparatus, wherein the semiconductor integrated circuit is arranged so as to be adjacent to the information processing apparatus. 11. The information processing apparatus according to claim 3, wherein the processor, the block address array, and the cache memory constituting the information processing apparatus are integrated in the same chip. The memory cell area of the block address array is arranged at the center, the logic circuit area of the processor is arranged so that each processor is adjacent to the memory cell area of the corresponding block address array, and the memory cell area of the cache memory is A semiconductor integrated circuit for an information processing device, wherein the semiconductor integrated circuit is arranged so as to be adjacent to a memory cell region of an address array and on a side opposite to a logic circuit region of a processor. 12. The semiconductor integrated circuit according to claim 3, wherein a processor, a block address array, and a cache memory constituting the information processing device are integrated in the same chip. The memory cell area of the block address array is arranged, the logic circuit area of each processor is arranged adjacent to one side of the memory cell area of the block address array, and the memory cell area of the cache memory is located at both ends of the chip. A semiconductor integrated circuit for an information processing device, wherein the semiconductor integrated circuit is arranged adjacent to between the memory cell regions of the arranged block address array and adjacent to the logic circuit region of each processor. 13. The information processing apparatus according to claim 3, wherein the processor, the block address array, and the cache memory constituting the information processing apparatus are integrated in the same chip. A memory cell area for storage is arranged, memory cell areas on both sides of the memory cell area for cache memory are arranged adjacently, and a logic circuit area of the processor is arranged adjacent to the outside of the memory cell area of the block address array. A semiconductor integrated circuit for an information processing device, comprising: 14. The information processing apparatus according to claim 3, wherein the processor, the block address array, and the cache memory constituting the information processing apparatus are integrated in the same chip. The memory cell area of the block address array is arranged adjacent to the center, the logic circuit area of the processor is arranged adjacent to both sides of the memory cell area of the block address array, and the cache is arranged on both sides of the memory cell area of the block address array. A semiconductor integrated circuit for an information processing device, wherein storage memory cell regions are arranged adjacently and divided. 15. The information processing device according to claim 3, wherein the processor, the block address array, and the cache memory constituting the information processing device are integrated in the same chip. Are arranged adjacent to each other, the memory cell areas of the block address array are arranged adjacent to both sides of the logic circuit area of the processor, and the memory cell areas of cache memory are arranged adjacent to both sides of the logic circuit area of the processor. A semiconductor integrated circuit for an information processing device, wherein the semiconductor integrated circuit is arranged separately. 16. The information processing device according to claim 6, wherein the processor, the block address array, and the cache memory constituting the information processing device are integrated in the same chip. The memory cell area of the address array is arranged, the logic circuit area of each processor is arranged adjacent to the memory cell area of the corresponding block address array, and the memory cell area of the cache memory is arranged in the corresponding block address array. A semiconductor integrated circuit for an information processing device, wherein the semiconductor integrated circuit is arranged adjacent to the memory cell region of the above and on the opposite side of the logic circuit region of the corresponding processor. 17. The information processing apparatus according to claim 6, wherein the processor, the block address array, and the cache memory constituting the information processing apparatus are integrated in the same chip. The memory cell areas of the address array are arranged adjacent to each other, and the logic circuit areas of the corresponding processors are arranged adjacent to both sides of the memory cell area of each block address array, and the memory of the block address array corresponding to each of the processors is arranged. A semiconductor integrated circuit for an information processing device, wherein a memory cell region for cache storage is divided and arranged adjacent to both sides of a cell region. 18. The information processing apparatus according to claim 6, wherein the processor, the block address array, and the cache memory constituting the information processing apparatus are integrated in the same chip. Are arranged adjacent to each other, and a pair of memory cell areas of a block address array corresponding to both sides of the logic circuit area of the processor are arranged adjacent to each other, and a logic circuit area of the processor corresponding to each of the block address arrays is arranged. A memory cell region for cache storage is divided and arranged adjacent to each other on both sides of the semiconductor integrated circuit.