JPH1116367A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory device in which the leakage defect of a bit line can be avoided with a simple circuit construction without lowering the voltage of the bit line. SOLUTION: A semiconductor memory device has bit lines and word lines which are laid vertically and horizontally, readable and writable memory cells 1, precharge MOS transistors Q1 and Q2, short-circuit MOS transistors Q3 and level setting MOS transistors Q4 and Q5. Two bit lines are provided for each bit. Three fuses F1-F3 for respective columns are connected between the precharge MOS transistors Q1 and Q2 and a bit line driving power supply terminal Vcc on their upstream side. If a leakage defect is produced in a bit line, all the fuses F1-F3 connected to that bit line are cut off. As a plurality of fuses are connected in parallel, a voltage drop between both the terminals of the fuses can be suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a static RA
The present invention relates to a circuit configuration of an M (SRAM), and more particularly to a technique for suppressing generation of a leak current inside an SRAM.

[0002]

2. Description of the Related Art A static RAM (hereinafter, referred to as an SRAM) is widely used as a cache memory of a CPU because it has no refresh operation and can be accessed at a high speed as compared with a dynamic RAM (DRAM).

FIG. 4 is a circuit diagram showing an internal configuration of a conventional MOS SRAM, and shows a circuit configuration for one column. The SRAM shown in FIG. 4 has bit lines B arranged vertically and horizontally.
L, / BL and word line W, readable and writable memory cell 1, precharge MOS transistors Q1, Q2, short-circuit MOS transistor Q3, and level setting of bit line pair BL, / BL MO for
S transistors Q4 and Q5 are provided.

The transistors Q1 and Q2 control the bit line pair to a high level immediately before reading or writing to the memory cell.
Controls the bit line pairs to have the same potential.

The SRAM shown in FIG. 4 is provided with two bit lines BL and / BL for each bit. When reading and writing to and from the memory cell 1, the logic of these two bit lines is used. Are opposite to each other.

[0006]

When the SRAM shown in FIG. 4 is formed on a semiconductor substrate, the bit lines BL, / B
L is often formed using an Al layer having a low resistance.
However, with the advance of microfabrication technology, the memory capacity of the SRAM tends to gradually increase, and at the same time, the wiring width and the wiring interval are shortened, and defects such as leak current are likely to occur.

In particular, as the degree of integration increases, the bit lines BL, BL
/ BL, word lines W, etc. must be arranged closely, and as shown in FIG. 4, the number of cases in which the ground line VSS must be arranged near the bit lines BL, / BL increases.

However, when the bit lines BL and / BL and the ground line VSS are arranged adjacent to each other, there is a possibility that both are short-circuited.
When a short circuit occurs, the bit line drive power supply terminal VCC connects to the bit line B
A leakage current flows to the ground line VSS via L and / BL.

[0009] As shown in FIG. 5, the bit line BL is connected to the drain terminal 1 of the transfer gate in the memory cell 1.
1 is connected through a contact hole 12,
When the bit line width becomes narrower, the bit line BL and the ground line VSS come into contact with each other, and the bit line BL comes into contact with the ground line VSS through the contact hole 12 from the power supply terminal VCC through the contact hole 12 only by slightly shifting the hole position of the contact hole 12 as shown in the figure. A leak current flows, which causes a spec-out of a current during a static operation (hereinafter, referred to as a standby failure).

Some SRAMs include a redundancy circuit for repairing a defective memory cell, in which a defective memory cell in which reading / writing cannot be performed normally (hereinafter, referred to as a function failure) is replaced with another memory cell. However, even if the memory cell is replaced by the redundant circuit, the leak current does not disappear. Therefore, the function failure can be remedied but the standby failure cannot be relieved only by performing the redundant replacement of the memory cell in which the leak has occurred.

As a method of suppressing such a leak current of a bit line, there has been proposed an SRAM in which a switch is provided in a power supply line to cut off a path in which the leak current has occurred. FIG. 6 is a block diagram showing the internal configuration of this type of SRAM (Japanese Patent Laid-Open No. 5-314790). The SRAM shown in FIG. 6 has a PMO between a memory cell 21 and a power supply terminal.
The memory cell is characterized by providing an S transistor 22 and a fuse 23, and the memory cell is configured by a circuit as shown in FIG. 7A or 7B. In the circuit shown in FIG. 6, a fuse 23 is connected between the drain terminals of the MOS transistors 24 and 25 constituting the memory cell 21 and the power supply VCC. The current does not disappear. Note that FIG.
FIG. 7B shows an example in which a memory cell is formed by two MOS transistors, and FIG. 7B shows an example in which a memory cell is formed by two MOS transistors and two high-resistance resistive elements, as shown in FIG. With this configuration, the cell area can be reduced.

On the other hand, Japanese Unexamined Patent Publication No. 8-138399 shown in FIG. 8 discloses a circuit in which a power supply line is cut off by a MOS transistor when a leak failure occurs. This publication also discloses an example in which a fuse is provided in a power supply control fuse circuit that controls a gate terminal voltage of a MOS transistor. However, since the fuse is not directly cut off by cutting the fuse, the circuit is not disclosed. May be complicated, and the element formation area and power consumption may increase.

Although a fuse having a simpler structure than the MOS transistor may be provided instead of the MOS transistor shown in FIG. 8, the fuse is generally formed using polysilicon as a material. Has a higher resistance value than the bit line formed by. Therefore, if a fuse is connected between the power supply terminal VCC and the bit line, a voltage drop occurs at both ends of the fuse, and the voltage level supplied to the bit line is reduced. To compensate for this voltage drop, it is conceivable to increase the voltage applied to the power supply terminal VCC. However, in this case, low-voltage driving cannot be performed and power consumption increases.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device capable of eliminating bit line leakage defects with a simple circuit configuration without lowering the bit line voltage. It is to provide a storage device.

[0015]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the invention according to claim 1 is capable of storing data corresponding to the logic of a bit line and a word line and a bit line. A semiconductor memory device comprising: a plurality of memory cells capable of transmitting data to a bit line; and a precharge transistor connected to each bit line in series and supplying a charging current to each bit line. A bit line drive power supply terminal for supplying a voltage to each bit line is provided on the upstream side of the precharge transistor. A plurality of fuses are connected in parallel between the bit line drive power supply terminal and the precharge transistor. It was done.

According to a second aspect of the present invention, there are provided a plurality of bit lines and word lines, and a plurality of memory cells capable of storing data according to the logic of the bit lines and transmitting the stored data to the bit lines. , A precharge transistor connected to each bit line in series and adjusting the voltage amplitude of each bit line. A bit line driving power supply terminal for supplying a voltage to the plurality of pre-charging transistors, and a plurality of the pre-charging transistors as a set. The fuses are connected in parallel.

According to a third aspect of the present invention, in the semiconductor memory device according to the second aspect, a pair of bit lines is provided for each bit, and the same number of memory cells as word lines are provided between the pair of bit lines. Are connected, and the plurality of fuses are connected in parallel for each bit line pair for a plurality of bits.

According to a fourth aspect of the present invention, in the semiconductor memory device according to the third aspect, the plurality of fuses are connected in parallel for each column address including a plurality of bits.

According to a fifth aspect of the present invention, in the semiconductor memory device according to any one of the first to fourth aspects, the memory cell is a static RAM (SRAM) cell, and a ground line is arranged adjacent to the bit line. It was done.

According to a sixth aspect of the present invention, in the semiconductor memory device according to any one of the first to fifth aspects, there is provided a redundant circuit for replacing the defective memory cell which cannot be read or written normally. When replacing the defective memory cell, the fuse corresponding to a bit line connected to the defective memory cell can be cut.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor memory device to which the present invention is applied will be specifically described with reference to the drawings. In the embodiment described below, a leak current is not generated in a bit line in an SRAM.

FIG. 1 is a circuit diagram showing an internal configuration of a part of the SRAM according to the present invention, and FIG. 2 is a schematic layout diagram of the SRAM. In FIG. I have.

In FIG. 2, each area divided by a dashed line corresponds to an address area for one column (for example, 8 bits), and a plurality of (for example, 3 bits) correspond to each column address.
Pieces) of fuses. FIG. 1 is a circuit diagram showing a detailed configuration of one column in FIG.

As shown in FIG. 1, the SRAM of this embodiment
Are bit lines B0 to Bn, / B0 to /
Bn and word lines W0 to Wn, a readable and writable memory cell 1, and a precharge MOS
Transistors Q1, Q2, short-circuit MOS transistor Q3, and level setting MOS transistors Q4, Q
5 is provided. The memory cell 1 includes MOS transistors Q6 and Q7 forming a cross latch circuit and MOS transistors Q8 and Q8 connected to a gate line and a word line.
Q9 and high resistance elements R1 and R2 connected to the respective gate terminals of the MOS transistors Q6 and Q7.

MOS transistor Q for precharge
, Q2 and the bit line drive power supply terminal VCC on the upstream side thereof, three fuses F1 and F
2 and F3 are connected in parallel. These fuses F1 to
F3 is formed on a semiconductor substrate using polysilicon as a material.

Next, the operation of the semiconductor memory device shown in FIGS. When writing to the memory cell 1, data to be written is stored in each of the bit lines B0 to Bn, / B.
0 // Bn. Two of these bit lines are provided for each bit, and the logic of these two bit lines is set to reverse polarity when data is written. In this state, when the corresponding word line goes high, the MOS transistors Q8 and Q9 in the memory cell 1 turn on,
The voltage of the bit line is supplied to the gate terminals of MOS transistors Q6, Q7, and these MOS transistors Q6, Q7
7 latches the voltage corresponding to logic "1" or "0".

On the other hand, when reading from the memory cell 1, the corresponding word line goes high, and
Bit lines B0 to Bn and / B0 to / Bn are connected to transistors Q
1 and Q2, and these bit lines are maintained at the same potential by a transistor Q3.
3 is turned off, and the precharge and short circuit to the bit lines B0 to Bn and / B0 to / Bn are stopped.

At this time, since the voltage corresponding to the logic "1" or "0" is latched at the gate terminals of the MOS transistors Q6 and Q7 in the memory cell 1, any one of the paired bit lines is latched. One is the MOS in the memory cell 1
Discharged by the transistor Q6 or Q7 to a low level, and the other remains at a high level.

The voltages of the bit lines B0 to Bn and / B0 to / Bn are determined by the voltage level of the bit line driving power supply terminal VCC and the voltage level of the ground line VSS. MOS transistors Q1, Q2
When fuses F1 to F3 are connected between
Bit lines B0 to Bn, / B by the voltage drop of 1 to F3.
The voltage of 0 to / Bn becomes low.

However, in the present embodiment, the plurality of fuses F1 to F3 are connected in parallel, so that the resistance value can be made smaller than when one fuse is connected, and the voltage drop at both ends of the fuse can be made sufficiently small.

Next, a description will be given of a case where a defect occurs in which the bit line is short-circuited to the ground line VSS. In this case, a leak current flows from the bit line drive power supply terminal VCC to the ground line VSS through the precharge MOS transistor and the bit line. When this leak current is detected by a memory tester or the like, all the corresponding fuses are cut for each bit. As a result, the bit line path where the leak current has occurred is electrically cut off, and no leak current flows.

As described above, in the semiconductor memory device of the present embodiment, the bit line drive power supply terminal VCC and the precharge MOS transistor Q are provided for each bit constituting the SRAM.
1 and Q2, a plurality of fuses F1 to F3 are connected,
When a leak current is generated in the bit lines B0 to Bn and / B0 to / Bn, the fuses F1 to F3 are cut off, so that the generation of the leak current can be reliably prevented. Further, since the plurality of fuses F1 to F3 are connected in parallel, the voltage drop at both ends of the fuses can be reduced, and the voltage supplied to the bit lines does not decrease.

Although omitted in FIGS. 1 and 2, the SR
As a part of the configuration of the AM, a redundant circuit for a function failure that cannot perform normal reading and writing may be provided. Further, when replacing the memory cell in which the function failure has occurred with another memory cell, the fuses F1 to F3 of the bit lines corresponding to the memory cell in which the function failure has occurred may be forcibly cut. Thus, when performing the function defect relief, it is possible to simultaneously perform the leak defect relief.

FIG. 1 shows an example in which three fuses F1 to F3 are provided for each bit, but the number of fuses is two.
The number is not particularly limited to three as long as the number is three or more.

Instead of providing a plurality of fuses for each bit, a plurality of fuses may be provided for each of bit lines B0 to Bn and / B0 to / Bn. FIG. 3 shows bit line B
0 to Bn and / B0 to / Bn, three fuses F1 to F3 are connected between the precharge MOS transistors Q1 and Q2 and the bit line drive power supply terminal VCC, respectively.
Are connected.

[0036]

As described above in detail, according to the present invention, a plurality of fuses are provided between a precharge transistor for adjusting the voltage amplitude of a bit line and a bit line drive power supply terminal on the upstream side. Are connected in parallel, and if a leak current failure occurs in the bit line, all the corresponding fuses are cut off, so that no leak current occurs. Voltage drop can be reduced.

In particular, if such fuses are provided in units of columns (for example, 8 bits), even if the number of bits increases or the memory capacity increases, the number of fuses does not need to increase so much. The formation area can be reduced.

If both the function failure and the standby failure are present, the memory cell having the function failure is replaced with a redundant cell, and the fuse of the defective memory cell is forcibly blown. Leak defects can be relieved at the same time.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an internal configuration of a part of an SRAM according to the present invention.

FIG. 2 is a schematic layout diagram of an SRAM.

FIG. 3 is a circuit diagram of an SRAM showing an example in which a plurality of fuses are provided for each bit line.

FIG. 4 is a circuit diagram showing the internal configuration of a conventional MOS SRAM.

FIG. 5 is a diagram illustrating a defect in a contact hole.

FIG. 6 is a block diagram of an SRAM disclosed in Japanese Patent Application Laid-Open No. 5-314790.

FIG. 7 is a circuit diagram showing an internal configuration of a memory cell in the SRAM of FIG. 6;

FIG. 8 is a block diagram of an SRAM disclosed in Japanese Patent Application Laid-Open No. 8-138399.

[Explanation of symbols]

 1 Memory cell B0-Bn, / B0 // Bn Bit line W0-Wn Word line VSS Ground line VCC Bit line drive power supply terminal F1-F3 Fuse Q1-Q9 MOS transistor

Claims (6)

[Claims] A plurality of memory cells capable of storing data corresponding to a bit line and a word line, a logic of the bit line, and transmitting the stored data to the bit line; A precharging transistor connected to the bit line and supplying a charging current to each bit line;
A bit line drive power supply terminal for supplying a voltage to each bit line is provided on the upstream side of the precharge transistor, and the bit line drive power supply terminal and the precharge transistor are connected to each other. A semiconductor memory device in which a plurality of fuses are connected in parallel. A plurality of bit lines and word lines, a plurality of memory cells capable of storing data corresponding to the logic of the bit lines, and capable of transmitting the stored data to the bit lines; A precharge transistor connected in series and adjusting the voltage amplitude of each bit line, a semiconductor memory device comprising: a plurality of precharge transistors;
A bit line driving power supply terminal for supplying a voltage to each bit line is provided.
A semiconductor memory device, wherein a plurality of fuses are connected in parallel between the precharge transistor and the bit line drive power supply terminal of each set. 3. A pair of bit lines are provided for each bit, and the same number of memory cells as word lines are connected between the pair of bit lines. 3. The semiconductor memory device according to claim 2, wherein said fuses are connected in parallel. 4. The semiconductor memory device according to claim 3, wherein said plurality of fuses are connected in parallel for each column address comprising a plurality of bits. 5. The method according to claim 1, wherein said memory cell is a static RAM.
5. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is an (SRAM) cell, and a ground line is arranged adjacent to the bit line. 6. A redundant circuit which replaces a defective memory cell which cannot be read or written normally, and which corresponds to a bit line connected to the defective memory cell when the defective memory cell is replaced by the redundant circuit. 6. The semiconductor memory device according to claim 1, wherein the fuse is cut off.