JPH11163523A - Formation of multilayer interconnection structure provided with a landless via hole and gaseous dielectric - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for forming multilayer interconnection structure, which has a landless via hole for interlayer connection and uses air as dielectric between the wirings. SOLUTION: A carbon layer is deposited on the surface of an insulator and a groove corresponding to a wiring pattern is formed on the surface of the carbon layer. A metal is supplied into the groove and onto the surface of the carbon layer, and a first layer wiring 66 is obtained by the subsequent chemical mechanical polishing process. Carbon ashing or etch back process is performed on the carbon layer, and the surface of the carbon layer is made lower than the wiring plane. An oxide capping layer 70 is formed on the wiring plane and on the surface of the recessed carbon layer. The carbon layer is consumed and removed by the oxidation process through the capping layer 70, and an air gap 74 is formed. Then, a silicon nitride etching stop layer 72 is formed on the surface of the capping layer 70, and a dielectric layer 76 is formed on the capping layer 70. After filing a via hole with a metal plug 78, a second layer wiring 80 is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the formation of an integrated circuit device including a multi-layer junction structure.

[0002]

2. Description of the Related Art Modern integrated circuits are field-effect transistors (FETs) formed on or in a semiconductor substrate.
Alternatively, it includes a device such as a bipolar device and a multilayer connection structure formed in contact with the device. The multi-layer connection structure provides a connection between different types of devices formed on a substrate, and is important in a novel design of an integrated circuit. In many integrated circuits, the multi-layer interconnect structure includes one or more interconnect arrays extending in parallel, providing connections between the devices in a densely packed array of devices. Arrays of such devices are typical of integrated circuit memories and other novel circuit designs.

[0003] Closely spaced, parallel traces provide undesirable levels of capacitive and inductive coupling between adjacent traces. In particular, it has an effect on the high data transmission speed through the parallel wiring array. That is,
Such capacitive and inductive couplings reduce data transmission rates and increase energy consumption and reduce integrated circuit characteristics. In some novel circuit designs, their transmission speed delay and energy consumption, which are related to the interconnect structure of the circuit, become a significant problem in circuit characteristics.

[0004] The complexity of modern interlayer connection structures has become a costly factor in integrated circuit design. Various factors can further increase the proportionate cost of interconnect structures in integrated circuits. For example, proposals have been made to substitute different interlayer dielectric materials and dielectric materials between metal conductors for a multilayer connection structure in order to improve the above-mentioned coupling problem. Capacitive and inductive coupling between adjacent wires is suppressed by the dielectric material that separates the wires.

[0005] Chemical vapor deposition (CV) from TEOS source gas
Dielectric materials such as silicon oxide deposited according to D) have a relatively high dielectric constant. It has been proposed to replace this dielectric material with a dielectric material having a low dielectric constant. The characteristics are improved by replacing the material having a high dielectric constant with a material having a low dielectric constant. Theoretically, the lowest dielectric constant is obtained with a gas or vacuum dielectric. These dielectric materials suffer from increased costs and process difficulties, and have not been used satisfactorily to this day.

One promising attempt at multi-layer interconnect structures using air dielectrics is described in Anand et al., "A Feasible Gas Dielectric Interlayer Connection Process" (1996 Symposium on VLSI Technology, Technical Paper Digest 82-83). )
It is described in. The interlayer connection structure and the method of making the structure are shown in FIGS. A schematic diagram of the wiring structure is depicted in FIG. In FIG. 1, various devices (not shown) are formed on the surface, and an interlayer dielectric 12 is formed.
A substrate 10 covered by a circle is shown. The first layer wirings 20 and 22 extend along the surface of the interlayer dielectric 12 and are separated by an air gap 32. Compared with common dielectric materials, the use of an air gap guarantees a minimum level of coupling between adjacent first-level interconnects (20, 22).

The air gap of the first layer is defined at its bottom by an interlayer dielectric 12 and at its top by a thin layer of silicon oxide 30. First
An interlayer connecting portion 36 extending vertically from the layer wiring to the second layer wiring 46 is formed. First layer wiring 22 and second layer wiring 4
6 are vertically separated by a via-hole layer air gap 42 surrounding the vertical interlayer connection 36. The air gap 42 is bounded at its upper and lower ends by thin layers 30 and 40 of silicon oxide, respectively. These via hole layer air gaps 42 are formed on the first layer wiring (20, 2) as compared with a general solid dielectric material.
The capacitive and inductive coupling between 2) and the second layer wiring 46 is reduced. With a similar configuration, the second layer air gap 52, whose boundaries are defined at the upper and lower ends by thin layers 50, 40 of silicon oxide, respectively, is
It is provided between the layer wirings 46 to reduce the level of capacitive and inductive coupling between the second layer wirings.

What is depicted in FIG. 1 is important in that it addresses some of the signal delay and energy consumption issues associated with interconnect structures used in high density integrated circuit designs. Also important is the method used to fabricate the structure shown in FIG.
It is shown below based on That is, as shown in FIG.
Devices are formed in and within the substrate 10 in the desired arrangement, after which the substrate is covered by the interlayer dielectric 12. Via holes are formed through the interlayer dielectric 12 to provide connections to devices (not shown) formed in the substrate. The first layer wiring will be formed to fill the via hole or to make contact with the interlayer connection. The first layer wiring is a modified etching process
(a Modified Damascene Process).

First, a layer of carbon is deposited on the surface of the interlayer dielectric, and then a photoresist mask (not shown) is provided on the surface of the carbon layer 14 using conventional photolithographic techniques. Next, the surface of the carbon layer is exposed in a pattern corresponding to the arrangement of the first layer wiring. An anisotropic etching is performed to form a groove 16 in the carbon layer 14. The mask is removed to obtain a structure as shown in FIG. Next, metal is deposited on the structure of FIG. 2 and excess metal is removed to obtain first layer wirings 20 and 22 as shown in FIG.

Subsequently, a thin layer 30 of silicon oxide is applied to the first
It is formed on the layer wirings 20 and 22 and on the carbon film 14. The thin layer 30 of silicon oxide is preferably deposited by sputtering to a thickness of approximately 500 °. Next, the structure is left in a furnace holding an oxygen atmosphere for approximately 2 hours at 400-450.
Heated at a temperature of ° C. In this atmosphere, oxygen easily diffuses through the silicon oxide thin layer 30 and the carbon film 1
4 to generate carbon dioxide gas, which diffuses again through the silicon oxide thin layer 30 and is released to the outside. As a result of performing this heat treatment for 2 hours, the entire carbon film 14 is removed, an air gap 32 remains between the oxide layer 30 and the interlayer dielectric 12, and as shown in FIG. Are separated by an air gap.

This process is repeated to produce a multi-layer interconnect structure as shown in FIG. That is, a carbon via hole layer is deposited and patterned to determine the location of the via hole where the vertical interlayer connection is to be formed. Carbon in via holes is removed, metal is deposited, etch back is performed, and vertical interlayer connections are formed in via holes. Thereafter, a thin oxide layer 40 is deposited on the carbon layer. A carbon burn-off process is performed to remove the carbon layer and between the vertical interlayer connections 36 and between the oxide layers 30,4.
A via hole layer air gap 42 is formed between 0.

Further, a carbon layer 44 is deposited on the second layer and patterned to provide a second layer wiring groove. Oxide layer 40 is suitably removed over vertical interlayer connections 36. The wiring groove is filled with metal to form a second layer wiring 46 which is in contact with the first layer wiring via the vertical interlayer connection.
A silicon oxide layer 50 (FIG. 5) is formed on the carbon layer 44 by sputtering, and a carbon burnout process is performed to form an air gap 52 between the second layer interconnects 46 and is depicted in FIG. The structure is completed.

[0013]

SUMMARY OF THE INVENTION The method of forming the structure depicted in FIG. 1 is described in terms of its simplicity and reliability as other interlayer connections using air as a dielectric material to separate adjacent wiring. When compared to the method of forming the structure, it is a simple and reliable process. However, there are aspects of the process for forming the structure of FIG. 1 that are incompatible with certain manufacturing processes. It is desired to provide a method for forming a multi-layer interconnect structure that is compatible with other requirements important for high density integrated circuit devices.

[0014]

According to the present invention, in order to form an integrated circuit device, a wiring pattern is formed on an insulating layer such that a first wiring is laterally separated from a second wiring by a layer of a sacrificial material. It is formed. After removing a portion of the sacrificial material layer so that the upper surface of the sacrificial material layer is lower than the upper surfaces of the first and second wirings, the capping material layer is removed from the upper surfaces of the first and second wirings and further sacrificed. It is formed on the upper surface of the material layer. A depletion reaction is performed through the capping material layer to further remove at least a portion of the sacrificial material layer to form an air dielectric between the first interconnect and the second interconnect, the upper boundary being defined by the capping material layer. I do.

Further, in the present invention, in order to form an integrated circuit device, a wiring pattern is formed on an insulating layer such that individual wirings are laterally separated by a layer of a sacrificial material. After the capping material layer is provided on the wiring pattern and on the upper surface of the sacrificial material, a consumption reaction is performed through the capping material layer to remove at least a part of the sacrificial material layer. The trace of the removed sacrificial material layer is used as an air dielectric.

After the depletion reaction, a layer of an etching stop material having a composition different from that of the capping material is formed on the capping material layer, and a dielectric layer between the metal conductors having a composition different from that of the etching stop material is formed on the etching stop layer. Formed. Via holes are formed by etching through the intermetal dielectric layer, stopping the etching in the etching stop layer, etching through the etching stop layer, and etching through the capping layer.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The conventional multi-layer connection structure depicted in FIG. 1 uses an air gap as a dielectric material inside which separates adjacent wiring and other conductors. The air gap 32 is formed by the first layer wiring 20.
And 22 function as an insulator. The low dielectric constant of air (K-1) results in an improvement in the dielectric constant (2-4) when using solid dielectric materials.

The connection structure of FIG. 1 has the effect of reducing the capacitive and inductive coupling between adjacent wires required for high density integrated circuit design. Since the capacitive and inductive coupling levels of this structure are reduced compared to conventional interconnect structures, the power consumption and operating speed of high density integrated circuits including the structure of FIG. 1 will be improved. However, the conventional connection structure of FIG. 1 has one aspect that hinders its application to such high-density integrated circuits.
It is difficult to make the structure of FIG. 1 compatible with the formation of landless via holes, which is often a feature of high-density integrated circuit design.

In the conventional structure shown in FIG. 1, in a region where a vertical interlayer connection is to be formed, the wiring is enlarged to facilitate the formation of the interlayer connection portion of the wiring. This enlarged pad area can be seen in FIG. That is, it is clear when the large width of the first layer wiring region 20 where the interlayer connection portion 36 is formed is compared with the first layer wiring level region 22 which is not related to the formation of the interlayer connection. Such a pad region of the first layer wiring is for allowing a slight error that may occur in a lithography process for providing the interlayer connection portion 36.

If the enlarged area of the first layer wiring is not formed in the structure of FIG. 1, both the vertical interlayer connection part and the first layer wiring part thereunder have the same dimensions. Become. As a result, the oxide layer 30 may be removed from above the air gap 32 due to a slight misalignment of the pattern or other lithographic errors when forming the via holes, or the oxide layer on the air gap 32 may be removed. 30 will be destroyed. Then, during the subsequent cleaning process, the inside of the air gap will be contaminated through the damage of the oxide layer. Furthermore, in the subsequent metal deposition process, metal is deposited in the air dielectric layer via the damaged oxide layer,
There is a possibility of causing a short circuit between the first layer wirings. As described above, it is difficult for the structure of FIG. 1 and the method for forming the structure of FIG. 1 to achieve both the formation of the landless via hole and the formation of the air dielectric layer.

Forming an unnecessarily large pad area in order to avoid pattern layout errors and lithography errors has become undesirable as the design rules of integrated circuits have become narrower. This is because such an enlarged pad area prevents the wiring from being arranged as close as possible to each other as far as the design rule allows. Therefore, it is desired to form via holes and wiring suitable for design rules. This means that formation of a landless via hole in the interlayer connection structure is desired.

It is a primary object of the present invention to provide a method for forming a multi-layer connection structure, which is compatible with formation of a landless via hole and use of an air gap as a dielectric material between adjacent wirings. In particular, in a preferred embodiment of the present invention, a carbon layer is deposited, a pattern groove is formed, the pattern groove is filled with a metal, a silicon oxide layer is deposited on the metal pattern and the carbon layer, and a carbon burnout treatment is performed. To remove the carbon layer from between the wirings to form an air gap. It is also preferred that an etch stop layer be provided on the metal pattern and on the oxide layer prior to the formation of a further layer, such as an intermetallic insulating layer.

By providing an etching stop layer on the oxide layer, the via hole etching process can reach the air gap in the landless region of the via hole regardless of the material constituting the intermetallic insulating layer. Without this, via holes can be formed in the oxide layer with high reliability via the inter-metal-conductor insulating layer.
Thus, the method according to the present invention is compatible with the processes used to form high density integrated circuit devices.

The present invention will be described in more detail with reference to FIGS. The formation of the multi-layer connection structure according to the present invention may be started in a manner similar to that described for the formation of the inter-layer connection structure of FIG. That is, a semiconductor substrate 60 having various devices formed on its surface is formed, and the substrate and the various devices are covered by the interlayer dielectric 62. The interlayer dielectric 62 is typically a silicon oxide, such as a single layer of CVD silicon oxide,
A combination of an oxide layer and a SOG (Spin On Glass) layer may be used. The via hole is formed through the intermediate dielectric 62. Metal or polysilicon internal connections are provided as part of the process for forming the first level interconnect or by a separate process.

The interlayer dielectric 62 is covered with a carbon layer. This carbon layer can be deposited, for example, by a high-density plasma CVD (HPCVD) process using methane (CH ₄ ) gas or acetylene (C ₂ H ₂ ) gas.
The optimal system for performing this deposition is Applied Material Cop, Santa Clara, California, USA
oration company is available,
Details are omitted. The carbon layer 64 is deposited to a thickness that is optimal for the first layer wiring, for example, a thickness of 5000-12000 °. A photoresist mask, more preferably, a hard film mask made of silicon oxide or silicon nitride is provided on the carbon layer 64 while exposing the carbon layer in a region where the first layer wiring is to be formed.

An anisotropic etching is performed, and a carbon layer 6 is formed.
A groove is formed in 4. Thereafter, the etching mask is removed. Metal is provided on the carbon layer 64 and in the trench.
As the metal used for the first layer wiring, aluminum, a refractory metal, or a multilayer compound of such a metal or a different conductive material can be used. The first layer wiring and other conductors separated by an air gap formed by carbon removal are preferably those that can withstand the carbon burning process at a temperature of 400 to 450 ° C. Etchback process, more preferably chemical mechanical polishing (CM
Excess metal is removed from the surface of the carbon layer 64 by any of the P) processes. Thereby, the first layer wiring 66 shown in FIG. 6 is obtained. The upper surface of the first layer wiring 66
Preferably, it is flush with the upper surface of the carbon layer 64,
This is easily obtained by a CMP process.

Next, the structure shown in FIG. 6 is set in a carbon burning-out system or an etching system,
4 is subjected to an oxygen plasma etching process to remove a part of the carbon layer 64 from the upper surface of the carbon layer. As a result, as shown in FIG. 7, a carbon region 68 having an upper surface receded by several hundred degrees from the upper surface of the first layer wiring is formed. Next, an oxide capping layer 70 is deposited on the carbon regions 68 and the first layer wiring 66. Capping layer 70
Extends along a part of the side surface of the first layer wiring 66. Forming the capping layer 70 to partially extend along the wall of the metal wiring increases the error tolerance of the etching process performed to expose the upper surface of the first wiring. Also, the capping layer 70 facilitates the formation of landless via holes.

In the present description, a burning reaction of carbon mainly consisting of oxidation is performed via the capping layer 70, the sacrificial carbon layer 68 is removed, and an air gap 74 as shown in FIG. Is formed. Due to the formation of the air gap, the capping layer 70 becomes the air gap 74.
Limits the extent of the top of the substrate, and supports the subsequently deposited layers. The capping layer 70 preferably has a thickness sufficient to provide structural support for the subsequently deposited layer, and is preferably formed to have an optimum thickness for the burnout reaction process.

As discussed in the prior art (Anand et al.), The thickness of the capping layer 70 is approximately 5
It is preferably about 00 °. Particularly preferred methods for forming the oxide capping layer 70 include:
Some deposit and harden from a liquid containing a polymer material to obtain a planarized oxide layer. This liquid preferably contains oxygen. For example, HSQ (hydrogen silses
A material known as quioxane) is supplied in liquid state on the structure of FIG. 7 and annealed in a nitrogen atmosphere at a temperature of about 400 ° C. for about 90 minutes to form an oxide capping layer 70 (nominally SiO _{3). / 2} ) is formed.

The method of forming the oxide capping layer 70, which is rotated on the liquid HSQ and hardens the HSQ, has an advantage that a smooth surface of the oxide layer can be automatically formed. This is the liquid polymer HS before curing
Spin on process to supply Q
That is why s) is used. Any other polymer or liquid material that can be deposited and cured to form a layer of dielectric material, or any other polymer or liquid material that can be solidified to form a layer of dielectric material , HSQ material can be used instead. The liquid used to form the capping layer may be a chemical reaction, such as the deposition of material from a saturated solution, or a process that occurs in the liquid, thereby supplying the material and forming an oxide capping layer. Things will be selected.

A process in which the smooth surface of the capping layer 70 is not formed naturally, for example, CVD or HDPCVD
If formed by such a process, a flattening process for forming a smooth plane is preferably performed. For example, if CVD oxide is used, it is preferred that the CVD oxide be planarized by a chemical mechanical polishing (CMP) process before starting further processing. The flattened plane further increases the process margin (error tolerance of the process) in a via hole etching step performed later.

A carbon burnout process is performed to remove carbon layer 68 from beneath oxide capping layer 70.
For example, this burning process is performed at 400 ° C. in an oxygen atmosphere.
It is performed at a temperature of 450 ° C. for a time sufficient to completely consume the thickness of the carbon layer via the oxide layer, for example, for 1 to 2 hours. Finally, the first layer wiring 66 is separated from the adjacent first layer wiring 66 by the air gap 74 by this process. The upper portion of the air gap 74 is defined by the capping layer, and the lower portion is defined by the interlayer dielectric 62.

The air gap forms a dielectric isolation between the first layer interconnects, and provides a relatively low level of capacitive and inductive coupling between adjacent first layer interconnects 66.
In this embodiment, carbon is the sacrificial material, and this sacrificial material is consumed and removed by an oxidation reaction performed through the oxide capping layer. The oxide capping layer has the properties expected in the present invention.
That is, the oxidative depletion reaction can easily proceed without excessive damage to the capping layer. For sacrificial materials, capping layers, and depletion reactions,
Other systems can also be used as long as equivalent operations and effects can be achieved.

The terms capping layer, sacrificial layer, and depletion reaction as used herein are named for their function in the present invention. For example, a depletion reaction refers more specifically to a reaction or process through a capping layer to remove a sacrificial layer from underneath the capping layer. It should be noted that alternative systems that can achieve certain advantages of the present invention can be employed. For example, a photoresist material would be used instead of a carbon sacrificial material under the use of a similar capping layer and a burn-out depletion reaction. Photoresist will achieve many of the same advantages of the present invention.

It is to be noted that, when viewed comprehensively, carbon has a low degree of pollution, can completely convert carbon to carbon dioxide by an oxidative burn-out reaction, and has a small amount of by-products of a volatile reaction. As a sacrificial material, it can be said that carbon is more preferable than photoresist. Nevertheless, in certain cases, photoresist will be employed because the amount of carbon consumed is small and the consumption reaction proceeds more quickly.

Next, an etch stop layer 72 will be formed on the capping layer 70, as shown in FIG. Generally, it is preferable that the etching stop layer has a composition different from that of the capping layer. What is important is that the etch stop layer be selected to be sufficiently different in composition from the layer formed over the etch stop layer, for example, the intermetal dielectric layer. The etch stop layer functions as an etch stop in the via hole etching process performed through the intermetal dielectric or other layers. Often used, the intermetal dielectric layer is an oxide of silicon and the etch stop layer is a nitride of silicon. For example, an etching stop layer made of silicon nitride has a thickness of about 20
It will be deposited to a thickness of 0-500 °.
The thickness of the nitride layer is determined so that it is not greater than necessary to provide an optimal etch stop.

The fact that nitride is deposited slowly during the process of forming the etch stop layer
The formation of excessively thick nitride is undesirable, for example, because excess nitride requires an unnecessarily long etch time in the via hole etching process required to form a hole through the via. If the intermetal dielectric layer is sufficiently different in composition from the oxide capping layer, the oxide capping layer may serve as an etch stop layer. If an oxide is used as the intermetal dielectric material, it is desirable to use a silicon nitride etch stop layer with the oxide capping layer.

After depositing the etch stop layer, an additional wiring layer will be formed by repeating the same technique used to form the air gap with the first layer wiring. That is, the etch stop layer is covered by a carbon layer, the carbon layer is patterned for interconnect formation, and further processing proceeds in a similar manner as described above. Accordingly, the process for forming the intermetallic dielectric, via hole, vertical coupling, and second layer interconnect will be fully understood in the following description. still,
Various air gaps, carbon or other materials may be included in the dielectric layer between the metal conductors where the vertical connection for connecting between the first layer wiring and the second layer wiring is formed. It should be noted.

As shown in FIG. 8, the inter-metal dielectric layer 76 is formed by, for example, a CVD method of synthesizing silicon oxide from a TEOS source gas by an etching stop layer 72.
Is deposited on the surface. For example, a via-hole mask is provided on the intermetallic dielectric layer 76 by providing a photoresist layer formed to serve as an etching mask by conventional photolithography. Via hole etching may be performed by using a number of dielectric etchants, including the LAM Rainbow system.

LA because the selectivity of the etching process between oxide and nitride is easy for the user to adjust.
It is particularly preferred to use the M rainbow system.
This is advantageous for performing the various stages of via-hole etching in a single process system employing a series of consecutive process steps while maintaining good process control. Via hole etching is performed via an intermetal dielectric layer by an etching agent. Preferably, the etchant used selectively etches the oxide at least immediately before the via-hole etch through the intermetal dielectric layer without sharply etching the etch stop layer.

An etching process with a relatively high etching rate but low selectivity is performed as an initial stage of the via hole etching process, followed by an etching process with improved selectivity and reduced etching speed as the second stage. It is also preferred. For example, the first
As a stage, a high speed, low selectivity via hole etching process is performed using a plasma of a source gas containing CF _4, and in a second stage, a slower, more selective etching process is performed using C ₂ F ₆ or C ₂ F _6. using a gas containing ₃ F ₈ will be performed. The first stage of the via hole etching process is used to partially etch through the intermetal dielectric layer, and is stopped before the etching process approaches the etch stop layer. The via hole etching process is then continued with a highly selective etch and stopped at the etch stop layer. Other optimal etching systems are known to those skilled in the art and are available.

Since the intermetallic dielectric layer 76 has a variation in thickness and a variation in etching characteristics that makes the result of the etching process for a fixed time unpredictable and unreliable, Providing a stop layer and employing an appropriate etching system is important in performing via hole etching. Subsequent etching steps performed to complete the via holes proceed through thinner layers. Etching through this thin layer needs to be more carefully controlled than in the etching process through a thick intermetal dielectric layer. In addition, because the etch stop layer and the capping layer are planarized, the etching process performed is more predictable and uniform than performed on inter-metal dielectric layers having varying thicknesses.

After the via hole is formed via the inter-metal dielectric layer 76 so as to extend vertically toward the first layer metal wiring 66, the via hole etching removes the etching stop layer 72 and the capping layer 70. The process is continued so as to reach the surface of the first layer wiring 66 via the first wiring. With respect to the nitride etch stop layer 72, the etch stop layer is removed by use of a nitride etchant, for example, a plasma obtained from a SF6 source gas. A part of the oxide capping layer 70 is formed in the via hole.
It is removed by a constant time etching process using a conventional oxide etchant. This etching through a thin, planarized oxide capping layer 70
It is easy to control and proceeds so as to sufficiently clean the surface of the wiring 66 but avoid complete etching through the capping layer 70. In FIG. 9, although most of the via holes are arranged on the first wiring 66,
Part of the via hole has a structure that is not arranged on the first wiring 66.

In the present invention, the formation of a capping layer that extends partially down along the walls of the first layer interconnect provides a sufficient margin to complete the via hole etching process. In other words, even if a slight error occurs in the position where the via hole etching process is performed,
It is possible to provide an error tolerance sufficient to prevent a failure in which the capping layer is damaged and the via hole communicates with the air gap 74. As already explained, this structural feature is to etch back part of the carbon sacrificial layer prior to depositing the capping layer, or to expose part of the sidewalls of the first layer wiring to the top of the carbon layer. Is obtained by denting.

The process continues after the formation of the via hole, the surface of the wiring 66 is cleaned, and a metal plug 78 is formed to fill the via hole. The metal plug is preferably formed of aluminum, but may be formed of tungsten by a CVD process using WF ₆ as a source gas. In many cases, plug formation begins with forming an adhesive or adhesive layer, such as titanium or titanium nitride, in the via hole and on the surface of the intermetallic dielectric layer 76. After an adhesive or an adhesive layer is formed by a sputtering or CVD process, tungsten is supplied to the CVD process, and the inside of the via hole is filled with a tungsten plug. Then, a chemical mechanical polishing (CMP) or an etch-back process is performed to form a vertical extension of the tungsten plug 78 and to remove excess tungsten from the surface of the intermetallic dielectric layer 76. This polishing or etchback process is for removing unnecessary portions of the adhesive layer.

Further processing is continued to form a second layer wiring, such as wiring 80 shown in FIG.
The second layer wiring is made by blanket metal deposition and normal photolithography or etching process.
ss). The present invention is intended to describe a preferred embodiment, and changes and modifications to this process and structure will be made by those skilled in the art without changing the basic technology of the present invention. . For example, in this specification, the formation of the adjacent first-layer wiring and the second-layer wiring is described for easy understanding of the present invention. The same is true for some. Thus, the present invention is not limited to a particular embodiment, but the scope of the present invention should be determined from the following claims.

[Brief description of the drawings]

FIG. 1 is a schematic view showing a conventional multilayer connection structure including an air gap as a dielectric material for separating adjacent wirings.

FIG. 2 is a schematic view showing a method of forming the multilayer connection structure of FIG. 1;

FIG. 3 is a schematic view showing a method of forming a multi-layer connection structure performed after FIG. 2;

FIG. 4 is a schematic view showing a method of forming a multilayer connection structure performed after FIG. 3;

FIG. 5 is a schematic view showing a method for forming a multilayer connection structure performed after FIG. 4;

FIG. 6 is a schematic view showing a method of forming a multi-layer connection structure according to an embodiment of the present invention.

FIG. 7 is a schematic diagram showing a method of forming a multilayer connection structure performed after FIG. 6;

FIG. 8 is a schematic view showing a method of forming a multilayer connection structure performed after FIG. 7;

FIG. 9 is a schematic view showing a method of forming a multilayer connection structure performed after FIG. 8;

[Explanation of symbols]

 Reference Signs List 60 semiconductor substrate 62 0 intermediate layer dielectric 66 first layer wiring 74 air gap 70 capping layer 72 etching stop layer 76 dielectric layer between metal conductors 78 metal plug 80 second layer wiring

Claims (38)

[Claims] A wiring pattern is provided on an insulating layer so that a first wiring is laterally separated from a second wiring by a sacrificial material layer, and an upper surface of the sacrificial material layer is lower than upper surfaces of the first and second wirings. A capping material layer is provided on the first and second wirings and on the upper surface of the sacrificial material layer, and the sacrificial material layer is interposed through the capping material layer. An integration, wherein at least a portion of the sacrificial material layer is further removed by a layer consumption reaction to form an air dielectric between the first wiring and the second wiring, the upper boundary being defined by the capping material layer. A method for forming a circuit device. 2. The method according to claim 1, wherein the capping material is an oxide, and the depletion reaction is an oxidation process. 3. The method according to claim 2, wherein said sacrificial material includes carbon. 4. The method of claim 3, wherein said sacrificial material consists essentially of carbon. 5. The method according to claim 4, wherein the exhaustion reaction is continued until all of the sacrificial material layer between the first wiring and the second wiring is removed. 6. The semiconductor device according to claim 2, wherein the capping material layer is formed by supplying a liquid layer on the first wiring and the second wiring and curing the liquid layer to a solid oxide layer.
The forming method as described above. 7. The liquid is HSQ (hydrogen silsesquioxa).
The method according to claim 6, wherein ne) is satisfied. 8. The method according to claim 1, wherein the capping material layer is formed by supplying a liquid onto the first wiring and the second wiring in a spin-on process. . 9. The method according to claim 8, wherein the capping material in the liquid is cured to form the capping material layer. 10. The method of claim 8, wherein said liquid comprises a polymer material. 11. The method according to claim 9, wherein said liquid contains oxygen. 12. The method according to claim 1, wherein the capping layer covers upper surfaces of the first wiring and the second wiring, and the capping layer is planarized. 13. The sacrificial material layer is patterned to form a groove, metal is supplied in the groove and on the sacrificial material layer, and excess metal is removed to form the wiring pattern in the sacrificial material layer. The method according to claim 1, wherein: 14. The method according to claim 13, wherein the step of removing excess metal is performed by chemical mechanical polishing. 15. After the depletion reaction, a layer of an etching stop material having a composition different from the capping material is provided on the capping material layer, and the inter-metal dielectric layer having a composition different from the etching stop material is formed on the capping material layer. Provided on an etching stop material layer, etching through the intermetallic dielectric layer, stopping etching in the etching stop material layer, etching through the etching stop material layer, and via the capping material layer 2. The method according to claim 1, wherein a via hole is formed by etching. 16. The method of claim 15, wherein the step of etching through the capping layer cleans the surface of the first interconnect but does not etch through the entire thickness of the capping material layer. Method. 17. The method according to claim 16, wherein most of the via holes are arranged on the first wiring, but part of the via holes are not arranged on the first wiring. 18. An etching process through the intermetal dielectric layer comprising a first stage which is a relatively high-speed etching process and a second stage which is an etching process having a relatively high selectivity. 17. The forming method according to claim 16, wherein: 19. The capping material is an oxide,
The method of claim 15, wherein the etch stop material is a nitride. 20. The method according to claim 19, wherein said intermetallic dielectric material includes an oxide. 21. A wiring pattern is formed on an insulating layer so that individual wirings are laterally separated by a sacrificial material, a capping layer is provided on the wiring pattern and on an upper surface of the sacrificial material, and via the capping layer. Depleting at least a portion of the sacrificial material layer by the depletion reaction of the sacrificial material layer, leaving an air dielectric on the trace of the depleted sacrificial material layer, providing an etching stop layer on the capping layer after the depletion reaction,
An intermetallic dielectric material layer having a composition different from that of the etching stop layer is provided on the etching stop layer, and etching is performed through the intermetallic dielectric layer, etching is stopped in the etching stop layer, and the etching is stopped through the etching stop layer. Forming a via hole by etching the semiconductor substrate and etching through a capping layer. 22. The method according to claim 21, wherein the etching stop layer has a composition different from that of the capping layer. 23. The method according to claim 21, wherein the step of etching through the capping layer cleans the surface of the wiring but does not etch through the entire thickness of the capping layer. 24. The method according to claim 21, wherein the capping material layer is formed by supplying a liquid layer on the first wiring and the second wiring and curing the liquid layer to a solid layer containing an oxide. Formation method. 25. The liquid is HSQ (hydrogen silsesquio).
25. The forming method according to claim 24, wherein xane) is used. 26. The method according to claim 21, wherein said capping layer is an oxide, and said depletion reaction is an oxidation process. 27. The method according to claim 26, wherein said sacrificial material includes carbon. 28. The method according to claim 27, wherein said sacrificial material consists essentially of carbon. 29. The method according to claim 26, wherein the depletion reaction is continued until all of the sacrificial material layer below the capping layer is removed. 30. A method according to claim 21, wherein a portion of the sacrificial material layer is removed such that an upper surface of the sacrificial material layer is located below an upper surface of the wiring before forming the etching stop layer. The forming method as described above. 31. The method of claim 30, wherein the sacrificial material is carbon, the capping layer is an oxide, and the etch stop layer is a nitride. 32. The method according to claim 21, wherein said via hole is filled with a metal plug. 33. The metal plug, comprising:
33. The method according to claim 32, wherein the wiring is connected to a layer wiring. 34. The method according to claim 33, wherein said metal plug contains tungsten. 35. The method according to claim 21, wherein the step of forming the capping material layer includes supplying a liquid onto the wiring in a spin-on process. 36. The method according to claim 21, wherein the step of forming the capping material layer includes supplying a liquid onto the wiring, and the liquid is solidified to form the capping material layer. Method. 37. The method according to claim 35, wherein said liquid comprises a polymer material. 38. The method according to claim 36, wherein said liquid contains oxygen.