JPH11163261A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPH11163261A
JPH11163261A JP9324173A JP32417397A JPH11163261A JP H11163261 A JPH11163261 A JP H11163261A JP 9324173 A JP9324173 A JP 9324173A JP 32417397 A JP32417397 A JP 32417397A JP H11163261 A JPH11163261 A JP H11163261A
Authority
JP
Japan
Prior art keywords
substrate
semiconductor device
back surface
chip
wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9324173A
Other languages
Japanese (ja)
Inventor
Shinichi Ofuji
晋一 大藤
Manabu Henmi
学 逸見
Hideyuki Unno
秀之 海野
Shigeo Ogawa
重男 小川
Masahiko Maeda
正彦 前田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP9324173A priority Critical patent/JPH11163261A/en
Publication of JPH11163261A publication Critical patent/JPH11163261A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/57Protection from inspection, reverse engineering or tampering
    • H01L23/573Protection from inspection, reverse engineering or tampering using passive means
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having irregular reflection surface and the manufacturing method thereof, which is capable of preventing unautorixzed acts, such as the tampering and the like for decoding and the memory information of the pattern of an integrated circuit which constitutes the semiconductor device, performed by having infrared rays irradiated from the side of the back surface of a substrate which constitutes the semiconductor device, even in the semiconductor device having a substrate with a thin plate thickness and the substrate cut into chip shapes. SOLUTION: In this semiconductor device, the irregular reflection of the light inputted from the side of a back surface 2 is promoted to the back surface 2 of a substrate 1 in the semiconductor device, in which an integrated circuit is arranged on the surface of the substrate 1. The assembly of an indentation 4 and a projection constituted of a plane, not in parallel with the surface of the substrate 1, is provided. In a manufacturing method of this semiconductor device, the indentation and the projection are formed by having the many points of the back surface 2 of the substrate 1 irradiated with the focused energy beam.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体装置及びそ
の製造方法に係る。より詳細には、半導体装置を構成す
る基板の裏面側から赤外光を照射して行われる、半導体
装置を構成する集積回路パターンの解読や記憶情報の改
竄等の不法行為を防ぐことができる半導体装置及びその
製造方法に関する。本発明は、ICカード等に利用され
て個人のプライバシーや金銭等の重要な情報を記憶およ
び処理する機能を備えた半導体装置及びその製造方法に
好適に用いられる。
The present invention relates to a semiconductor device and a method for manufacturing the same. More specifically, a semiconductor capable of preventing illegal acts such as decoding of an integrated circuit pattern constituting a semiconductor device and falsification of stored information, which are performed by irradiating infrared light from the back side of a substrate constituting the semiconductor device. The present invention relates to an apparatus and a method for manufacturing the same. INDUSTRIAL APPLICABILITY The present invention is suitably used for a semiconductor device having a function of storing and processing important information such as personal privacy and money used in an IC card or the like, and a manufacturing method thereof.

【0002】[0002]

【従来の技術】近年、ICカード等に利用されて個人の
プライバシーや金銭などの重要な情報を記憶および処理
する機能を備えた半導体装置が注目され、その実用化を
図るための研究・開発が急ピッチで進めれている。
2. Description of the Related Art In recent years, attention has been paid to a semiconductor device having a function of storing and processing important information such as personal privacy and money used in an IC card or the like, and research and development for realizing the semiconductor device have been attracting attention. It is progressing rapidly.

【0003】上記機能を有する半導体装置を開発するた
めには、設計・製造技術の改良や不良品の原因究明など
の目的で、半導体装置を構成する集積回路(IC)の機
能、動作方式、回路方式、回路パタン、記憶データ等を
解析する技術が必須である。従来、その解析法の一つと
して半導体装置を構成する基板上のICチップ表面を光
学顕微鏡で観察し、回路パタンを読みとる手法が用いら
れてきた。1μm以下の微細なパタンに対しては、観察
光の波長がパタン幅に近いことから、回折の影響を軽減
するために比較的波長の短いレーザ光が用いられ、分解
能及び焦点深度の向上が図られてきた。しかし、配線層
が多層化されるにつれて、下層の配線パターンを精度良
く読みとるためには上層の膜を除去する必要があり、I
Cを動作させたままの非破壊では観察できないという欠
点があった。また、EEPROM(Electrically Erasa
ble Programmable Read Only Memory)のデータは最下
層のMOSトランジスタのゲート電極に記憶されている
ため、ICチップの表面側からの観察はこれらの回路観
察には必ずしも有効な手段ではなかった。
In order to develop a semiconductor device having the above-mentioned functions, the functions, operating methods, and circuit functions of an integrated circuit (IC) constituting the semiconductor device have been developed for the purpose of improving design and manufacturing techniques and investigating causes of defective products. Techniques for analyzing methods, circuit patterns, stored data, and the like are essential. Conventionally, as one of the analysis methods, a method of observing an IC chip surface on a substrate constituting a semiconductor device with an optical microscope and reading a circuit pattern has been used. For fine patterns of 1 μm or less, since the wavelength of the observation light is close to the pattern width, a laser beam with a relatively short wavelength is used to reduce the effect of diffraction, and the resolution and depth of focus are improved. I have been. However, as the number of wiring layers increases, it is necessary to remove the upper film in order to accurately read the lower wiring pattern.
There is a defect that observation is not possible without destruction while C is operated. In addition, an EEPROM (Electrically Erasa
Since the data of the bleedable programmable read only memory (MEM) is stored in the gate electrode of the lowermost MOS transistor, observation from the front side of the IC chip is not always effective means for observing these circuits.

【0004】このような光学顕微鏡を用いた手法を補う
方法としては、例えばICチップの裏面側から非破壊で
チップ表面近傍の回路を観察する方法が挙げられる。す
なわち、ICチップの基板であるシリコンウェハに吸収
されにくい波長の赤外線を観察光源として用い、ウェハ
の透明性を高めて主に金属からなる配線パタンなどを裏
面側からウェハを通して観察可能にする方法である。こ
の方法によれば、最下層のトランジスタのパタンや第1
層の配線パタンを非破壊で観察することができる。特
に、最近の高密度実装技術では、ICチップの表面側に
実装基板との電気的な接続を取るためのバンプ電極が形
成され、ICチップを裏返して実装基板上に接続する方
法が取られている。従って、実装した状態ではICチッ
プの裏面が外面に露出した状態となり、ICチップの表
面側以上に裏面側からのパタン観察が容易になった。ま
た、従来から、ICチップの裏面にはチップ保護用のエ
ポキシ膜等がコーティングされているのみであり、化学
薬品にて比較的容易に除去が可能な状態にあった。
As a method for supplementing such a method using an optical microscope, for example, there is a method of observing a circuit near the chip surface in a non-destructive manner from the back side of the IC chip. In other words, a method of using infrared light having a wavelength that is hardly absorbed by a silicon wafer, which is a substrate of an IC chip, as an observation light source and increasing the transparency of the wafer so that a wiring pattern mainly made of metal can be observed through the wafer from the back side. is there. According to this method, the pattern of the lowermost transistor and the first transistor
The wiring pattern of the layer can be observed nondestructively. In particular, in recent high-density mounting technology, a bump electrode is formed on the front side of an IC chip for electrical connection with a mounting substrate, and a method of connecting the IC chip to the mounting substrate by turning over the IC chip is adopted. I have. Therefore, in the mounted state, the back surface of the IC chip is exposed to the outer surface, and pattern observation from the back surface side becomes easier than the front surface side of the IC chip. Conventionally, the back surface of an IC chip has only been coated with an epoxy film or the like for protecting the chip, and has been in a state where it can be relatively easily removed with a chemical.

【0005】一方、上述した方法、すなわち半導体基板
を構成する集積回路(IC)の機能、動作方式、回路方
式、回路パタン、記憶データ等を解析する技術、が悪用
された場合に防御できる技術の開発が求められている。
例えば、ICカード等に利用されて個人のプライバシー
や金銭等の重要な情報を記憶および処理する機能を備え
た半導体装置では、広く普及させるためには必須の技術
である。
On the other hand, the above-mentioned method, that is, a technique for analyzing the function, operation method, circuit method, circuit pattern, stored data, etc. of an integrated circuit (IC) constituting a semiconductor substrate, is a technique capable of protecting against misuse. Development is required.
For example, a semiconductor device having a function of storing and processing important information such as personal privacy and money used in an IC card or the like is an essential technology for widespread use.

【0006】従来、半導体基板のみならず、一般に膜や
板により被覆された部分に格納された情報を光学的手段
による観察から守る方法としては、次に示すような膜や
基板の表面または裏面に乱反射面を形成する方法が用い
られてきた。
Conventionally, as a method for protecting information stored not only on a semiconductor substrate but also on a portion generally covered with a film or a plate from observation by optical means, the following method is used to protect the surface or the back of the film or substrate. A method of forming a diffuse reflection surface has been used.

【0007】図4は、従来の機械的な研削法を用いて、
乱反射面を表面に設けた基板の模式的な鳥瞰図である。
例えば、45度の角度の付いた乱反射面12を形成する
場合は、研磨剤入りの45度の傾斜刃の付いたグライン
ダーを用いてガラス基板11の表面を研削処理すること
により得られる。凹凸のピッチは1mm程度のサイズと
することが可能であり、この例では角度を45度とした
こともあり、ガラス基板の厚さは最低1mm以上が要求
される。
FIG. 4 shows a conventional mechanical grinding method.
It is a typical bird's-eye view of the board | substrate which provided the irregular reflection surface on the surface.
For example, in the case of forming the irregular reflection surface 12 having a 45-degree angle, the surface of the glass substrate 11 can be obtained by grinding the surface of the glass substrate 11 using a grinder having a 45-degree inclined blade containing an abrasive. The pitch of the unevenness can be set to a size of about 1 mm. In this example, the angle may be set to 45 degrees, and the thickness of the glass substrate is required to be at least 1 mm.

【0008】しかしながら、ICチップなどの1μm以
下の微細な線幅のパタンを描画した基板は、一般に1m
m以下の厚さのものが主流である。例えばシリコン基板
では一般に600μmからさらに研削して200μm前
後の厚さが多用される。従って、ICチップなどの情報
を高密度に描画した情報媒体への乱反射面の形成には、
上述したグラインダーによる研削法を適用できないとい
う問題があった。
However, a substrate, such as an IC chip, on which a pattern with a fine line width of 1 μm or less is drawn, generally has a size of 1 m.
m or less is the mainstream. For example, in the case of a silicon substrate, a thickness of about 200 μm is generally used by further grinding from 600 μm. Therefore, to form a diffuse reflection surface on an information medium on which information such as an IC chip is drawn at a high density,
There is a problem that the above-described grinding method using a grinder cannot be applied.

【0009】図5は、従来の化学的なエッチング法を用
いて、基板の裏面に乱反射面を形成する工程を示した模
式的な断面図である。基板としては、(100)面から
なるシリコンウェハ21を用意し(図5(a))、裏面
に化学的気相成長法(CVD法)を用いて厚さ2μmの
SiO2膜22を堆積する(図5(b))。次いで、写
真蝕刻技術を用いてSiO2膜22をストライプ状に加
工し、SiO2パタン23を形成する(図5(c))。
その後、SiO2パタン23をマスクにしてエチレンジ
アミン水溶液中でシリコンウェハ21の化学的エッチン
グを行うことにより、ウェハ面から約55度の角度で傾
斜が形成され、(100)面からなるエッチング底面2
4がエッチングの進行と共に下方へ沈む(図5
(d))。最終的に両側の傾斜がぶつかってエッチング
が自動停止して略V字型の谷25が形成される(図5
(e))。その後、フッ酸にてSiO2パタン23を除
去することにより、開口部26を有する乱反射面が形成
される(図5(f))。
FIG. 5 is a schematic cross-sectional view showing a process of forming a diffuse reflection surface on the back surface of a substrate by using a conventional chemical etching method. As a substrate, a silicon wafer 21 having a (100) plane is prepared (FIG. 5A), and a 2 μm-thick SiO 2 film 22 is deposited on the back surface using a chemical vapor deposition method (CVD method). (FIG. 5 (b)). Next, the SiO 2 film 22 is processed into a stripe shape by using a photolithography technique to form an SiO 2 pattern 23 (FIG. 5C).
Thereafter, the silicon wafer 21 is chemically etched in an aqueous solution of ethylenediamine using the SiO 2 pattern 23 as a mask, whereby an inclination is formed at an angle of about 55 degrees from the wafer surface, and the etching bottom surface 2 of (100) plane is formed.
4 sinks downward as the etching progresses (FIG. 5).
(D)). Eventually, the slopes on both sides collide with each other and the etching is automatically stopped to form a substantially V-shaped valley 25 (FIG. 5).
(E)). Then, the irregular reflection surface having the opening 26 is formed by removing the SiO 2 pattern 23 with hydrofluoric acid (FIG. 5F).

【0010】しかしながら、この方法には次に示すよう
な問題があった。 (1)SiO2パタン23をマスクとしてシリコンウェ
ハ21の化学的エッチングを行うため、基板裏面のうち
エッチング後にマスクを除去した領域には平坦部27が
残存し、この領域27は基板表面と平行な位置関係が維
持されてしまう。従って、この領域27を利用すること
によって、基板の裏面側から赤外光を照射し、半導体装
置を構成する集積回路パターンの解読や記憶情報の改竄
等の不法行為を行う可能性が残されていた。
However, this method has the following problems. (1) Since the silicon wafer 21 is chemically etched using the SiO 2 pattern 23 as a mask, a flat portion 27 remains in a region of the back surface of the substrate where the mask is removed after the etching, and this region 27 is parallel to the substrate surface. The positional relationship is maintained. Therefore, by using this region 27, there is a possibility that an infrared light is irradiated from the back surface side of the substrate to perform an illegal act such as decoding of an integrated circuit pattern constituting the semiconductor device or falsification of stored information. Was.

【0011】(2)この方法では写真蝕刻技術を使うこ
とから、例えば直径が6インチ等の円形ウェハ全体を加
工工程に投入する必要がある。しかし、ウェハ裏面を研
削してウェハ厚さを薄くした後にはウェハ強度が小さく
なるため、このようなウェハに対して、水洗、酸液への
浸漬、回転乾燥などの工程を含む写真蝕刻技術を適用す
るのは非常に難しい。また、強度の低下したウェハを処
理するためには、ウェハを他の保護基板に貼り付けるな
どの煩雑な工程も要するという欠点があった。さらに、
ひとたびチップ状にウェハを切り分けた後には写真蝕刻
技術を適用できないという欠点もあった。
(2) In this method, since a photolithography technique is used, it is necessary to put a whole circular wafer having a diameter of, for example, 6 inches into a processing step. However, since the wafer strength is reduced after the wafer thickness is reduced by grinding the back surface of the wafer, such a wafer is subjected to photographic etching technology including processes such as washing with water, immersion in an acid solution, and spin drying. Very difficult to apply. In addition, in order to process a wafer with reduced strength, there is a disadvantage that a complicated process such as attaching the wafer to another protective substrate is required. further,
Once the wafer has been cut into chips, the photolithography technique cannot be applied.

【0012】以上説明した通り、従来の基板への乱反射
面の形成法によれば、以下の問題点があった。すなわ
ち、機械的な研削法には、厚さの薄い基板に対して微細
な加工ができない点があり、化学なエッチング法には、
マスクを除去した領域は基板表面と平行な位置関係が維
持されてしまう点と、チップ状に切断したウェハ基板に
対しては加工が困難な点とがあった。
As described above, according to the conventional method of forming a diffuse reflection surface on a substrate, there are the following problems. In other words, the mechanical grinding method has a point that fine processing cannot be performed on a thin substrate, and the chemical etching method has
The region from which the mask has been removed has a point that the positional relationship parallel to the substrate surface is maintained, and there is a point that it is difficult to process the wafer substrate cut into chips.

【0013】ゆえに、従来の半導体装置を構成する基板
への乱反射面の形成法では、薄い板厚の基板やチップに
切断した基板に対して、乱反射を簡便に形成することは
できなかった。従って、ひとたび半導体装置を構成する
集積回路パターンの解読や記憶情報の改竄等の不法行為
を目的に、チップ裏面から観察や解析を実施されると従
来技術では阻止し難いという問題があった。
Therefore, in the conventional method of forming a diffuse reflection surface on a substrate constituting a semiconductor device, diffuse reflection cannot be easily formed on a substrate having a small thickness or a substrate cut into chips. Therefore, once observation or analysis is performed from the back of the chip for the purpose of illegal acts such as decoding of an integrated circuit pattern constituting the semiconductor device or falsification of stored information, there is a problem that it is difficult to prevent the conventional technique.

【0014】[0014]

【発明が解決しようとする課題】本発明は、薄い板厚の
基板やチップ状に切断した基板からなる半導体装置にお
いても、該半導体装置を構成する基板の裏面側から赤外
光を照射して行われる、半導体装置を構成する集積回路
パターンの解読や記憶情報の改竄等の不法行為を防止で
きる乱反射面を有する半導体装置及びその製造方法を提
供することを目的とする。
SUMMARY OF THE INVENTION The present invention relates to a semiconductor device comprising a thin substrate or a substrate cut into chips, which is provided by irradiating infrared light from the back side of the substrate constituting the semiconductor device. It is an object of the present invention to provide a semiconductor device having a diffuse reflection surface capable of preventing illegal actions such as decoding of an integrated circuit pattern constituting the semiconductor device and falsification of stored information, and a method of manufacturing the same.

【0015】[0015]

【課題を解決するための手段】本発明の半導体装置は、
基板の表面上に集積回路が配設された半導体装置におい
て、該基板の裏面に、該裏面側から入射した光の乱反射
を促す、該基板の表面とは非平行な面から構成された窪
み及び突起の集合体を設けたことを特徴とする。
According to the present invention, there is provided a semiconductor device comprising:
In a semiconductor device in which an integrated circuit is provided on a surface of a substrate, a back surface of the substrate, which promotes irregular reflection of light incident from the back surface side, a recess formed of a surface non-parallel to the surface of the substrate, It is characterized in that a set of projections is provided.

【0016】上記構成からなる窪み及び突起の集合体を
基板の裏面に設けたことにより、基板の裏面側から赤外
光を照射しても、該裏面側から入射した光は乱反射され
るので、該基板の裏面側では、該基板の表面上に配設さ
れた集積回路からの反射光が乱された形でしか得られな
い。従って、該基板の表面上に配設された集積回路パタ
ーンの解読や記憶情報の改竄等の不法行為を防ぐことが
できる。
By providing the aggregate of depressions and projections having the above-described structure on the back surface of the substrate, even if infrared light is irradiated from the back surface of the substrate, the light incident from the back surface is irregularly reflected. On the back side of the substrate, the reflected light from the integrated circuit disposed on the surface of the substrate can be obtained only in a disturbed form. Therefore, illegal acts such as decoding of the integrated circuit pattern disposed on the surface of the substrate and falsification of stored information can be prevented.

【0017】上記特徴において、前記窪みの断面形状を
略V字型としたとき、基板の裏面側から入射した光の乱
反射が最も効果的に生じることから好ましい。
In the above feature, it is preferable that the cross-sectional shape of the depression is substantially V-shaped, since diffused reflection of light incident from the back side of the substrate occurs most effectively.

【0018】本発明の半導体装置の製造方法は、基板の
表面上に集積回路を有し、該基板の裏面上に、該裏面側
から入射した光の乱反射を促す、該基板の表面とは非平
行な面から構成された窪み及び突起の集合体を設けた半
導体装置の製造方法において、前記窪み及び突起は、集
束したエネルギービームを前記基板の裏面の多数点に照
射して形成することを特徴とする。
According to a method of manufacturing a semiconductor device of the present invention, an integrated circuit is provided on a front surface of a substrate, and irregular reflection of light incident from the back surface is promoted on the back surface of the substrate. In a method of manufacturing a semiconductor device provided with an aggregate of dents and projections formed of parallel surfaces, the dents and projections are formed by irradiating a focused energy beam to a plurality of points on the back surface of the substrate. And

【0019】集束したエネルギービームを前記基板の裏
面の多数点に照射することにより、基板の裏面に窪みを
形成すると共に、該窪みから移動した物質が該窪みの周
辺部に堆積されて突起も形成することができる。従っ
て、本発明の方法によれば、該基板の表面とは非平行な
面から構成された窪み及び突起の集合体を、該基板の裏
面に効率的に形成することが可能である。
By irradiating the focused energy beam to a plurality of points on the back surface of the substrate, a dent is formed on the back surface of the substrate, and a substance transferred from the dent is deposited on the periphery of the dent to form a projection. can do. Therefore, according to the method of the present invention, it is possible to efficiently form an aggregate of depressions and projections formed of a surface that is not parallel to the surface of the substrate on the back surface of the substrate.

【0020】特に、前記エネルギービームとして集光性
レーザビームを用いた場合には、光の乱反射や散乱性の
高いV字型の窪みを容易に形成できることから好まし
い。スパッタリング現象を利用してないので、飛散する
ダストの悪影響が少ないという利点もある。
In particular, it is preferable to use a condensing laser beam as the energy beam because a V-shaped recess having a high degree of irregular reflection and scattering of light can be easily formed. Since the sputtering phenomenon is not used, there is also an advantage that the adverse effect of the scattered dust is small.

【0021】[0021]

【発明の実施の形態】以下、図1〜図3を参照して本発
明の実施の形態を詳細に述べる。図1は、本発明に係る
半導体装置の製造工程を示す模式的な断面図である。図
2は、レーザビームの照射回数と得られた窪み及び突起
の形状を示す模式的な断面図である。図3は、本発明に
係る方法を用いて窪み及び突起を形成したICチップ裏
面の概略図である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to FIGS. FIG. 1 is a schematic sectional view showing a manufacturing process of a semiconductor device according to the present invention. FIG. 2 is a schematic cross-sectional view showing the number of laser beam irradiations and the shapes of the obtained dents and protrusions. FIG. 3 is a schematic view of the back surface of an IC chip in which depressions and protrusions are formed by using the method according to the present invention.

【0022】以下では、製造工程の手順に従って説明す
る。 (1)まず、チップのサイズが4mm角からなる集積回
路を有する半導体装置を、直径6インチのシリコンウエ
ハ表面に薄膜堆積技術と写真蝕刻技術等を用いて形成し
た。ウエハの厚さを625μm、最小パタンの線幅を
0.5μmとした。集積回路としては、8ビットの中央
演算装置の他に、1キロバイトのRAM(Random Acces
s Memory)、8キロバイトのROM(Read Only Memor
y)、及び8キロバイトの不揮発性EEPROMを設け
た。ウエハ表面に表面保護用のSi34及びSiO2
らなるパシベーション膜を形成し、ウエハの前処理工程
を終えた。その後、ウエハ裏面を研削してウエハ基板1
の厚さを200μmとし、チップに切断した(図1
(a))。
Hereinafter, description will be made in accordance with the procedure of the manufacturing process. (1) First, a semiconductor device having an integrated circuit having a chip size of 4 mm square was formed on the surface of a silicon wafer having a diameter of 6 inches using a thin film deposition technique and a photolithography technique. The thickness of the wafer was 625 μm, and the line width of the minimum pattern was 0.5 μm. As an integrated circuit, in addition to an 8-bit central processing unit, 1 kilobyte of RAM (Random Acces
s Memory), 8 KB ROM (Read Only Memor)
y), and 8 kilobytes of non-volatile EEPROM. A passivation film made of Si 3 N 4 and SiO 2 for surface protection was formed on the surface of the wafer, and the wafer pretreatment step was completed. Then, the wafer back surface is ground to grind the wafer substrate 1
Was cut into chips having a thickness of 200 μm (FIG. 1).
(A)).

【0023】(2)次いで、本発明に係る基板の裏面2
側への凹凸形成工程を行った。すなわち、ウエハ基板の
裏面2にレーザが照射されるようにレーザマーカ装置へ
チップを装填し、ウエハ基板の裏面2に凹凸を形成する
ため集光性レーザビーム3を照射した(図1(b))。
レーザ光源には、レーザダイオードを励起光源とした超
音波Qスイッチ付きのNdドープYAGレーザを使用し
た。使用した波長は第二高調波の532nmであり、パ
ルス発振モードはTEM00のシングルモード、出力エネ
ルギーは16μJ、パルス幅は1kHzで25nsec
以下とした。
(2) Next, the back surface 2 of the substrate according to the present invention
A step of forming unevenness on the side was performed. That is, a chip was loaded into a laser marker device so that the back surface 2 of the wafer substrate was irradiated with a laser, and a converging laser beam 3 was irradiated to form irregularities on the back surface 2 of the wafer substrate (FIG. 1B). .
As a laser light source, an Nd-doped YAG laser equipped with an ultrasonic Q switch using a laser diode as an excitation light source was used. Wavelength used was 532nm second harmonic, the pulse oscillation mode single mode TEM 00, an output energy is 16MyuJ, pulse width is 1 kHz 25 nsec
It was as follows.

【0024】(3)光学系はガルバノメータ型ビームポ
ジショナ(不図示)で制御した。レーザービームの光は
不図示のレンズで絞り、ウエハ基板の裏面2に形成する
窪みの深さに焦点を合わせた(図2(b))。所定の照
射位置に対して3つのパルスを照射した(図2(b):
第1パルス照射後→図2(c):第2パルス照射後→図
2(d):第3パルス照射後)。
(3) The optical system was controlled by a galvanometer type beam positioner (not shown). The light of the laser beam was stopped down by a lens (not shown) and focused on the depth of a dent formed on the back surface 2 of the wafer substrate (FIG. 2B). A predetermined irradiation position was irradiated with three pulses (FIG. 2 (b):
(After irradiation of the first pulse → FIG. 2 (c): After irradiation of the second pulse → FIG. 2 (D): After irradiation of the third pulse).

【0025】(4)上記工程(3)の処理によって、ウ
エハ基板の裏面2には円形でクレータ状の窪み(凹部)
4が形成された。シリコンはレーザ光を吸収したことに
よる熱で溶融し、中央部がへこんで溶融物は周辺部に押
しやられ、周辺部はウエハ1の裏面よりも盛り上がった
部分(凸部)5が形成された(図2(d)、図1(c)
の丸円内に示す拡大図)。以下では、この凹部4と凸部
5との組合せからなる凹凸部分を照射痕跡と呼ぶ。平均
的な凹凸の形状は、直径:Lが60μm、ウエハ面から
の凹部の深さ:Dが5μm、周辺部の凸部の高さ:Hは
3μmであった。凹部の断面形状は、光源のガウス分布
に近いエネルギー分布をそのまま残して集光し、かつ上
述の焦点位置の設定方法を採用したことにより、概ねV
字型の形状が得られた(図2(d)、図1(c)の丸円
内に示す拡大図)。
(4) Due to the processing in the above step (3), a circular crater-shaped depression (recess) is formed on the back surface 2 of the wafer substrate.
4 was formed. The silicon was melted by the heat due to the absorption of the laser beam, the central portion was dented and the melt was pushed to the peripheral portion, and the peripheral portion was formed with a portion (convex portion) 5 protruding from the back surface of the wafer 1 ( FIG. 2 (d), FIG. 1 (c)
(Enlarged view shown in a circle). Hereinafter, the concavo-convex portion formed of the combination of the concave portion 4 and the convex portion 5 is referred to as an irradiation trace. The average uneven shape was as follows: the diameter: L was 60 μm, the depth of the concave portion from the wafer surface: D was 5 μm, and the height of the peripheral convex portion: H was 3 μm. The cross-sectional shape of the concave portion is substantially V
A letter-shaped shape was obtained (the enlarged view shown in the circles of FIGS. 2D and 1C).

【0026】図3は、上述した方法を用いて凹凸を形成
したICチップ裏面の概略図である。図3において、1
はSi基板から成るICチップであり、チップ1の裏面
2にはクレータ状の凹凸が隣接して多数形成されてい
る。凹凸形成領域6は、EEPROMを形成したチップ
表面位置に対応する裏面で、約2×3mm2の面積一面
とした。凹部(V字型の窪み部分)4は、約60μm間
隔に隣接して最密構造となるように配置した。
FIG. 3 is a schematic view of the back surface of an IC chip on which concavities and convexities have been formed using the method described above. In FIG. 3, 1
Is an IC chip made of a Si substrate, and a large number of crater-shaped irregularities are formed adjacently on the back surface 2 of the chip 1. The concavo-convex formation region 6 is a back surface corresponding to the chip surface position on which the EEPROM is formed, and has a surface area of about 2 × 3 mm 2 . The concave portions (V-shaped concave portions) 4 were arranged adjacent to each other at intervals of about 60 μm so as to have a close-packed structure.

【0027】半導体装置の一例であるICカードの製造
においては、上記工程によって得られたICチップをガ
ラスエポキシ基板上にチップ表面を下にしてフリップチ
ップ技術により実装する。さらに露出したチップ裏面の
上からエポキシ系樹脂を塗布して保護し、チップ全体を
塩化ビニル樹脂からなるカード基材で被覆してICカー
ドに完成させた。
In the manufacture of an IC card, which is an example of a semiconductor device, the IC chip obtained by the above process is mounted on a glass epoxy substrate by flip chip technology with the chip surface facing down. Further, the exposed chip back surface was coated with an epoxy resin to protect the chip, and the entire chip was covered with a card base material made of vinyl chloride resin to complete an IC card.

【0028】このような工程により作製されたICカー
ドの情報は、次のような手順で不正に解析される。ま
ず、加熱した発煙硝酸でICカード表面の塩化ビニール
の一部およびエポキシ樹脂からなる基材を溶解してIC
チップの裏面を露出させる。従来技術では、この段階で
波長1.15μmのHe−Neレーザの赤外光を直径1
μm以下に集光させてチップ裏面を走査し、反射光をホ
トダイオードで検出する顕微鏡でチップ裏面を観察す
る。これによりチップ表面近傍のトランジスタ回路や第
1層配線を観察することができる。しかしながら、本発
明に係る凹凸形状を有するICカードの場合、エネルギ
ービーム照射によってチップの裏面には、該裏面側から
入射した光の乱反射を促す、該基板の表面とは非平行な
面から構成された窪み及び突起の集合体からなる凹凸形
状が形成されているため、チップ表面近傍の回路パタン
からの反射光は著しく歪められて正確な観察像が得られ
ない。従って、本発明に係る凹凸形状を有する半導体装
置(例えばICカード)では、該半導体装置を構成する
集積回路パターンの解読や記憶情報の改竄等の不法行為
を容易に防ぐことができる。
The information of the IC card manufactured by such a process is illegally analyzed by the following procedure. First, a part of the vinyl chloride on the surface of the IC card and the base material made of epoxy resin are dissolved with heated fuming nitric acid,
Expose the back of the chip. In the prior art, at this stage, infrared light of a He-Ne laser having a wavelength of
The back surface of the chip is scanned by condensing light to a size of not more than μm, and the back surface of the chip is observed with a microscope that detects reflected light with a photodiode. Thereby, the transistor circuit and the first layer wiring near the chip surface can be observed. However, in the case of the IC card having the uneven shape according to the present invention, the back surface of the chip is irradiated with an energy beam, and is formed of a surface that is non-parallel to the surface of the substrate, which promotes irregular reflection of light incident from the back surface side. Due to the formation of the concavo-convex shape formed by the aggregate of the depressions and projections, the reflected light from the circuit pattern near the chip surface is significantly distorted, and an accurate observation image cannot be obtained. Therefore, in the semiconductor device having an uneven shape (for example, an IC card) according to the present invention, illegal acts such as decoding of an integrated circuit pattern constituting the semiconductor device and falsification of stored information can be easily prevented.

【0029】上記の実施形態では、エネルギービームと
して集光性レーザビームを用いたが、クレータ状の窪み
が形成できるのもであれば他のエネルギービームでもよ
い。具体的には、例えば電子ビーム、イオンビーム等が
挙げられる。その一例として、電子ビームを用いて光を
乱反射させるための凹凸を形成する場合について述べ
る。タングステンヘアピン型熱電子放出源を用いて加熱
状態のまま静電界で電子ビームを引き出し、30kVで
加速してビーム電流100μA、ビーム径1μmとし
た。このビームをICチップ裏面上で電子計算機制御で
走査することにより、電子ビームの加熱効果に基づきシ
リコン基板表面の一部を溶融して溝を形成した。計算機
上の描画データの調整により、深さ2μm、幅4μmの
溝が得られた。溝を4μmの周期間隔で配置することに
より、ウェハ裏面に概ねストライプ状の凹凸構造が一面
に形成可能であった。
In the above embodiment, a condensing laser beam is used as an energy beam. However, any other energy beam may be used as long as a crater-like depression can be formed. Specific examples include an electron beam and an ion beam. As an example, a case where unevenness for irregularly reflecting light is formed using an electron beam will be described. Using a tungsten hairpin type thermoelectron emission source, an electron beam was extracted with an electrostatic field while being heated, accelerated at 30 kV, and set to a beam current of 100 μA and a beam diameter of 1 μm. By scanning this beam on the back surface of the IC chip under computer control, a part of the surface of the silicon substrate was melted based on the heating effect of the electron beam to form a groove. By adjusting the drawing data on the computer, a groove having a depth of 2 μm and a width of 4 μm was obtained. By arranging the grooves at a periodic interval of 4 μm, a substantially striped uneven structure could be formed on one surface of the back surface of the wafer.

【0030】集光性レーザビームを用いる方法では、光
の乱反射や散乱性の高いV字型の窪みを容易に形成でき
る利点がある。また、レーザビームによる溶融物は周辺
部に押しやられて突起を形成するので、光の乱反射の効
率はさらによくなる。一般にシリコン基板は赤外光及び
可視光の吸収性が高いことから、エネルギービームとし
て集光性のレーザビームを用いることによりシリコンの
光吸収に起因した溶融が生じ易い利点がある。さらに、
スパッタリング現象を利用してないので、飛散するダス
トの悪影響は少ない。
The method using a condensing laser beam has an advantage that a V-shaped recess having high irregular reflection and scattering of light can be easily formed. Further, since the melt by the laser beam is pushed to the periphery to form a projection, the efficiency of irregular reflection of light is further improved. In general, since a silicon substrate has high absorption of infrared light and visible light, there is an advantage that melting due to light absorption of silicon is easily caused by using a condensing laser beam as an energy beam. further,
Since the sputtering phenomenon is not used, the adverse effect of the scattered dust is small.

【0031】また、上述した照射痕跡は円形のクレータ
状のまま配置するのみならず、連続的に繋げて溝状に
し、これを近接してストライプ状に多数配置しても良
い。さらに、1μm以下の微細な直径のビームを用いる
場合には、浅いものから深いものまで多数の痕跡をつな
げて幅数μmの略V字型の溝を形成する等、種々のバリ
エーション又はその組合せとしても構わない。
In addition, the above-mentioned irradiation traces may be arranged not only in the form of a circular crater but also in a continuous groove-like manner, and may be arranged in the form of stripes in close proximity. Furthermore, when a beam with a fine diameter of 1 μm or less is used, various variations or combinations thereof, such as forming a substantially V-shaped groove having a width of several μm by connecting a number of traces from a shallow to a deep one, etc. No problem.

【0032】さらに、上記2つの実施形態では、チップ
状に切断したあとに裏面にビーム加工を施したが、切断
前のウエハ状のままビーム加工を施しても良いことは言
うまでもない。
Further, in the above two embodiments, beam processing is performed on the back surface after cutting into chips, but it is needless to say that beam processing may be performed with the wafer shape before cutting.

【0033】本発明では、基板の裏面に、該裏面側から
入射した光の乱反射を促す、該基板の表面とは非平行な
面から構成された窪み及び突起の集合体からなる凹凸形
状を設けたが、この窪みを略V字型とすることで、光を
効率よく乱反射することができるので最も好ましい形態
である。
According to the present invention, on the back surface of the substrate, there is provided a concave-convex shape formed of an aggregate of depressions and projections formed of a surface non-parallel to the front surface of the substrate, which promotes irregular reflection of light incident from the rear surface side. However, it is the most preferable form that the recess is formed in a substantially V shape because light can be efficiently diffused and reflected efficiently.

【0034】なお、上記の実施の形態では、シリコン基
板を用いた例を取り上げたが、基板はシリコンに限定さ
れるものではない。すなわち、特定の波長の観察用光線
に対して基板の透明性が高くなり、かつ基板裏面の凹凸
によりこれらの光線の乱反射や散乱を高めることができ
れば、本発明を適用することができる。従って、種々の
化合物半導体にも本発明を適用し得ることは言うまでも
ない。
In the above embodiment, an example using a silicon substrate has been described, but the substrate is not limited to silicon. That is, the present invention can be applied as long as the transparency of the substrate is increased with respect to the observation light beam having a specific wavelength, and irregular reflection and scattering of these light beams can be enhanced by unevenness on the back surface of the substrate. Therefore, it is needless to say that the present invention can be applied to various compound semiconductors.

【0035】[0035]

【発明の効果】以上説明したように、請求項1に係る発
明によれば、基板の裏面側から赤外光を照射しても、該
裏面側から入射した光は乱反射されるので、該基板の裏
面側では、該基板の表面上に配設された集積回路からの
反射光が乱された形でしか得られない半導体装置が得ら
れる、その結果、基板の表面上に配設された集積回路パ
ターンの解読や記憶情報の改竄等の不法行為を防ぐこと
が可能となる。
As described above, according to the first aspect of the present invention, even if infrared light is irradiated from the back side of the substrate, the light incident from the back side is irregularly reflected. On the back side of the substrate, a semiconductor device is obtained in which the reflected light from the integrated circuit disposed on the front surface of the substrate can be obtained only in a disturbed form. As a result, the integrated device disposed on the front surface of the substrate is obtained. It is possible to prevent illegal acts such as decoding of circuit patterns and falsification of stored information.

【0036】請求項2に係る発明によれば、前記窪みの
断面形状を略V字型とすることによって、基板の裏面側
から入射した光の乱反射を最も効果的に発生させること
ができる。
According to the second aspect of the present invention, by making the cross-sectional shape of the dent substantially V-shaped, diffuse reflection of light incident from the back side of the substrate can be generated most effectively.

【0037】請求項3に係る発明によれば、基板の裏面
に窪みを形成すると共に、該窪みから移動した物質が該
窪みの周辺部に堆積されて突起も形成することができ
る。従って、本発明によれば、該基板の表面とは非平行
な面から構成された窪み及び突起の集合体を、該基板の
裏面に効率的に形成することが可能である。
According to the third aspect of the present invention, a dent can be formed on the back surface of the substrate, and a substance transferred from the dent can be deposited around the dent to form a projection. Therefore, according to the present invention, it is possible to efficiently form an aggregate of depressions and projections formed of a surface that is not parallel to the surface of the substrate on the back surface of the substrate.

【0038】請求項4に係る発明によれば、光の乱反射
や散乱性の高いV字型の窪みを容易に形成できる。ま
た、スパッタリング現象を利用していないので、飛散す
るダストの悪影響がほとんど生じない。
According to the fourth aspect of the present invention, it is possible to easily form a V-shaped recess having a high degree of irregular reflection and scattering of light. Further, since the sputtering phenomenon is not used, the adverse effect of the scattered dust hardly occurs.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に係る半導体装置の製造工程を示す模式
的な断面図である。
FIG. 1 is a schematic sectional view showing a manufacturing process of a semiconductor device according to the present invention.

【図2】レーザビームの照射回数と得られた窪み及び突
起の形状を示す模式的な断面図である。
FIG. 2 is a schematic cross-sectional view showing the number of laser beam irradiations and the shapes of the obtained dents and protrusions.

【図3】本発明に係る方法を用いて窪み及び突起を形成
したICチップ裏面の概略図である。
FIG. 3 is a schematic view of the back surface of an IC chip in which a depression and a projection are formed by using the method according to the present invention.

【図4】従来の機械的な研削法を用いて、乱反射面を表
面に設けた基板の模式的な鳥瞰図である。
FIG. 4 is a schematic bird's-eye view of a substrate provided with a diffuse reflection surface on the surface using a conventional mechanical grinding method.

【図5】従来の化学的なエッチング法を用いて、基板の
裏面に乱反射面を形成する工程を示した模式的な断面図
である。
FIG. 5 is a schematic cross-sectional view showing a step of forming a diffuse reflection surface on the back surface of a substrate by using a conventional chemical etching method.

【符号の説明】[Explanation of symbols]

1 基板、 2 基板の裏面、 3 レーザビーム、 4 窪み(凹部)、 5 盛り上がった部分(凸部)、 6 凹凸形成領域、 11 ガラス基板、 12 乱反射面、 21 シリコンウェハ、 22 SiO2膜、 23 SiO2パタン、 24 エッチング底面、 25 略V字型の谷、 26 開口部、 27 SiO2パタン23を除去した後に残存する平坦
部。
Reference Signs List 1 substrate, 2 back surface of substrate, 3 laser beam, 4 dent (concave portion), 5 raised portion (convex portion), 6 irregularity forming region, 11 glass substrate, 12 diffuse reflection surface, 21 silicon wafer, 22 SiO 2 film, 23 SiO 2 pattern, 24 etched bottom, 25 substantially V-shaped valley, 26 opening, 27 flat portion remaining after removing SiO 2 pattern 23.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 小川 重男 東京都新宿区西新宿三丁目19番2号日本電 信電話株式会社内 (72)発明者 前田 正彦 東京都新宿区西新宿三丁目19番2号日本電 信電話株式会社内 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Shigeo Ogawa 3-19-2 Nishi Shinjuku, Shinjuku-ku, Tokyo Nippon Telegraph and Telephone Corporation (72) Inventor Masahiko Maeda 3-19, Nishishinjuku, Shinjuku-ku, Tokyo 2 Nippon Telegraph and Telephone Corporation

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 基板の表面上に集積回路が配設された半
導体装置において、該基板の裏面に、該裏面側から入射
した光の乱反射を促す、該基板の表面とは非平行な面か
ら構成された窪み及び突起の集合体を設けたことを特徴
とする半導体装置。
1. A semiconductor device having an integrated circuit disposed on a surface of a substrate, the surface of the substrate having a surface non-parallel to the surface of the substrate for promoting irregular reflection of light incident from the rear surface. A semiconductor device provided with an aggregate of the formed depressions and projections.
【請求項2】 前記窪みの断面形状が、略V字型である
ことを特徴とする請求項1に記載の半導体装置。
2. The semiconductor device according to claim 1, wherein the recess has a substantially V-shaped cross section.
【請求項3】 基板の表面上に集積回路を有し、該基板
の裏面上に、該裏面側から入射した光の乱反射を促す、
該基板の表面とは非平行な面から構成された窪み及び突
起の集合体を設けた半導体装置の製造方法において、 前記窪み及び突起は、集束したエネルギービームを前記
基板の裏面の多数点に照射して形成することを特徴とす
る半導体装置の製造方法。
3. An integrated circuit is provided on a front surface of the substrate, and diffused reflection of light incident from the rear surface side is promoted on the back surface of the substrate.
In a method for manufacturing a semiconductor device provided with an aggregate of dents and projections formed of a plane not parallel to the surface of the substrate, the dents and projections irradiate a focused energy beam to a plurality of points on the back surface of the substrate. A method for manufacturing a semiconductor device, comprising:
【請求項4】 前記エネルギービームが、集光性レーザ
ビームであることを特徴とする請求項3に記載の半導体
装置の製造方法。
4. The method according to claim 3, wherein the energy beam is a converging laser beam.
JP9324173A 1997-11-26 1997-11-26 Semiconductor device and manufacture thereof Pending JPH11163261A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9324173A JPH11163261A (en) 1997-11-26 1997-11-26 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9324173A JPH11163261A (en) 1997-11-26 1997-11-26 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH11163261A true JPH11163261A (en) 1999-06-18

Family

ID=18162917

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9324173A Pending JPH11163261A (en) 1997-11-26 1997-11-26 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH11163261A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002189000A (en) * 2000-10-10 2002-07-05 Nec Corp Semiconductor device, method of evaluating and analyzing semiconductor device, and working device for semiconductor device
JP2017063146A (en) * 2015-09-25 2017-03-30 パナソニックIpマネジメント株式会社 Transformer device and manufacturing method for the same
WO2018179718A1 (en) * 2017-03-29 2018-10-04 日本ピラー工業株式会社 Coating base material

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002189000A (en) * 2000-10-10 2002-07-05 Nec Corp Semiconductor device, method of evaluating and analyzing semiconductor device, and working device for semiconductor device
JP2017063146A (en) * 2015-09-25 2017-03-30 パナソニックIpマネジメント株式会社 Transformer device and manufacturing method for the same
WO2018179718A1 (en) * 2017-03-29 2018-10-04 日本ピラー工業株式会社 Coating base material
JP2018167287A (en) * 2017-03-29 2018-11-01 日本ピラー工業株式会社 Coating substrate
US10792888B2 (en) 2017-03-29 2020-10-06 Nippon Pillar Packing Co., Ltd. Coating base material

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