JPH11163174A - Nonvolatile semiconductor storage device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device, which has improved drain disturbance characteristics, and a method of manufacturing the device. SOLUTION: A nonvolatile semiconductor storage device is provided with a laminated gate part 10 formed by laminating a tunnel insulting film 2, a floating gate electrode 3, a capacitor insulating film 4 and a controller gate electrode 5 on a p-type substrate 1. An n<++> arsenic-containing drain layer 26a, an n<++> source layer 26b, an n<+> drain layer 22 and an n<+> source layer 20 are provided in the substrate 1. Moreover, an n<-> layer 23 which contains phosphorus and overlaps with the end part extending along the widthwise direction of the gate part 10 as a whole, and a p-type layer 24 which encircles the layer 22 and the bottom of the layer 23, are provided on the side of a drain in the substrate 1. With this structure of the nonvolatile semiconductor storage device, an electric field which is applied between the electrode 3 and the drain is relaxed at the time of a write operation, and the drain disturbance characteristics of the device are enhanced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a nonvolatile semiconductor memory device having a floating gate electrode and a method of manufacturing the same, and more particularly to a measure for improving drain disturb characteristics.

[0002]

2. Description of the Related Art Conventionally, a nonvolatile semiconductor memory device having a memory cell structure including a memory cell transistor having a floating gate electrode is disclosed in
No. 134377 and a paper (Process and
Device Technologies For
16Mbit EPROMs with LargeT
ilt Angle Implanted P-Poc
Ket cell) (pp. 95-9 of IEDM90)
As disclosed in 8), there is known one that achieves high integration.

FIG. 16A is a cross-sectional view showing a memory cell structure of a nonvolatile semiconductor memory device described in the above article. As shown in FIG.
A gate oxide film 102 also functioning as a tunnel insulating film, a floating gate electrode 103 formed of a polysilicon film, a capacitance insulating film 104 formed of an ONO film, and a polysilicon film And a control gate electrode 105 formed from the same. The protective insulating film 106 is provided on the stacked gate portion 110. p
In the type Si substrate 101, a drain n ++ layer 126a (n ++ deep drain) and a source n ++ layer 126b containing a high concentration of arsenic (As), and a drain n + layer 123 containing a low concentration of arsenic (Shallow drain) and p-pockets 124a and 124b containing phosphorus (P) and functioning as punch-through stoppers are provided.

FIG. 16B is a flow chart showing a manufacturing process of the nonvolatile semiconductor memory device. First, after forming the stacked gate portion 110, arsenic (As) ions are implanted for forming a shallow drain (drain n + layer 123). Next, boron (B) ions for forming p-pockets 124a and 124b are implanted by a large tilt ion implantation method. Then, after forming a peripheral transistor, an n ++ deep drain (drain n ++ layer 12
6a) Arsenic (As) ions are implanted for formation, followed by activation of impurities in each region by heat treatment. Thereafter, ion implantation of a low-concentration n-type impurity for forming an LDD region of the peripheral transistor is performed. In addition,
Although not shown in FIG.
On the side surface of the insulator 10, an insulator sidewall indicated by a broken line in FIG. 16A is formed, and ion implantation for forming a deep drain is performed using the stacked gate portion 110 and the insulator sidewall as a mask. Seem.

Next, the operation of the conventional nonvolatile semiconductor memory device will be described.

Writing is performed on the control gate electrode 10.
5 is applied to the drain n ++ layer 126.
A voltage of about 5 V is applied to a to generate channel hot electrons near the junction between the p − pocket 124a and the n + layer 123, and the channel hot electrons are injected into the floating gate electrode 103 and accumulated. For erasing, a voltage of about 12 V is applied to the source n ++ layer 126b,
By Fowler-Nordheim (FN) current,
Electrons stored in the floating gate electrode 103 are extracted. Reading is performed using the control gate electrode 10.
5 is applied to the drain n ++ layer 126a.
A voltage of about V is applied, and the amount of accumulated electrons in the floating gate electrode 103 is detected based on the magnitude of the drain current. When a large amount of electrons are accumulated in the floating gate electrode 103, almost no drain current flows,
When electrons are hardly accumulated in the floating gate electrode 103, a sufficient drain current flows. The stored information is read based on the difference in the magnitude of the drain current.

In such a nonvolatile semiconductor memory device,
It is known that the steeper the pn junction between the p- pocket 124a and the drain n + layer 123, the more hot electrons are generated during writing. And p-
The pockets 124a and 124b can surely prevent punch-through, so that a fine memory cell structure having a gate length of about 0.4 μm is to be realized.

[0008]

However, the nonvolatile semiconductor memory device having a memory cell structure having a shallow drain as described in the above-mentioned conventional paper has the following problems.

In a write operation to a memory cell, in a non-selected memory cell which is not a selected memory cell but is connected to a selected bit line common to a selected memory cell, that is, a non-selected memory cell, a drain of 5 V is applied to a drain. A voltage of 0 V is applied to the gate electrode. Here, when electrons are injected into the floating gate electrode, the potential of the floating gate electrode is -2 V
Therefore, a considerable electric field is generated between the floating gate electrode and the drain. In the vicinity of the drain, GIDL (Gate Induced)
A pair of electrons and holes called “DrainLakage Current” is generated, and the holes are pulled by the electric field and enter the gate oxide film (hot hole trap). Alternatively, it reaches near the floating gate electrode. The accumulation of holes in the gate oxide film causes the following two problems.

First, since the accumulation of electrons in the floating gate electrode is reduced, the threshold voltage of a non-selected memory cell transistor during a write operation varies (drain disturb), and erroneous writing may occur. .

The above-described fluctuation of the threshold voltage tends to occur when a high voltage is applied between the floating gate electrode and the drain of the memory cell for a long time. Here, the number of memory cells connected to one bit line increases as the integration degree of the nonvolatile semiconductor memory device increases. For example, in a 1 megabit memory cell array, 1024 memory cells are connected to a common bit line. Therefore, during the write operation, the time during which a high voltage is applied between the floating gate electrode and the drain of one memory cell is 1 second or more, and this time will continue in accordance with the high integration of the nonvolatile semiconductor memory device. Tend to be longer. In other words, for high integration of the nonvolatile semiconductor memory device, it is essential to improve drain disturb characteristics.

Second, since the film quality of the gate oxide film is degraded due to the accumulation of holes, there is a problem that the reliability is also lowered.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to prevent penetration and accumulation of holes into a gate oxide film in a nonvolatile semiconductor memory device having a floating gate electrode in a memory cell. Measures to improve drain disturb characteristics,
Accordingly, it is an object of the present invention to improve the integration and reliability of a nonvolatile semiconductor memory device.

[0014]

According to the present invention, there is provided a nonvolatile semiconductor memory device comprising a semiconductor substrate of a first conductivity type, and a tunnel insulating film, a floating gate electrode, a capacitor insulating film, and a control gate electrode formed on the semiconductor substrate in this order. A stacked gate portion provided by stacking; a second conductivity type source region and a drain region provided in an element formation region on the surface of the semiconductor substrate with the stacked gate portion interposed therebetween; and a drain of the second conductivity type A first conductivity type region surrounding the bottom of the region;
A function of writing by applying a voltage between the drain and the source to generate hot carriers,
The drain region includes a first diffusion layer containing a second impurity of a first conductivity type and a second diffusion layer containing a second impurity of a second conductivity type having a greater range during ion implantation than the first impurity. At least the second diffusion layer.
In the plan view, the diffusion layer overlaps the entire end of the stacked gate portion along the gate width direction in the element formation region.

Thus, the drain region has at least 2
And a first diffusion layer containing impurities of the second conductivity type. At least a second diffusion layer of the first and second diffusion layers is stacked over the entire gate width direction of the stacked gate portion on the element formation region. It overlaps with the gate. Therefore, the drain region has a sharp p-type between the drain region and the first conductivity type region.
While the n-junction is formed, a portion where the drain region does not overlap with the floating gate electrode can be eliminated. Therefore, the drain disturb characteristic can be improved without lowering the writing speed and increasing the short channel effect, and the reliability and the integration can be improved.

In the nonvolatile semiconductor memory device, the first impurity is arsenic and the second impurity is phosphorus, so that the range and diffusion coefficient of phosphorus are larger than the range and diffusion coefficient of arsenic. By utilizing this, the above effects can be effectively exhibited.

In the nonvolatile semiconductor memory device, it is preferable that the source region is constituted only by a region of the second conductivity type.

In the nonvolatile semiconductor memory device, it is preferable that the diffusion coefficient of the second impurity in the heat treatment for activating the impurity is larger than the diffusion coefficient of the first impurity.

According to the method of manufacturing a nonvolatile semiconductor memory device of the present invention, a tunnel insulating film,
A first method of forming a stacked gate portion by sequentially stacking a floating gate electrode, a capacitor insulating film, and a control gate electrode;
A second step of forming a source region and a drain region of a second conductivity type in the element formation region on the surface of the semiconductor substrate with the stacked gate portion interposed therebetween; and a bottom portion of the drain region of the second conductivity type Forming a first conductivity type region so as to cover the first conductive type region, and in the second step, heat treatment is performed by ion-implanting at least two types of second conductive type impurities having different ranges. Thereby, at least two types of diffusion layers of the second conductivity type are formed, and the diffusion layer containing the impurity having the larger range is formed in plan view.
This is a method in which an end of the stacked gate portion along the gate width direction on the element formation region is entirely overlapped.

According to this method, a nonvolatile semiconductor memory device exhibiting the above effects can be easily formed.

In the method of manufacturing a nonvolatile semiconductor memory device, in the second step, the dose of impurity ions having a larger range is set smaller than that of impurity ions having a smaller range. Is preferred.

In the method of manufacturing a nonvolatile semiconductor memory device, in the second step, ion implantation of at least one of the at least two types of impurities of the second conductivity type is performed by using By performing the step immediately after the formation, the second diffusion layer in the drain region can be formed to the inner side of the stacked gate portion.

In the method of manufacturing a nonvolatile semiconductor memory device, in the third step, the ion implantation of the first conductivity type impurity for forming the first conductivity type region may be performed also in the lower region of the stacked gate portion. By using the large-angle ion implantation performed from a direction having an angle of 20 degrees or more with respect to the normal direction of the semiconductor substrate so as to be implanted, the first conductivity type region is formed under the stacked gate portion under the second conductivity type. It is easy to form so as to cover the bottom of the drain region.

In the method for manufacturing a nonvolatile semiconductor memory device, it is preferable that the impurity having the larger range has a larger diffusion coefficient in the heat treatment for activating the impurity than the impurity having the smaller range.

[0025]

(First Embodiment) A first embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view showing the configuration of the nonvolatile semiconductor memory device according to the present embodiment. FIGS. 2A to 2C and 3A to 3C show the nonvolatile semiconductor memory device according to the present embodiment. FIG. 14 is a cross-sectional view showing a manufacturing step of the semiconductor memory device.

As shown in FIG. 1, the nonvolatile semiconductor memory device according to this embodiment has a first conductivity type of B (boron).
A tunnel insulating film 2 formed of a silicon oxide film, a floating gate electrode 3 formed of a polysilicon film, a capacitance insulating film 4 formed of an ONO film, A control gate electrode 5 formed of a silicon film and also functioning as a word line is provided in a laminated gate portion 10 which is sequentially laminated. An insulator sidewall 25 formed of a silicon oxide film is provided on a side surface of the entire stacked gate unit 10. In the p-type Si substrate 1, a region located on the side of the insulator sidewall 25 includes a drain n ++ layer 26a containing a high concentration of arsenic and a source n ++ layer 26b.
And a drain n.sup. + Layer 22 and a source n.sup. + Layer 20 which contain arsenic at a relatively high concentration and are formed to surround the bottoms of the drain n.sup. ++ layer 26a and the source n.sup. ++ layer 26b, respectively. Then, on the source side of the p-type Si substrate 1,
A source n- layer 21 containing P (phosphorus) and surrounding the bottom of the source n + layer 20 is provided.
On the drain side of the type Si substrate 1, a drain n− layer 23 containing P (phosphorus) and formed at a position overlapping the stacked gate portion 10 on the inner side of the drain n + layer 22, and a drain n + layer 22 and a p layer 24 formed so as to surround the bottom of the drain n− layer 23.

That is, the first feature of the nonvolatile semiconductor memory device according to the present embodiment is that the drain region has a drain n ++ layer 26a containing arsenic as a second conductivity type impurity and a drain n + containing arsenic. A layer 22 and a drain n− layer 23 containing phosphorus, which is a second conductivity type impurity having a greater diffusion range during ion implantation and a larger diffusion coefficient than arsenic during heat treatment.
This is the point that is constituted. That is, the point that the drain n− layer 23 is provided is greatly different from the memory cell structure of the nonvolatile semiconductor memory device described in the figure in the above-mentioned article. The drain n− layer 23
An end along the width direction (a direction orthogonal to the cross section shown in FIG. 1) of the stacked gate portion 10 on the element formation region separated by the LOCOS separation film (not shown) overlaps the whole. I have. Further, the second feature of the nonvolatile semiconductor memory device according to the present embodiment is that p
The point is that the layer 24 is provided, and the source region is not provided with a p-type diffusion layer corresponding to the p-pocket 124b described in the figure in the above-mentioned article.

A gate bird's beak 7 is formed at the ridge of the floating gate electrode 3 adjacent to the source region and the drain region by oxidation of the polysilicon film, so that the ridge of the floating gate electrode 3 is chamfered. It is in a state of being left.

Next, a method of manufacturing the nonvolatile semiconductor memory device shown in FIG. 1 will be described with reference to FIGS.
This will be described with reference to (a) to (c).

First, in the step shown in FIG.
Although not shown, a p-well and a LOCOS isolation film are formed on the substrate 1. Next, on the p-type Si substrate 1, a thickness of 1
A silicon oxide film having a thickness of about 0 nm, a first polysilicon film, an ONO film having a thickness of about 18 nm, and a second polysilicon film are sequentially formed. Then, the second polysilicon film, the ONO film, the first polysilicon film, and the silicon oxide film are sequentially patterned to form the control gate electrode 5.
, A capacitive insulating film 4, a floating gate electrode 3,
A stacked gate portion 10 including the tunnel insulating film 2 is formed.

Next, in the step shown in FIG. 2B, a thermal oxidation process is performed to form a protective oxide film 6 on the entire surface of the substrate.
At this time, the ridge portion on the lower end side of the floating gate electrode 3 is oxidized to form a gate bird's beak 7. The protective oxide film 6 prevents unnecessary contamination at the time of various ion implantations. Further, the gate bird's beak 7 formed at the same time causes the ridge portion of the floating gate electrode 3 to be chamfered, so that the electric field concentration at the gate end of the floating gate electrode 3 can be reduced.

Next, in a step shown in FIG. 2C, a resist film 8 covering substantially half of the laminated gate portion 10 and the drain side of the p-type Si substrate 1 and opening the source side of the p-type Si substrate 1 is formed. Is formed, ions of impurities are implanted into the source region of the p-type Si substrate 1 using the resist film 8 as a mask. First, the acceleration voltage is 30 to 80 keV, preferably 35
～60KeV, after forming the arsenic ion implanted layer 11 by performing implantation of arsenic ions (As +) at a dose of about 6 × 10 ¹⁵ cm ^-2, an acceleration voltage is 30~80keV preferably 35～60KeV, Dose amount is about 1.5 × 10 ¹⁵
implanting phosphorus ions (P +) under the condition of cm ^-2 ,
A phosphorus ion implanted layer 12 is formed. Although only the peak portions of the arsenic ion-implanted layer 11 and the phosphorus ion-implanted layer 12 are shown in the figure, in actuality, the arsenic ion-implanted layer 11 and the phosphorus ion-implanted layer 12 each have a wide range in the depth direction. It has spread.

Next, in the step shown in FIG.
Cover half of the gate portion 10 and the source side of the p-type Si substrate 1.
Film 1 having an opening on the drain side of a p-type Si substrate 1
3 is formed, and using this resist film 13 as a mask, p
Implantation of impurities into the drain region of the silicon substrate 1
Do. First, an acceleration voltage of 30 to 80 keV, preferably
35-60 keV, dose amount is about 5 × 10¹⁴cm^-2Article
Arsenic ion (As +) is implanted into the arsenic ion implanted layer
After forming 17, the accelerating voltage is preferably 30 to 80 keV.
35 to 60 keV, dose about 1 × 10¹⁴cm^-2
Phosphorus ion (P +) implantation under the conditions described above
The layer 18 is formed, and the accelerating voltage is 40 to 70 keV.
Preferably 45-60 keV, dose amount about 2.5 × 1
0¹³cm ^-2Implant boron ions (B +)
An ion implantation layer 19 is formed. In the figure, arsenic ion
Implanted layer 17, phosphorus ion implanted layer 18, and boron ion
Although only the peak portion of the injection layer 19 is shown, actually
Arsenic ion implantation layer 17, phosphorus ion implantation layer 18,
The ion implantation layer 19 extends over a wide range in the depth direction.
I have. Here, boron ions are implanted with a large tilt ion injection.
By the implantation method, the direction perpendicular to the main surface of the p-type Si substrate 1 is
From a direction inclined by 45 °.
The ion implantation layer 19 is overlapped with the stacked gate portion 10.
It can be formed up to the region to be dropped.

Next, in the step shown in FIG.
By performing the heat treatment at ℃, the arsenic ion-implanted layer 11,
The impurities in the phosphorus ion implanted layer 12, the arsenic ion implanted layer 17, the phosphorus ion implanted layer 18, and the boron ion implanted layer 19 are activated and diffused, and on the source side in the p-type Si substrate 1, the source n @ + layer 20 is formed. On the drain side, a drain n + layer 22, a drain n− layer 23, and a p layer 24 are formed. Here, due to this heat treatment, in the source region in the p-type Si substrate 1, the source n − layer 21 containing phosphorus having a large range and diffusion coefficient becomes a source n − layer containing arsenic having a small range and diffusion coefficient than phosphorus. surrounding the bottom of the n + layer 20,
Further, in a region near the surface of the p-type Si substrate 1, it is formed in a wide range so as to overlap with the laminated gate portion 10.

Here, the "range" means, for example, the distance from the surface of the substrate to the center of the distribution of the density of the implanted ions when the ions are implanted into the substrate. The range varies depending on the mass and the atomic radius. Further, the “diffusion coefficient” is a concept indicating the ease of spreading of particles, and the diffusion coefficient changes with the same impurity depending on the temperature, impurity concentration, and plane orientation. Here, when these parameters are shared, The magnitude of the diffusion coefficient is compared.

On the other hand, in the drain region in the p-type Si substrate 1, the drain n− layer 23 containing phosphorus having a larger range and diffusion coefficient has a drain n + containing arsenic having a smaller range and diffusion coefficient than phosphorus. The p-type Si substrate 1 is formed in a range wider than the layer 22 and in a region near the surface of the p-type Si substrate 1 so as to overlap the stacked gate portion 10. However, since the phosphorus ion-implanted layer 18 contains a relatively low concentration of phosphorus, the region behind the p-type Si substrate 1 is neutralized by boron of the boron ion-implanted layer 19.
Therefore, the drain n− layer 23 is formed only in the region near the surface of the p-type Si substrate 1 and
And are formed so as to overlap. Further, the p layer 24 containing boron which is implanted with relatively high energy and has a large diffusion coefficient includes the drain n + layer 22 and the drain n
-In a region surrounding the bottom of the layer 23 and near the surface of the p-type Si substrate 1, it is formed so as to enter the inside of the laminated gate portion 10 more than the drain n- layer 23.

Thereafter, in the step shown in FIG. 3C, a silicon oxide film is deposited on the entire surface of the substrate and then etched back to form an insulator sidewall 25 on the side surface of the laminated gate portion 10. I do. Thereafter, high concentration arsenic ions are implanted using the stacked gate portion 10 and the insulator sidewall 25 as a mask, and a drain n is formed in a region located on the side of the insulator sidewall 25 in the p-type Si substrate 1.
++ layer 26a and source n ++ layer 26b.

The feature of the method of manufacturing the nonvolatile semiconductor memory device according to this embodiment is that two types of ions (P +, As +) having different ranges and diffusion coefficients are used for forming each n-type layer in the drain region. That is the point. Note that the dose in the ion implantation of phosphorus having a large range and diffusion coefficient is set to be smaller than the dose in the ion implantation of arsenic having a small range and diffusion coefficient. This is to maintain a sharp pn junction between the drain n-type layer and the p layer 24. By adopting such a manufacturing process,
A planar structure and a cross-sectional structure of a memory cell as described below can be realized.

(Comparative Example to First Embodiment) Next,
In order to examine the effects obtained by the first embodiment, instead of providing the p-pockets 124a and 124b on the source side and the drain side in the structure of the memory cell of the nonvolatile semiconductor memory device described in the above article, As in the first embodiment, a comparative example in which a p-type layer is provided only on the drain side will be described.

FIGS. 12A to 12G are cross-sectional views showing the steps of manufacturing a nonvolatile semiconductor memory device according to a comparative example.

First, in the steps shown in FIGS. 12A to 12C, the same processes as those shown in FIGS. 2A to 2C in the first embodiment are performed. That is, after a stacked gate portion 10 including a tunnel insulating film 2, a floating gate electrode 3, a capacitor insulating film 4 and a control gate electrode 5 is formed on a p-type Si substrate 1, a protective oxide film 6 is formed on the entire surface of the substrate. Is formed, and an arsenic ion implantation layer 11 and a phosphorus ion implantation layer 12 are formed in the source region of the p-type Si substrate 1. The processing conditions at this time are the same as the conditions in the first embodiment.

Next, in the step shown in FIG.
Similarly to the process shown in FIG. 3A in the embodiment, the resist film 13 covering substantially half of the stacked gate portion 10 and the source side of the p-type Si substrate 1 and opening the drain side of the p-type Si substrate 1 is formed. After the formation, impurity ions are implanted into the drain region of the p-type Si substrate 1 using the resist film 13 as a mask. However, the arsenic ion implantation layer 17 and the boron ion implantation layer 19 are formed, but the phosphorus ion implantation layer 18 shown in FIG. 3A is not formed. Arsenic ion implanted layer 1
The ion implantation conditions for forming the 7 and boron ion implantation layers 19 are the same as those in the first embodiment.

Next, in the step shown in FIG.
By performing a heat treatment at a temperature of about 5 ° C., the impurities in the arsenic ion-implanted layer 11, the phosphorus ion-implanted layer 12, the arsenic ion-implanted layer 17, and the boron ion-implanted layer 19 are activated and diffused. And source n- layer 2
1 and a drain n + layer 22 and p
The layer 24 is formed. That is, the second embodiment differs from the first embodiment in that the drain n− layer does not exist.

Next, in the step shown in FIG. 12F, after the insulator sidewall 25 is formed, arsenic ions are implanted to form the drain n ++ layer 26a and the source n ++ layer 26.
and b.

(Comparison of First Embodiment and Comparative Example) FIG. 4
FIG. 2 is a plan view of a memory cell of the nonvolatile semiconductor memory device according to the first embodiment. FIGS. 5A and 5B
5 is a cross-sectional view taken along line Va-Va shown in FIG. 4 and a diagram showing changes in impurity types and concentrations along the gate length direction.
6 (a), 6 (b) and 6 (c) are cross-sectional views taken along the line VIa-VIa shown in FIG. 4, a diagram showing changes in impurity types and concentrations along the gate length direction, and hot spots at the drain end. It is a figure for demonstrating the accumulation | storage suppression effect of a hole.

FIG. 13 is a plan view of a memory cell of the nonvolatile semiconductor memory device according to the comparative example. FIG.
FIGS. 4A and 4B are a cross-sectional view taken along line XIVa-XIVa shown in FIG. 13 and a diagram showing types and concentrations of impurities. FIGS. 15A, 15B, and 15C show XVa-XVa shown in FIG.
FIG. 3 is a cross-sectional view taken along a line, a diagram showing types and concentrations of impurities along a gate length direction, and a diagram for explaining an action of suppressing accumulation and intrusion of hot holes at a drain end portion. FIG. 17A is a cross-sectional view showing a state of formation of an ion-implanted layer at the time of impurity ion implantation in the cross section taken along line XVIIa-XVIIa in FIG. 4, and FIG. 17B is an impurity diffusion region after activation processing in the same cross-section. It is a figure showing the state of formation of. FIG. 18A is a cross-sectional view showing a state of formation of an ion-implanted layer at the time of impurity ion implantation in a cross section taken along line XVIIIa-XVIIIa in FIG. 13, and FIG. 18B is an impurity diffusion region after activation processing in the same cross-section. It is a figure showing the state of formation of.

As shown in FIG. 13, in the drain region of the memory cell of the comparative example, the drain n + layer 22 and the LO
The point P at which the COS isolation film 27 intersects the control gate electrode 5 (floating gate electrode 3) as a word line
In the vicinity of t, the drain n + layer 22 formed by arsenic ion implantation does not extend below the floating gate electrode 3. This is for the following reason.

First, at the time of arsenic ion implantation, most of arsenic ions having a relatively small range are blocked by bird's beaks of the LOCOS film 27. On the other hand, boron ions have a larger range than arsenic, and therefore pass through the bird's beak of the LOCOS separation membrane 27. Therefore, as shown in FIG. 18A, in the cross section orthogonal to the gate length direction of the floating gate electrode 3, the boron ion implanted layer 19 has L
The arsenic ion-implanted layer 17 is formed in the region just below the bird's beak of the OCOS separation film 27.
It is not formed in a region of the OS isolation film 27 immediately below the bird's beak. Moreover, even in the heat treatment for activation,
The diffusion coefficient of arsenic is small. As a result, as shown in FIG. 18B, after the heat treatment for activating the impurities,
While the p layer 24 enters deeply below the LOCOS isolation film 27, the drain n + layer 22
7 does not enter below.

On the other hand, as shown in FIG. 4, in the drain region of the memory cell of the first embodiment, LOC
OS isolation film 27 and control gate 5 as word line
Is similar to the comparative example in that the drain n + layer 22 formed by arsenic ion implantation does not extend below the floating gate electrode 3 in the vicinity of the intersection Pt. It is formed sufficiently wide below the gate electrode 3. This is for the following reason.

When phosphorus ions are implanted, phosphorus ions whose range is larger than that of arsenic and smaller than that of boron are LOCOS
The portion of the film 27 where the bird's beak is thick is blocked by the bird's beak, but the portion where the bird's beak is thin passes through the bird's beak. Therefore, FIG.
As shown in (a), in the cross section orthogonal to the gate length direction of the floating gate electrode 3, the phosphorus ion implanted layer 18 is located immediately below the bird's beak thin film portion of the LOCOS isolation film 27, that is, the boron ion implanted layer 19 is formed. The arsenic ion implantation layer 17 is formed up to an intermediate position. Moreover, the diffusion coefficient of phosphorus is larger than that of arsenic.
As a result, as shown in FIG. 17B, after the heat treatment for activating the impurities, the drain n−
It is formed to penetrate below the COS separation film 27.

The difference in the structure as described above will be compared in detail with respect to the structure of the cross section of the floating gate electrode 3 along the gate length direction. In the memory cell of the comparative example, as shown in FIGS. 14A and 14B, in the cross section passing through the central portion of the drain, the drain n + layer 22
Extends to a region below the floating gate electrode 3. On the other hand, also in the memory cell of the first embodiment, as shown in FIGS. 5A and 5B, in the cross section passing through the central portion of the drain, the drain n + layer 22 is located below the floating gate electrode 3. It extends to the region and overlaps with the floating gate electrode 3 almost to the same extent as the drain n− layer 23. That is, at the central portion of the drain, the drain n− layer 23 is extremely narrow, so that the p layer 24 and the drain n + layer 22
Between them, a steep pn junction is formed as in the memory cell of the comparative example. Therefore, it can be seen that also in the memory cell of the first embodiment, sufficient channel hot electrons necessary for the write operation of the nonvolatile semiconductor memory device can be generated, and there is no possibility that the write operation is hindered.

On the other hand, in the cross section passing through the drain end (that is, near the intersection Pt), in the memory cell of the comparative example,
As shown in FIGS. 15A and 15B, the drain n + layer 2
2 does not extend to a region below the floating gate electrode 3 and does not overlap with the floating gate electrode 3 in plan view. As a result, the hot hole generation position due to the pn junction, that is, GIDL coincides with the gate end where the electric field is concentrated, and as shown in FIG. 15C, during the write operation, the unselected memory connected to the selected bit line Since the electric field applied between the floating gate electrode and the drain of the cell becomes as large as about 7 MV / cm, the generated hot holes penetrate into the inside of the tunnel insulating film 2 and the hot hole traps and the holes become floating gate electrodes 3. Is more likely to be reached. On the other hand, in the memory cell of the first embodiment, FIG.
As shown in (a) and (b), in the cross section passing through the drain end, the drain n + layer 22 does not extend to the region below the floating gate electrode 3, but
The layer 23 extends to the region below the floating gate electrode 3; As a result, as shown in FIG.
During a write operation, in a non-selected memory cell connected to a selected bit line, the position of a hot hole generated by a pn junction, ie, GIDL, and the gate end where an electric field is concentrated do not match. The electric field of the film is reduced to about 3 MV / cm.
Therefore, the probability that hot holes generated at the time of writing penetrate into the tunnel insulating film 2 is reduced. That is, even if a hot hole trap occurs in the tunnel insulating film 2, its position is limited to the surface of the tunnel insulating film 2. Although the above effects can be obtained by using impurity ions having a larger range than arsenic ions, the above effects can be more reliably achieved by using impurities such as phosphorus that have a large diffusion coefficient at the time of heat treatment as well as the range. Can be demonstrated.

It is conceivable that arsenic ions may pass through a part of the bird's beak by increasing the acceleration energy at the time of arsenic implantation. However, when the acceleration energy is large, the concentration peak of the drain n + layer 22 may be reduced. Therefore, the write operation to the floating gate electrode 3 is hindered, the basic performance of the nonvolatile semiconductor memory device is reduced, or arsenic having high acceleration energy is deposited on the protective oxide film. 6, the tunnel insulating film 2 may be damaged, or the characteristics of the LOCOS isolation film 27 may be deteriorated due to the fact that the drain n + layer 22 is located deep in the substrate.

FIG. 7 is a diagram showing drain disturb characteristics at the time of writing. In FIG. 7, the horizontal axis Time
Indicates a drain stress time in which a voltage of 0 V is applied to the word line and a voltage of 5 V is applied to the drain, and the threshold voltage on the vertical axis indicates that the drain voltage is 1.0 V and the gate voltage is increased. It is a gate voltage at which the drain current starts flowing more than a certain amount. Also, VTW and VTE shown on the vertical axis are the threshold voltage after writing and the threshold voltage after erasing of the nonvolatile semiconductor memory device, respectively. As can be seen from the drawing, in the nonvolatile semiconductor memory device according to the comparative example, when the drain stress time reaches about 10 seconds, the threshold voltage V
TW may approach the threshold voltage VTE after erasure, so that an erased memory cell may be determined to be in a written state, or a written memory cell may be determined to be in an erased state. On the other hand, in the nonvolatile semiconductor memory device according to the first embodiment, the drain stress time is 1
Until the time reaches about 00 seconds, there is no possibility of such erroneous determination. That is, according to the first embodiment, the drain stress time that can guarantee that the threshold voltage does not fluctuate is improved to about ten times that of the conventional nonvolatile semiconductor memory device. As described above, the drain disturb characteristic of the nonvolatile semiconductor memory device according to the first embodiment is significantly improved as compared with the drain disturb characteristic of the conventional nonvolatile semiconductor memory device.

The structure of the memory cell of the nonvolatile semiconductor memory device described in the article in IEDM 90 corresponds to the structure in which the source n − layer 21 in the source region of the comparative example is replaced with a p-type pocket layer. However, the structure in the drain region is basically the same as the structure of the memory cell according to the comparative example. Therefore, the drain disturb characteristic of the nonvolatile semiconductor memory device described in the above-mentioned paper can be considered to be substantially equivalent to that of the memory cell of the comparative example.

As described above, according to the nonvolatile semiconductor memory device of the first embodiment, in the cross section passing through the central portion of the drain of the memory cell, the drain n + -type layer 22 sufficiently overlaps with the floating gate electrode 3. However, since a sharp pn junction is formed with the p-layer 24, sufficient channel hot electrons are generated in the write operation of the nonvolatile semiconductor memory device, and the write speed is maintained at the same level as that of the conventional nonvolatile semiconductor memory device. Can be. on the other hand,
At the drain end, the drain n− layer 23 sufficiently overlaps with the floating gate electrode 3 in plan view, so that the floating gate electrode near the pn junction in the drain disturb state during the write operation is
The electric field applied between the drains is alleviated, and the drain disturbance at the time of writing can be improved as shown in FIG. That is, a highly reliable nonvolatile semiconductor memory device can be realized.

The drain n − layer 23 may be formed so as to sufficiently overlap the floating gate electrode 3 in the vicinity of the LOCOS isolation film 27, and there is no possibility that the short channel effect is promoted.

The following effects can be exhibited in the present invention by improving the drain disturb characteristic.

FIGS. 8A and 8B are plan views showing the structure of the memory cell array of the conventional nonvolatile semiconductor memory device and the structure of the memory cell array of the nonvolatile semiconductor memory device of the first embodiment, respectively. is there. Considering that the conventional memory cell structure has poor drain disturb characteristics, the memory cell array is divided into a plurality of blocks as shown in FIG. It is necessary to arrange an SA and perform a write operation for each block. This is because, if the number of memory cells connected to the common bit line is too large, the drain stress time becomes long, and the threshold voltage may fluctuate.

On the other hand, in the case of the memory cell array of the nonvolatile semiconductor memory device of the present invention, as shown in FIG. 8B, all the memory cells are arranged in a single block and each bit line is Need only be provided with one sense amplifier SA. This is because even if the number of memory cells connected to the common bit line is large and the drain stress time is long, there is almost no possibility that the threshold voltage will fluctuate. Of course, when the degree of integration is dramatically increased, it may be necessary to divide the memory cell array into a plurality of blocks. However, even in such a case, the number of blocks is reduced by one in comparison with the memory cell array of the conventional nonvolatile semiconductor memory device.
It can be reduced to about 1/0. Therefore, not only can the cost be reduced, but also the number of sense amplifiers for increasing the area can be reduced, whereby high integration of the nonvolatile semiconductor memory device can be achieved.

In order to obtain the effect of the first embodiment as described above, the concentration of phosphorus in the drain n − layer 23 shown in FIG. 1 must be 3 × 10 ¹⁸ to 1 × 10 ¹⁹ cm ^−2. preferable. Further, in order to obtain such an appropriate concentration range, in the ion implantation step shown in FIG. 3A, the dose of phosphorus ions is preferably 3 × 10 ¹³ to 1 × 10 ¹⁴ cm ⁻² . On the other hand, the boron concentration in the boron implanted layer 24 may be 1 × 10 ¹⁹ cm ⁻² or more, and the upper limit of the concentration varies depending on the structure and type of the memory cell transistor arranged in the nonvolatile semiconductor memory device. Any range may be used as long as the operation of the transistor can be held smoothly.

(Second Embodiment) In this embodiment, a method for testing a nonvolatile semiconductor memory device will be described. First
In the method of manufacturing the nonvolatile semiconductor memory device according to the embodiment, the drain n− layer 23 and the like of the drain are
May not overlap sufficiently. In such a case, hot hole traps are formed in the tunnel insulating film 2, causing a problem that the drain disturb characteristic deteriorates and the amount of electrons of the floating gate electrode 3 fluctuates. In that case, FIG.
A defective nonvolatile semiconductor memory device (memory cell) can be detected by the methods shown in FIGS.
However, such an inspection method is not necessarily established based on the nonvolatile semiconductor memory device having the configuration of the present invention, and is applicable to all nonvolatile semiconductor memory devices having memory cells having floating gate electrodes. It is.

FIG. 9A is a diagram schematically showing the structure of a memory cell array. In the memory cell array, for example, memory cells having the structure as in the first embodiment are arranged in a matrix. I have. At the time of inspection, after all the memory cells arranged in the NOR type are set in an erased state in advance, the read current of all the memory cells is detected. The word line 29 includes a plurality of nonvolatile semiconductor memory devices (memory cells).
, And each drain n ++ layer 26a of a plurality of nonvolatile semiconductor memory devices (memory cells) is connected to the bit line 30. Note that the configuration of the NOR-type memory cells is such that a plurality of word lines 29 and a plurality of bit lines 30 are arranged in a lattice,
One memory cell is arranged at each intersection.

Next, as shown in FIG. 9B, a voltage sufficient to generate hot holes in the drain, for example, a voltage of 5 V is applied to all the bit lines 30 for a predetermined time. In this state, since no electrons are stored in the floating gate electrode 3, the electric field applied between the floating gate electrode and the drain is relatively small. Therefore, a hot hole trap as shown in FIG. 9C occurs only in the defective memory cell.

Thereafter, as shown in FIG. 9D, a constant high voltage, for example, a voltage of 8 V is applied to all the word lines 29 for a predetermined time, and then the read current of all the memory cells arranged in the NOR type is reduced. Detect. At this time, a hot hole trap is formed in the tunnel insulating film in a memory cell showing a read current different from the read current when the erase state is already measured. As a result, the detected defective memory cell is replaced with a redundant cell, or the entire storage device is determined to be defective. As shown in FIG. 9E, in the defective memory cell, since a trap of positive charges is formed in the tunnel insulating film near the drain or on the surface of the tunnel insulating film, the potential in the tunnel insulating film decreases. Then, electrons are injected into the floating gate electrode 3 through the trap, and the state of the memory cell changes.

According to the present embodiment, it is possible to quickly and electrically find a memory cell in which drain disturb is particularly likely to occur due to adhesion of dust, generation of defects, and the like during the manufacturing process. In particular, in the nonvolatile semiconductor memory device having the structure of the present invention, there is obtained an effect that a memory cell whose drain region does not sufficiently overlap with the floating gate electrode due to the above-described trouble can be electrically detected. Can be

(Third Embodiment) Next, a third embodiment of the present invention will be described. FIGS. 10A to 10C and FIGS. 11A to 11C are cross-sectional views illustrating manufacturing steps of the nonvolatile semiconductor memory device according to the third embodiment.
The nonvolatile semiconductor memory device according to the present embodiment has the same structure as that of the first embodiment shown in FIG. 1, but differs in the manufacturing method.

In the step shown in FIG. 10A, a p-well and a LOCOS isolation film (not shown) are formed on the p-type Si substrate 1. Next, on the p-type Si substrate 1, a thickness of 10 n
A silicon oxide film having a thickness of about m, a first polysilicon film, an ONO film having a thickness of about 18 nm, and a second polysilicon film are sequentially formed. Then, after forming a resist film 31 having a pattern of a gate to be formed, anisotropic etching is performed using the resist film 31 as a mask, so that the second polysilicon film, the ONO film, the first polysilicon film and The silicon oxide film is sequentially patterned to form a laminated gate portion 10 including the control gate electrode 5, the capacitor insulating film 4, the floating gate electrode 3, and the tunnel insulating film 2.

Next, in the step shown in FIG. 10B, the phosphorus ion (P +) is applied under the conditions of an acceleration voltage of 30 to 80 keV, preferably 35 to 60 keV, and a dose of about 1 × 10 ¹⁴ cm ^−2.
) Is implanted to form a phosphorus ion implanted layer 33 on the source side and the drain side of the p-type Si substrate 1.

Next, in the step shown in FIG. 10C, a thermal oxidation process is performed to form a protective oxide film 6 on the entire surface of the substrate. At this time, the ridge portion on the lower end side of the floating gate electrode 3 is oxidized to form a gate bird's beak 7.
The protective oxide film 6 prevents unnecessary contamination at the time of various ion implantations. The ridge of the floating gate electrode 3 is chamfered by the gate bird's beak 7 formed at the same time.

Next, in the step shown in FIG. 11A, a resist film 8 covering substantially half of the laminated gate portion 10 and the drain side of the p-type Si substrate 1 and opening the source side of the p-type Si substrate 1 is formed. Is formed, and using this resist film 8 as a mask, p
Impurity ions are implanted into the source region of type Si substrate 1. First, the acceleration voltage is 30 to 80 keV, preferably 3
After arsenic ions (As +) are implanted under the conditions of ^{5 to} 60 keV and a dose of about 6 × 10 ¹⁵ cm ⁻² to form the arsenic ion implanted layer 11, the acceleration voltage is 30 to 80 keV, preferably 35 to 60 keV. , Dose amount is about 1.5 × 10
^By implanting phosphorus ions (P +) under the condition of ¹⁵ cm ^-2 , a phosphorus ion implanted layer 12 is formed. Although only the peak portions of the arsenic ion-implanted layer 11 and the phosphorus ion-implanted layer 12 are shown in FIG.
Each of the phosphorus ion implanted layers 12 extends over a wide range in the depth direction.

Next, in the step shown in FIG. 11B, a resist film 13 covering substantially half of the stacked gate portion 10 and the source side of the p-type Si substrate 1 and opening the drain side of the p-type Si substrate 1 is formed. After the formation, impurity ions are implanted into the drain region of the p-type Si substrate 1 using the resist film 13 as a mask. First, the acceleration voltage is 30~80keV Preferably 35～60KeV, after forming the arsenic ions implanted layer 17 by implanting arsenic ions (As +) at a dose of about 5 × 10 ¹⁴ cm ^-2, an acceleration voltage Is 40 to 70 keV, preferably 45 to 60 keV, and the dose is about 2.5 × 10 ¹³
Boron ions (B +) are implanted under the condition of cm ^-2 to form a boron ion implanted layer 19. Although only the peak portions of the arsenic ion-implanted layer 17, the phosphorus ion-implanted layer 33, and the boron ion-implanted layer 19 are shown in FIG. Reference numeral 19 extends over a wide range in the depth direction. Here, boron ions are implanted in a direction inclined by 45 ° with respect to a direction perpendicular to the main surface of the p-type Si substrate 1 by a large-angle ion implantation method. It can be formed up to a region overlapping with the stacked gate section 10.

Next, in the step shown in FIG.
By performing the heat treatment at 0 ° C., the impurities in the arsenic ion-implanted layer 11, the phosphorus ion-implanted layer 12, the arsenic ion-implanted layer 17, the phosphorus ion-implanted layer 33, and the boron ion-implanted layer 19 are activated and diffused. On the source side in the Si substrate 1, a source n + layer 20 and a source n− layer 21 are formed, while on the drain side, a drain n + layer 22, a drain n− layer 23 and a p layer 24 are formed. . Here, due to this heat treatment, in the source region in the p-type Si substrate 1, the phosphorus ion implanted layer 1
Since only phosphorus at a concentration lower than 2 is introduced, the source n − layer 21 is formed solely by diffusion of phosphorus in the phosphorus ion implanted layer 12. The source n − layer 21 containing phosphorus having a large range and diffusion coefficient surrounds the bottom of the source n + layer 20 containing arsenic having a small range and diffusion coefficient than phosphorus. In a region near the surface, the layer is formed in a wide range so as to overlap with the stacked gate portion 10.

On the other hand, in the drain region in the p-type Si substrate 1, the drain n− layer 23 containing phosphorus having a larger range and diffusion coefficient has a drain n + containing arsenic having a smaller range and diffusion coefficient than phosphorus. The p-type Si substrate 1 is formed in a range wider than the layer 22 and in a region near the surface of the p-type Si substrate 1 so as to overlap the stacked gate portion 10. However, since the phosphorus ion-implanted layer 33 contains a relatively low concentration of phosphorus, the region in the back of the p-type Si substrate 1 is neutralized by boron of the boron ion-implanted layer 24.
Therefore, the drain n− layer 23 is formed only in the region near the surface of the p-type Si substrate 1 and
And are formed so as to overlap. Further, the p layer 24 containing boron which is implanted with relatively high energy and has a large diffusion coefficient includes the drain n + layer 22 and the drain n
-In a region surrounding the bottom of the layer 23 and near the surface of the p-type Si substrate 1, it is formed so as to enter the inside of the laminated gate portion 10 more than the drain n- layer 23.

Thereafter, the same processing as the step shown in FIG. 3C in the first embodiment is performed to form the insulator sidewall, the drain n ++ layer 26a, the source n ++ layer 2
6b is formed.

According to the third embodiment, in addition to the effects of the first embodiment, phosphorus ions are implanted before forming the protective oxide film 6 and the gate bird's beak 7, that is, the tunnel insulating film 2 and the first polysilicon. The silicon film 3, the capacitor insulating film 4, and the second polysilicon film 5 are patterned to form a laminated gate portion 10.
Is performed immediately after the formation, the effect that the phosphorus ion implanted layer 33 can be diffused deeper into the region below the floating gate electrode 3 than in the first embodiment.

In the third embodiment, in order to form the drain n + layer 22 and the drain n − layer 23 in the drain region, phosphorus ion implantation is performed before forming the protective oxide film 6 and the gate bird's beak 7. The arsenic ion implantation is performed after the formation of the protective oxide film 6 and the gate bird's beak 7, but the arsenic ion implantation is performed before the formation of the protection oxide film 6 and the gate bird's beak 7. Phosphorus ion implantation may be performed after the bird's beak 7 is formed, or both phosphorus ion implantation and arsenic ion implantation may be performed before the protective oxide film 6 and the gate bird's beak 7 are formed. You may.

In the first and third embodiments, two types of ions (P + and As +) having different ranges and diffusion coefficients are used for forming the drain region. The above-described ion implantation may be performed. In this case, at least one of the three or more types having a large range is used, similarly to the state where the drain n− layer 23 of the drain region overlaps the floating gate electrode 3. The impurity layer formed by the ion implantation described above may be formed so as to overlap the stacked gate portion 10 over the entire gate width direction of the stacked gate portion 10 on the element formation region.

In the first and third embodiments, all the n-type and p-type regions may be configured to be reversed.

[0080]

According to the present invention, two diffusion layers containing at least two types of impurities of the second conductivity type having different ranges from each other are provided in the drain region, and the diffusion layer containing at least the impurity having a large range is provided. In plan view, the end portion of the stacked gate portion on the element formation region along the gate width direction overlaps the entire portion, so that the drain region and the first conductivity type region are steep. The drain disturb characteristic can be improved without forming a portion where the drain region does not overlap with the floating gate while forming a proper pn junction, and without reducing the writing speed or increasing the short channel effect. It is possible to improve reliability and increase integration.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a structure of a memory cell of a nonvolatile semiconductor memory device according to a first embodiment.

FIG. 2 is a cross-sectional view showing the first half of the manufacturing process of the nonvolatile semiconductor memory device according to the first embodiment.

FIG. 3 is a process cross-sectional view showing a latter half of the manufacturing process of the nonvolatile semiconductor memory device according to the first embodiment.

FIG. 4 is a plan view showing a part of the memory cell array of the nonvolatile semiconductor memory device according to the first embodiment.

5 is a cross-sectional view taken along line Va-Va of FIG. 4 and a diagram showing changes in impurity type and concentration along the gate length direction.

6 is a cross-sectional view taken along the line VIa-VIa of FIG. 4, a diagram showing changes in impurity type and concentration along the gate length direction, and a schematic diagram for explaining the effect of suppressing accumulation of hot holes at the drain end. FIG.

FIG. 7 is a diagram illustrating drain disturb characteristics of the nonvolatile semiconductor memory devices according to the first embodiment and a comparative example.

FIG. 8 is a block circuit diagram showing a structure of a memory cell array of the nonvolatile semiconductor memory device according to the related art and the first embodiment.

FIGS. 9A and 9B are a block circuit diagram and a schematic cross-sectional view illustrating a method for testing a memory cell array of a nonvolatile semiconductor memory device according to a second embodiment.

FIG. 10 is a cross-sectional view showing the first half of the manufacturing process of the nonvolatile semiconductor memory device according to the third embodiment.

FIG. 11 is a sectional view showing the latter half of the manufacturing process of the nonvolatile semiconductor memory device according to the third embodiment.

FIG. 12 is a cross-sectional view illustrating a manufacturing process of the nonvolatile semiconductor memory device according to the comparative example.

FIG. 13 is a plan view showing a part in a memory cell array of a nonvolatile semiconductor memory device according to a comparative example.

14 is a cross-sectional view taken along line XIVa-XIVa in FIG. 13 and a diagram showing changes in impurity types and concentrations along the gate length direction.

FIG. 15 is a cross-sectional view taken along line XVa-XVa of FIG. 13, a diagram showing changes in impurity type and concentration along the gate length direction, and a schematic diagram for explaining the effect of suppressing accumulation of hot holes at the drain end. FIG.

16A and 16B are a cross-sectional view showing a structure of a memory cell of a conventional nonvolatile semiconductor memory device described in a paper in IEDM 90, and a flow diagram showing a manufacturing process.

17 is a cross-sectional view showing a state of formation of an ion-implanted layer and an impurity diffusion region at the time of impurity ion-implantation in a cross section taken along line XVIIa-XVIIa in FIG. 4;

18 is a cross-sectional view showing a state of formation of an ion implantation layer and an impurity diffusion region at the time of impurity ion implantation in a cross section taken along line XVIIIa-XVIIIa in FIG. 13;

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 p-type Si substrate 2 tunnel insulating film 3 floating gate electrode 4 capacitance insulating film 5 control gate electrode 6 protective oxide film 7 gate bird's beak 8 resist film 11 arsenic ion implanted layer 12 phosphorus ion implanted layer 13 resist film 17 arsenic ion implanted layer 18 Phosphorus ion implanted layer 19 Boron ion implanted layer 20 Source n + layer 21 Source n− layer 22 Drain n + layer 23 Drain n− layer 24 P layer 25 Insulator sidewall 26a Drain n ++ layer 26b Source n ++ layer 27 LOCOS Separation film 29 Word line 30 Bit line 31 Resist film 33 Phosphorus ion implantation layer

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Miki Ando 1-1, Kochi-cho, Takatsuki-shi, Osaka Matsushita Electronics Co., Ltd. (72) Inventor Toshimoto Kubota 1-1, Kochi-cho, Takatsuki-shi, Osaka Matsushita Electronics Industrial Co., Ltd.

Claims (9)

[Claims] A semiconductor substrate of a first conductivity type; a stacked gate portion formed by sequentially stacking a tunnel insulating film, a floating gate electrode, a capacitor insulating film, and a control gate electrode on the semiconductor substrate; A second conductivity type source region and a drain region provided in the element formation region on the surface of the substrate with the stacked gate portion interposed therebetween; and a first conductivity type region surrounding a bottom of the second conductivity type drain region. A writing function by generating a hot carrier by applying a voltage between the drain and the source; the drain region includes a first diffusion layer containing a first impurity of a second conductivity type; At least a second diffusion layer containing a second impurity of a second conductivity type having a greater range at the time of ion implantation than the first impurity. Is a non-volatile semiconductor memory device, wherein in a plan view, an end of the stacked gate portion in the element formation region along a gate width direction is entirely overlapped. 2. The nonvolatile semiconductor memory device according to claim 1, wherein said first impurity is arsenic, and said second impurity is phosphorus. 3. The non-volatile semiconductor storage device according to claim 1, wherein said source region comprises only a second conductivity type region. 4. The nonvolatile semiconductor memory device according to claim 1, wherein a diffusion coefficient of said second impurity in a heat treatment for activating said impurity is larger than a diffusion coefficient of said first impurity. Non-volatile semiconductor storage device. 5. A first step of forming a stacked gate portion by sequentially stacking a tunnel insulating film, a floating gate electrode, a capacitor insulating film, and a control gate electrode on a semiconductor substrate of a first conductivity type; A second step of forming a source region and a drain region of the second conductivity type in the element formation region on the surface of the semiconductor device with the stacked gate portion interposed therebetween; and a first step of covering the bottom of the drain region of the second conductivity type.
And a third step of forming a conductivity type region. In the second step, at least two steps having different ranges are provided.
At least two types of diffusion layers of the second conductivity type are formed by ion-implanting impurities of the second conductivity type to form at least two types of diffusion layers of the second conductivity type. A method of manufacturing a non-volatile semiconductor memory device, wherein, as viewed from the outside, an end portion of the stacked gate portion along the gate width direction on the element formation region is entirely overlapped. 6. The method of manufacturing a nonvolatile semiconductor memory device according to claim 5, wherein in the second step, the dose of the impurity ion having a larger range is determined by the dose of the impurity ion having a smaller range. A method for manufacturing a nonvolatile semiconductor memory device, wherein the amount is smaller than the amount. 7. The method of manufacturing a non-volatile semiconductor storage device according to claim 5, wherein in the second step, at least one type of ion implantation of the at least two types of second conductivity type impurities is performed. A method for manufacturing a nonvolatile semiconductor memory device, wherein ion implantation is performed immediately after forming a stacked gate portion. 8. The method of manufacturing a nonvolatile semiconductor memory device according to claim 5, wherein in the third step, a first conductive type for forming the first conductive type region is provided. The ion implantation of the impurity is characterized by using a large angle ion implantation performed from a direction having an angle of 20 degrees or more with respect to a normal direction of the semiconductor substrate so as to be implanted also into a lower region of the stacked gate portion. A method for manufacturing a nonvolatile semiconductor memory device. 9. The method for manufacturing a nonvolatile semiconductor memory device according to claim 5, wherein the impurity having the larger range has a higher impurity content than the impurity having the smaller range. A method for manufacturing a nonvolatile semiconductor memory device, wherein a diffusion coefficient in a heat treatment for activation is large.