JPH11162981A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form equal and highly accurate patterns within the same substrate, by possessing one or plural sheets of patterns for check of resolution, in a region other than a first region where a pattern highest in density is made. SOLUTION: A memory part 30 occupies about half of one side on a chip 10, and a logic part 20 is made in the residual region. In plane patterns of electrodes made in the regions a and a' surrounded by broken lines within the memory part 30, gate electrode patterns under minimum line rule are made densely roughly all over the surface. Moreover, electrode patterns are made also in a region b surrounded by a broke line at the end within the logic part 20. Especially, at one part of an auxiliary pattern 13, a plurality of line-shaped electrode patterns 14 made under minimum line rule similar to the one made in the memory part 30 are made. Similarly, check of a resolution of the pattern under minimum line rule becomes possible not only in the memory part 30 but also in the logic part 20.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to an integrated circuit having both a region for forming a coarse pattern and a region for forming a dense pattern in the same chip.

[0002]

2. Description of the Related Art FIG. 4A shows a memory section 130 and a Log section.
FIG. 2 is a plan view showing an example of an integrated circuit having an ic section 120 on the same chip 110. Here, the memory unit 130 is formed at about half of the left side from the center of the circuit formation region, and the Logic unit 120 is formed in the remaining region. In addition,
The outer periphery of the circuit formation region is a region provided for dicing.

FIG. 4B shows an enlarged plane pattern of areas a and a 'surrounded by broken lines in the memory section 130 in FIG. 4A. FIG. 4C shows an enlarged plane pattern of a region b surrounded by a broken line in the Logic portion in FIG. 4A.

[0004] As shown in FIG.
A plurality of linear gate electrodes 111 corresponding to word lines are densely formed on the surface of the substrate. The gate electrode 111 is formed so as to straddle a plurality of transistor cells arranged in an array, and its line rule is an extremely fine pattern of usually 0.4 μm to 0.25 μm. Note that the regular irregularities in the line pattern of the gate electrode 111 correspond to the planar structure of the memory cell.

On the other hand, as shown in FIG.
A dense electrode pattern is not formed in the c portion 120 unlike the memory portion, and a single T-shape (however,
The shape of the gate extraction electrode 1 is not limited.)
Only 12 are formed, and the electrode pattern becomes a rough region.

FIGS. 5A to 5C are cross-sectional views of a conventional semiconductor device having the above-mentioned planar pattern, showing the manufacturing steps of the device. The region shown on the left side of the two broken lines in the figure corresponds to a partial cross section corresponding to the region a of the memory unit 130, and the center and the region on the right side thereof correspond to a partial cross section corresponding to the region b in the Logic unit. I do.

[0007] As shown in FIG.
A trench (trench) for forming an element isolation region is formed in the silicon substrate 101 of the mold. Thereafter, an insulating film such as silicon oxide (SiO2 film) is formed on the substrate, the trench is filled, and the surface of the substrate is smoothed by using a CMP (Chemical Mechanical Polishing) method to form a buried element isolation region 102. I do.

Thereafter, a gate oxide film 103 is formed on the substrate and a gate electrode 111 is formed on the gate oxide film 103 according to a normal transistor forming process. The gate electrode 111 is formed, for example, of a polycrystalline silicon film 104 doped with phosphorus (P) and a tungsten silicon (WSi) film 1.
05 is formed. At the same time, a gate lead electrode 112 of a Logic portion having the same film configuration is formed also in the region b. Gate electrode 111 and gate extraction electrode 1
12 is used as an implantation mask, an n-type impurity such as P is ion-implanted into the substrate surface, and a source / drain region 106 is formed through a thermal diffusion process.

After that, an insulating film such as a SiNx film is formed on the surface of the substrate. The spacer 107 is formed by etching the entire surface of the SiNx film so that a part of the film remains on the side wall of the gate electrode 111. On the substrate surface in the region a in the memory unit 130,
Although a plurality of gate electrodes 111 are formed densely,
Only a single gate extraction electrode 112 is formed on the surface of the substrate in the region b in the portion c, and the electrode on the substrate has an extremely coarse pattern.

[0010] As shown in FIG. 5B, an insulating film 108 such as boron phosphosilicate glass (BPSG) is formed on the surface of the substrate. The surface of the insulating film 108 has a step due to the presence or absence of a protrusion due to the electrode pattern formed on the substrate.

Next, in order to remove a step of the insulating film 108,
The substrate is heat-treated, and the BPSG film as the insulating film 108 is reflowed. Subsequently, the insulating film 10 is formed using a CMP process.
8 Grind the surface. As shown in the left view of FIG.
In the region a, the surface height of the insulating film 108 and the gate electrode 11
1 can be made uniform and the surface can be flattened.

However, as shown in the center and right views in FIG. 5C, Logi having a rough electrode pattern is used.
In the region b of the portion c, since the convex portion pattern for suppressing the deflection of the polishing pad is not present in a wide region during the CMP process, the BPSG surface becomes lower than the surface of the gate extraction electrode 112 in the CMP process. A so-called phenomenon may occur.

In order to eliminate such a dishing phenomenon, electrode patterns as shown in FIGS. 6A to 6C are currently being studied. That is, similarly to the substrate shown in FIG. 5A, in a semiconductor device having the memory unit 130 and the Logic unit 120 in one chip, the pattern of the gate electrode 111 formed in the memory unit 130 is as follows.
This is the same as that shown in FIG. 5B (see FIG. 6B), but in the region b which is the end of the Logic part 120, around the gate lead-out electrode pattern 112 conventionally formed only in a single form. The auxiliary pattern 113 is formed.

The steps of manufacturing a semiconductor device using the electrode patterns shown in FIGS. 6A to 6C will be described with reference to FIGS. 7A to 7C. The basic steps are the same as the above-described conventional manufacturing steps. That is, first, as shown in FIG. 7A, an embedded element formation region 102 is formed in a substrate 101, and a gate insulating film 11 is formed on the substrate.
0, a polycrystalline silicon film 104 and a WSi film 105 are formed and patterned, and a necessary gate electrode 111 is formed.
The pattern, the gate extraction electrode 112 and the auxiliary pattern 113 are formed simultaneously.

Next, as shown in FIG. 7B, an insulating film 108 made of, for example, a BPSG film is formed on the surface of the substrate, and then the substrate is heat-treated, and the insulating film 108 is reflowed to remove a step in the film. In the region b of the Logic portion, the presence of the auxiliary electrode pattern serves as a stopper in the CMP process, and the dishing unlike the conventional case does not occur.

Therefore, as shown in FIG.
After the reflow of the G film, the CMP process is performed, so that the gate electrode 111, the gate extraction electrode 112,
The surface can be flattened so that the surface height of each auxiliary pattern 113 is the same as the surface height of the insulating film 108.

[0017]

As described above, as described above, Lo
By forming the auxiliary pattern 113 having the same height as the gate electrode 111 in the gic portion 120, the BPSG
After the film CMP process, a substantially flat surface can be formed over the entire surface of the substrate. However, as described above, in a semiconductor device in which a dense electrode pattern such as a memory portion and a coarse electrode pattern such as a Logic portion are mixed on the same chip, there is another problem as follows.

Usually, the pattern of the gate electrode 111 corresponding to the word line in the memory section is formed according to the minimum line rule on the chip. When such a fine line pattern is formed using a photolithography process, first, a photoresist film is applied and formed on a substrate, and then an alignment operation for aligning a position on the substrate with an exposure mask is performed. Thereafter, exposure and development are performed to form a resist pattern. Usually 1
One chip is included in an area to be exposed in one exposure step, that is, in the exposure area. The resolution of the obtained photoresist pattern is confirmed at a predetermined position on the substrate, and an optimum exposure focal position is determined based on this information.

Generally, the pattern resolution is confirmed using a line pattern in a memory area where a pattern of a minimum line rule on a chip is formed. However, the fact that the resolution is checked only in a limited area on the chip, that is, only in the memory unit, means that the resolution is checked only in a limited area in the exposure area. That is, the optimum exposure setting for the memory section for which the resolution is to be checked, particularly the focus position of the exposure, is determined, and the exposure on the chip is performed under these conditions. However, in many cases, this condition is an optimal condition for the memory section, but is not always optimal for other areas.

For example, when the lens axis of the exposure lens and the image plane on the chip are normal, that is, in a parallel relationship, if the focus position is adjusted at a certain position on the image plane, the focus can be obtained over the entire image plane. become. However, if the lens axis of the exposure lens and the image plane on the chip are not parallel and slightly inclined, even if the focus position is correct at a certain position on the image plane, even if the focus position is set at a certain position on the image plane, At the position, a focus shift occurs. Such a state is generally called “image plane inclination”.

As described above, in the conventional method for checking the resolution of the pattern, "the inclination of the lens characteristic" including the above-mentioned "the inclination of the image plane" is generated, and the focus difference easily occurs depending on the position in the exposure area. There is a dimensional difference between patterns having the same dimensions between the Logic part and the Logic part, or the resolution in the Logic part is insufficient, and a non-resolution part occurs.

In view of the above problems, an object of the present invention is to provide
An object of the present invention is to provide a semiconductor device capable of forming a uniform and highly accurate pattern on the same substrate.

[0023]

According to a first aspect of the present invention, there is provided a semiconductor device having a plurality of regions having different pattern densities on the same substrate. That is, one or more resolution checking patterns are provided in an area other than the area.

According to the first aspect of the present invention, since the resolution confirmation pattern is formed in a region other than the first region where the pattern with the highest density is formed, the resolution can be confirmed in a wider region on the substrate. It can be carried out. As a result, a highly accurate pattern can be formed in a wider area on the substrate.

The semiconductor device according to claim 2 of the present invention is characterized in that, in a semiconductor device having a plurality of regions on a substrate having different electrode pattern densities, the first region on which the highest density electrode pattern is formed is provided. In the region, has an auxiliary electrode pattern having the same thickness as the electrode pattern, the auxiliary electrode pattern has a pattern for the resolution check in a part of the pattern, the first region, the The region where the resolution checking pattern is formed is both within the single exposure region in the photolithography process for forming the pattern.

According to the feature of the second aspect, since the auxiliary electrode pattern is provided in a region other than the first region having the electrode pattern with the highest density,
After the electrode pattern is formed, an insulating film is formed, and when the insulating film is subjected to a reflow process, the reflow of the insulating film is necessary even in a region where a gate electrode or the like is not formed in a wide area if there is an auxiliary electrode pattern. The dishing does not proceed as described above, and the occurrence of dishing, which has conventionally occurred, can be prevented. As a result, the surface of the substrate can be planarized through a CMP process performed later, regardless of the density of the formed electrode pattern. Furthermore, since a part of the auxiliary electrode pattern has a resolution checking pattern,
It is also possible to check the resolution over a wider area on the substrate. As a result, a highly accurate pattern can be formed in a wider area on the substrate.

The semiconductor device according to a third aspect of the present invention is characterized in that, in the semiconductor device according to the second aspect, the resolution check pattern is a line equivalent to a minimum line rule of an electrode pattern formed in the first region. That is, the electrode pattern has a rule.

According to the third aspect of the present invention, the resolution checking pattern is formed by the same line rule as the minimum line rule on the chip, so that the resolution of the resolution required for forming the minimum line rule can be obtained. Confirmation can be made over a wider area on the substrate.

If the above-mentioned first region is arranged at the center on the substrate, and the resolution checking pattern is arranged at the end of the circuit forming region on the substrate, the resolution at the center and the end of the substrate can be improved. Can be confirmed, the exposure conditions can be made uniform over almost the entire surface of the substrate, and a highly accurate pattern can be formed. Here, the circuit formation region refers to a memory portion or a Log portion.
A region where a circuit pattern including the ic portion can be formed.

Further, the resolution checking pattern may be formed in a dicing area at an end of the substrate, which is an area further outside the circuit forming area. Since the resolution can be checked in a wider area, the exposure conditions can be made more uniform over almost the entire surface of the substrate, and a highly accurate pattern can be formed.

[0031]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) First, FIGS.
A first embodiment of the present invention will be described with reference to FIG.

FIG. 1A is a plan view showing a plan configuration of the semiconductor device according to the first embodiment. As shown in the figure, here, DRAM and Lo are mounted on one chip 10.
A description will be given by taking an integrated circuit element equipped with a gic circuit as an example. As shown in the figure, the DRAM area (memory section) 3
0 occupies about half of one side on the chip, and the Logic part 20 is formed in the remaining area.

The area of the memory section 30 varies depending on the application, but a large area is, for example, 5 mm × 12 m.
m, the area of the Logic unit 20 is, for example, 5 mm × 14 mm
It is.

FIG. 1B is an enlarged plan view showing a plane pattern of electrodes formed in regions a and a 'surrounded by broken lines in the memory section 30. FIG. In the memory unit 30, a gate electrode pattern with a minimum line rule of 0.25 μm to 0.15 μm is densely formed almost over the entire surface.

FIG. 1C is an enlarged plan view showing an electrode pattern formed in a region b surrounded by a broken line at an end of the Logic portion 20. Characteristically, a plurality of linear electrode patterns 14 formed by a minimum line rule similar to that formed in the memory unit 30 are formed in a part of the conventional auxiliary pattern 13.

As described above, in the semiconductor device according to the first embodiment, the electrode pattern of the minimum line rule conventionally formed only in the memory section is formed in a part of the auxiliary pattern provided in the Logic section 20. Therefore, the resolution of the minimum line rule pattern can be confirmed not only in the memory unit 30 but also in the Logic unit 20.

A method for manufacturing a semiconductor device according to the first embodiment will be described with reference to FIGS. On the left side of two broken lines in the figure, a partial cross section of the device corresponding to the area a in the memory section is shown. In the drawing, a region where the gate lead-out electrode 12 is formed in the region b in the Logic portion is shown between two broken lines. In the area to the right of the two break lines in the drawing, Lo
In the area corresponding to the area b in the gic section 20, particularly, an area where the same linear electrode pattern 14 as the gate electrode 11 of the memory section 30 is formed is shown.

First, as shown in FIG.
A trench for forming an element isolation region is formed in a silicon substrate 1 of a mold type. On the substrate on which the trench was formed, CVD (Ch
An insulating film such as a SiO2 film is formed by using an emical vapor deposition method, and the trench is filled. Furthermore, CM
An excess SiO2 film on the substrate is removed by using the P method, the surface of the substrate is planarized, and a buried element isolation region 2 is formed.

A thin gate insulating film 3 such as a SiO 2 film is formed on the surface of the substrate by using a CVD method or the like. On the gate insulating film 3, a polycrystalline silicon film 4 doped with phosphorus (P) to be a gate electrode is formed by a sputtering method or the like. Further, a WSi film 5 is formed on the polycrystalline silicon film 4 also by using a sputtering method or the like.

Next, a photoresist film is applied and formed on the substrate surface, and a resist pattern corresponding to the electrode pattern to be formed is formed through alignment, exposure and development steps. In the memory unit, the minimum line rule, for example, 0.
A resist pattern for a gate electrode having a line rule of 15 μm to 0.25 μm is formed. At the same time, Logic part 2
A resist pattern for a gate lead-out electrode and a resist pattern for a line-shaped electrode having substantially the same line rule as that of the memory unit are also formed in a region b within 0.

Not only the memory unit 30 but also the Logic unit 2
Since a resist pattern corresponding to the electrode pattern of the minimum line rule on the chip is also formed in the region b within the chip 0, this pattern is used not only in the memory region but also in the Logic region 20 using this pattern. Resolution can be checked. For example, after exposing the resist pattern, the pattern size is measured with both the resist pattern in the memory unit 30 and the resist pattern in the Logic unit 20, and the optimum focus of the exposure apparatus that minimizes the pattern size difference from the measured value is measured. Find the position. The obtained data is fed back to the exposure apparatus to eliminate the difference in the focal position depending on the position in the exposure area, so-called image plane tilt,
This makes it possible to prevent a difference in patterning accuracy from occurring between locations in the exposure region.

Using this resist pattern as a mask, W
The Si film 5 and the polycrystalline silicon film 4 are dry etched to form an electrode pattern in each region. The gate electrode 11 of the minimum line rule is formed in the memory unit 30, and the gate lead-out electrode 12, the auxiliary pattern 13, and the linear electrode pattern 14 having the minimum line rule are formed in the region b in the Logic unit 20.

The linear electrode pattern 14 formed in the Logic section 20 is not limited to a specific line shape, but may be any pattern whose resolution can be confirmed. Therefore, for example, a linear pattern having a constant width may be used.
If the same pattern as that of the memory unit 30 is used as shown in FIG. 1C, it becomes easier to compare and examine the resolution. Further, the linear electrode pattern 14 is formed only in a part of the region b, but may be formed in a wider region. Further, such a pattern may be arranged at a plurality of places in the Logic section.

Thereafter, an n-type impurity, for example, P is implanted into the substrate surface layer by ion implantation using each electrode pattern and the newly formed resist pattern as an implantation mask. Further, the implanted P is activated by heat treatment to form source / drain regions 6 in the substrate surface layer.

Subsequently, a silicon nitride film (SiN
An xN film is formed, and the SiNx film on the substrate surface is etched so as to slightly leave a film only on the side surface of each electrode. Thus, spacers 7 are formed on the side surfaces of each electrode.

Next, as shown in FIG. 2B, an insulating film 8 such as a BPSG film is formed on the entire surface of the substrate by using a CVD method or the like. Since the electrode patterns of the same height are densely formed on the substrate in both the region a and the region b, the BPS
The surface height of the G film does not greatly differ from region to region.

After that, the substrate is heated and the insulating film 108 is reflowed to further reduce the level difference of the BPSG film.

As shown in FIG. 2C, after reflowing the BPSG film, a CMP process is performed to
In the region b of the Logic part 20 as well as in the region a of the gate electrode 11, the gate electrode 11, the gate electrode 12, and the electrode surface of the line-shaped electrode pattern 14 have the insulating film 108
The surface can be flattened to be the same as the surface height.

Since the auxiliary pattern 13 and the line-shaped electrode pattern 14 are present in the region b in the Logic portion 20, dishing as in the prior art may occur to prevent the polishing cloth from being excessively bent in the CMP process. Nor.

As described above, not only the memory section 30 but also the end of the Logic section 20 are provided with the electrode pattern of the minimum line rule. It is possible to prevent a difference in pattern accuracy from occurring depending on the location due to the inclination. As a result, a high-precision pattern can be formed in a wide area on the substrate, and the occurrence of a pattern defect due to the image plane inclination unlike the related art is unlikely to occur. In addition, since the surface of the substrate can be reliably flattened, high-precision patterning can be performed even when a wiring layer or the like is further formed thereon.

(Second Embodiment) Next, FIGS.
The second embodiment of the present invention will be described with reference to FIG.

FIG. 3A is a plan view showing the configuration of the semiconductor device according to the second embodiment. As shown in the figure, the DR 10 is provided on the chip 10 as in the first embodiment.
Although an AM and a Logic circuit are mounted, the difference from the first embodiment lies in the DRAM area (memory section 30).
Is located in the center of the chip, and Logic is
The point is that a circuit is formed. Memory unit 3 shown here
The area of 0 is, for example, about 5 mm × 12 mm in a large one,
The area of the Logic unit 20 is, for example, 5 mm × 14 mm formed at two places on both left and right sides of the memory unit 30.

FIG. 3B is an enlarged plan view showing a plane pattern of an electrode formed in a region c surrounded by a broken line in the memory section 30. The memory unit 30 has a gate electrode 1 having a minimum line rule of 0.15 μm to 0.25 μm as in the related art.
One pattern is densely formed in almost the entire area.

FIG. 3C is an enlarged plan view showing an electrode pattern formed in regions d1 to d4 surrounded by broken lines located at four corners in the Logic section 20. The shape and arrangement of the electrode patterns formed in each region are the same as those formed in the region b in the first embodiment.

As in the semiconductor device according to the first embodiment described above, not only the memory section 30 but also the end of the Logic section 20 are provided with the electrode pattern of the minimum line rule. The patterning is performed over a wide area on the substrate to prevent a difference in pattern accuracy from occurring depending on the location due to the inclination of the image plane, and highly accurate patterning can be performed over a wide area of the substrate.

In particular, since the minimum line rule patterns are arranged in a well-balanced manner at the center and four corners of the chip, uniform exposure conditions can be more easily obtained over a substantially entire area of the chip. In this case, it is preferable that the center of the exposure area in the exposure step be aligned with the center of the chip.

The semiconductor device according to the second embodiment can be formed through the same steps as those of the semiconductor device according to the first embodiment. Since dense patterns are also formed at the four corners of the Logic portion, the occurrence of dishing as in the related art can be prevented.

Although the present invention has been described with reference to the embodiments, the present invention is not limited to these embodiments. For example, in the above-described embodiment, the memory cell array of the DRAM having the minimum line rule is
Although an example of a semiconductor device having an ic circuit on the same chip is shown, the same effect can be obtained by applying the present invention to a semiconductor device having a large exposure area and a large pattern density difference depending on a place.

In the above example, the case where there is a difference in the pattern density of the gate electrode is mentioned. However, the same applies to the case where there is a difference in the pattern density of the element isolation region and the metal wiring pattern. If the resolution checking pattern is formed in an area where the pattern is coarse, high-precision patterning can be performed in a wider area on the substrate.

The position at which the resolution checking pattern having the same line rule as the pattern of the minimum line rule is arranged is not limited to the position shown in the first and second embodiments, but is a position where the exposure state can be checked. If so, the pattern may be arranged anywhere in the coarse area. At this time, it is preferable that the pattern can be confirmed in as large an area as possible. For example, the resolution confirmation pattern can be provided on a dicing area corresponding to the outer peripheral edge of the chip. At this time, it is preferable to provide at the four corners of the rectangular chip. It will be apparent to those skilled in the art that various other modifications, improvements, combinations, and the like can be made.

[0062]

As described above, according to the present invention, in a semiconductor device having a large pattern density such as an electrode depending on a place, a resolution check pattern is arranged even in a coarse pattern area. The pattern resolution can be checked within the range. This makes it possible to correct a difference in exposure conditions depending on a location due to an inclination of an image plane or the like, and to perform high-precision patterning over a wider area of the substrate surface.

At the same time, in the manufacturing process, a problem such as dishing does not occur, and the substrate surface can be more reliably flattened using the CMP process. Therefore, high-precision patterning can be performed over the entire area of the chip surface.

[Brief description of the drawings]

FIG. 1 is a plan view of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of the device in each step for describing the method for manufacturing a semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a plan view of a semiconductor device according to a second embodiment of the present invention.

FIG. 4 is a plan view of a conventional semiconductor device.

FIG. 5 is a cross-sectional view of the device in each step for explaining a conventional method of manufacturing a semiconductor device.

FIG. 6 is a plan view of another conventional semiconductor device.

FIG. 7 is a cross-sectional view of the device in each step for explaining another conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Substrate 2 ... Element isolation region 3 ... Gate insulating film 4 ... Polycrystalline silicon film 5 ... WSi film 6 ... Source / drain region 7 ... Spacer 8 ... Insulating film 10 ... Chip 11 ... Gate electrode 12 ... Gate lead electrode 13 ... Auxiliary pattern 14 ... Linear electrode pattern

Claims (6)

[Claims] 1. A semiconductor device having a plurality of regions having different pattern densities on the same substrate, wherein one or more resolution checking patterns are provided in a region other than the first region where the highest density pattern is formed. Semiconductor device. 2. A semiconductor device having a plurality of regions having different electrode pattern densities on the same substrate, wherein a region other than the first region where an electrode pattern having the highest density is formed has the same thickness as the electrode pattern. Have one
Or a plurality of auxiliary electrode patterns, wherein the auxiliary electrode pattern has a resolution checking pattern in a part of the pattern, and the first region and the region where the resolution checking pattern is formed 2. The semiconductor device according to claim 1, wherein both are located within a single exposure region in a photolithography step for forming the pattern. 3. 3. The method according to claim 2, wherein the resolution checking pattern is the first pattern.
3. The semiconductor device according to claim 2, wherein the electrode pattern has a line rule equivalent to the minimum line rule of the electrode pattern formed in the region. 4. The method according to claim 1, wherein the first region is a region having a memory cell array, and the electrode pattern having the minimum line rule formed in the first region is a gate electrode of the memory cell array. The semiconductor device according to claim 3, wherein: 5. The method according to claim 1, wherein the first region is arranged at a center on the substrate, and one or a plurality of the resolution checking patterns are arranged at an end of a circuit forming region on the substrate. The semiconductor device according to any one of claims 1 to 4. 6. The semiconductor device according to claim 1, wherein one or a plurality of the resolution checking patterns are formed in a dicing region at an end of the substrate.