JPH1116292A - Synchronizing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a re-synchronizing action to be promptly obtained without the necessity of pulling into synchronism from a reset condition even in the condition that the synchronizing signal is not detected at a predicted position by accidental effects of noise, etc., though a correct synchronizing signal is detected. SOLUTION: A synchronizing signal detector 12 detects a synchronizing signal a2 and a synchronizing signal detecting and predicting circuit 13 is reset by the signal a2 to obtain a window signal b2 at the predicted position, and an AND circuit 15 obtains a prediction hitting pulse c2. A plural period judging circuit 30 outputs a signal d2 to continue the detecting state for plural periods of synchronizing signals. If the prediction hitting pulse c2 can be obtained during the period of this signal d2, a re-synchronizing condition judging circuit 18 judges that it is the synchronism detecting condition.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronizing circuit for synchronizing reproduced data when optically reproducing data from a recording medium such as an optical disk.

[0002]

2. Description of the Related Art Currently, digital audio compact disks (hereinafter abbreviated as CDs) having a diameter of 8 cm or 12 cm and analog video laser disks (hereinafter abbreviated as LDs) having a diameter of 20 cm or 30 cm are used as audio / video information recording media. Is abbreviated in the market).

Further, in addition to the CD and the LD, a high-density video disk (hereinafter referred to as a DVD) capable of recording moving images and a plurality of audio data based on the MPEG2 (Moving Picture Experts Group 2) standard has recently been developed.
Abbreviated).

FIG. 5 shows a data array for one sector of data recorded on the DVD. There are frames from the 0th frame to the 25th frame, and a synchronization signal is added at the beginning of each frame. The synchronization signal includes a specific code section and a common code section. There are eight types of synchronization signals, and these are combined and arranged so that, when looking at the types of surrounding synchronization signals, it is possible to know what frame number the current position is.

FIG. 6 shows that when the above data is input, a synchronization signal is detected and the serial / parallel converter 100
2 shows a synchronous circuit for obtaining the operation timing of FIG. Also,
FIG. 7 shows signal waveforms at various parts of the synchronous circuit.

The input terminal 11 receives the preceding data in the order of the 0th frame, the 1st frame, the 2nd frame,... This serial data is input to the synchronization signal detector 12 and the serial / parallel converter 100. The synchronization signal detector 12 detects a synchronization signal pattern and outputs a detection signal (a1). This detection signal is sent to the synchronization signal detection prediction circuit 13, one end of the AND circuit 14, and the AND circuit 15.
At one end.

When the detection signal (a1) is input to the synchronization signal detection / prediction circuit 13, since the period of the synchronization signal is predetermined, the period is counted by a counter, and the next synchronization detection signal will be obtained. The window signal (b1) is output to the position. The window signal (b1) is supplied to the AND circuit 15, the one-period determination circuit 16, the AND circuit 17,
It is supplied to the resynchronization condition judgment circuit 18. During the high level period of the window signal (b1), the next synchronization detection signal (a
When 1) arrives, the predictive medium pulse (c1) is output from the AND circuit 15.

The one-period determination circuit 16 generates and outputs a periodic pulse (d1) for one period from the predictive medium pulse (c1). The logical product of the periodic pulse (d1) and the next predictive middle pulse (c1) is obtained by the AND circuit 17.

The output of the AND circuit 17 is input to a resynchronization condition determination circuit 18. In the resynchronization condition determination circuit 18, when the logical product of the predictive medium pulse (c1) and the periodic pulse (d1) is obtained during the window signal (b1), the current synchronization state is determined to be accurate. The signal (e1) is output at a high level, and the synchronization detection signal (a1)
Passes through the AND circuit 14, and the synchronization signal detection prediction circuit 20
To be entered.

As a result, the synchronization signal detection prediction circuit 20
If the AND circuit 14 is conductive, the synchronization detection signal (a
Since 1) passes, an operation similar to that of the synchronization signal detection and prediction circuit 13 described above is obtained. That is, the synchronization signal detection prediction circuit 20 is reset by the synchronization detection signal (a1) via the AND circuit 14. The synchronization signal detection / prediction circuit 20 is the same circuit as the synchronization signal detection / prediction circuit 13 and obtains the same operation.

Therefore, in the synchronous state, the reset is performed by the synchronous detection signal (a1), and an appropriate synchronous signal (f1) for extracting data can be given to the serial / parallel conversion circuit 24. It has become.

An output similar to that of the AND circuit 15 can be obtained from the AND circuit 21. When the predictive medium pulse is obtained from the AND circuit 21 and a window signal is present, the out-of-synchronization determination circuit 23 determines that the synchronization state is established, and its output signal is, for example, low level.

However, if the synchronization detection signal (a1) does not arrive within the width of the window signal, no pulse output is obtained from the AND circuit 21. At this time, the out-of-synchronization determination circuit 23 determines that there is a window signal, but no predictive intermediate pulse (c1; in this case, the output of the AND circuit 21), and is output from the resynchronization condition determination circuit 18. The signal (e1) is turned off (low level) to prevent the resetting of the synchronization signal detection / prediction circuit 20 by the signal (a1).

[0014]

According to the above-described synchronization circuit, in the one-period determination circuit 16, the AND circuit 17, and the synchronization condition determination circuit 18, the synchronization signal detection / prediction circuit 13 outputs one window signal. Sometimes, if a predictive medium pulse cannot be obtained due to the influence of a scratch, noise, or the like, the resynchronization condition determination circuit 18 does not determine the resynchronization state. As a result, the operation for obtaining synchronization is redone from the beginning.

In practice, for example, as shown in FIG. 8, the expected synchronization detection cycle is correct, and in the next cycle, the synchronization signal can be detected. Even if serial-parallel conversion should be performed based on this cycle, You miss out on the opportunity to synchronize correctly. This allows
A synchronization pull-in operation must be performed from the initial reset state, and it takes time to reach a normal synchronization state, and an error in serial-parallel conversion output occurs.

Therefore, according to the present invention, it is necessary to perform synchronization pull-in from the reset state even in a state where a synchronization signal cannot be detected at a predicted position due to the influence of noise or the like even though a correct synchronization signal can be detected. It is another object of the present invention to provide a synchronization circuit that adaptively determines a synchronization state and reduces an error occurrence rate.

[0017]

According to the present invention, a digital data having a frame structure composed of digital data including a synchronization signal, and having a sector structure in which a plurality of the frames are aggregated, is provided.
A synchronizing signal detecting means for detecting the synchronizing signal, a clock signal of a constant frequency being counted in synchronization with the output of the synchronizing signal detecting means, and a time for detecting the next synchronizing signal is predicted. A synchronization signal detection / prediction circuit that outputs a window signal indicating a detection period of the synchronization signal within a predetermined period, and controls the synchronization signal or a signal synchronized with the synchronization signal when the synchronization signal is detected during the window signal. A synchronization circuit having means for performing synchronization control for reproducing digital data as a signal, wherein a hit pulse generation for generating a predictive hit pulse when the sync signal is detected in a shortest detection cycle of the window signal. Means,
With the predictive hit pulse from the hit pulse generating means as a trigger, it is determined whether or not the predictive hit pulse can be obtained again during a period of an integral multiple of the synchronization signal, and the predictive hit pulse is obtained. In this case, the synchronization control for reproducing the digital data is performed using the detected synchronization signal or a signal synchronized with the detected synchronization signal as a control signal.

According to the above-mentioned means, the detection of the synchronization signal at the time of resynchronization is performed at a point of time which is an integral multiple of the shortest cycle of the synchronization signal. Can be

[0019]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a synchronous circuit according to an embodiment of the present invention, and FIG. 2 shows signal waveforms at various parts of the circuit. This embodiment shows a synchronization circuit that detects a synchronization signal reproduced from a disk, for example, and obtains the timing of the data cutout operation of the serial / parallel converter 100.

Data from the disk is input to the input terminal 11 in the order of the 0th frame, the 1st frame, the 2nd frame, and so on. This serial data is input to the synchronization signal detector 12 and the serial / parallel converter 100.
The synchronization signal detector 12 detects a pattern of the synchronization signal,
A synchronization detection signal (a2) is output. This synchronization detection signal (a2) is sent to the synchronization signal detection prediction circuit 13 and the AND circuit 1
4 and one end of an AND circuit 15.

When the synchronization detection signal (a2) is input, the synchronization signal detection and prediction circuit 13 counts the period of the synchronization signal using a counter, and obtains the next synchronization detection signal because the period of the synchronization signal is predetermined. A window signal (b2) is output at the wax position. This window signal (b2)
AND circuit 15, multiple cycle determination circuit 30, AND circuit 1
7. It is supplied to the resynchronization condition determination circuit 18. During the high level period of the window signal (b2), the next synchronization detection signal (a
When 2) arrives, the predictive medium pulse (c2) is output from the AND circuit 15.

The multi-period determination circuit 30 generates and outputs a periodic pulse (d2) of a plurality of periods from the predictive medium pulse (c2). The logical product of this periodic pulse (d2) and the next predictive middle pulse (c2) is taken by the AND circuit 17.

The output of the AND circuit 17 is input to a resynchronization condition judgment circuit 18. In the resynchronization condition determination circuit 18, the window signal (b
When the logical product of the predictive medium pulse (c2) and the periodic pulse (d2) is obtained during the period 2), it is determined that the current synchronization state is accurate, and the signal (e2) is output at a high level. Then, the synchronization detection signal (a2) passes through the AND circuit 14 and is input to the synchronization signal detection prediction circuit 20.
The synchronization signal detection and prediction circuit 20 is a circuit similar to the synchronization signal prediction and detection circuit 13 described above.

Thus, the synchronization signal detection and prediction circuit 20
If the AND circuit 14 is conductive, the synchronization detection signal (a
Since 2) passes, an operation similar to that of the synchronization signal detection and prediction circuit 13 described above is obtained. That is, the synchronization signal detection prediction circuit 20 is reset by the synchronization detection signal (a2) via the AND circuit 14. When reset is performed in the synchronous state, the synchronous signal detection / prediction circuit 20 can supply the serial-parallel conversion circuit 24 with an appropriate synchronous signal (f2) for data extraction. I have.

Further, an output similar to that of the AND circuit 15 can be obtained from the AND circuit 21. When the predictive medium pulse is obtained from the AND circuit 21 and a window signal is present, the out-of-synchronization determination circuit 23 determines that the synchronization state is established, and its output signal is, for example, low level.

However, when the synchronization detection signal (a2) does not arrive within the width of the window signal, no pulse output is obtained from the AND circuit 21. At this time, the out-of-synchronization determination circuit 23 determines that there is a window signal, but no predictive intermediate pulse (c1; in this case, the output of the AND circuit 21), and is output from the resynchronization condition determination circuit 18. The signal (e2) is turned off (low level) so that the synchronization signal detection / prediction circuit 20 is not reset by the signal (a2).

In this case, the synchronization signal detection and prediction circuit 20
Is in a self-running state and outputs a synchronization signal (f2) at a constant cycle. According to the above circuit, the first synchronization detection signal (a
When the synchronization detection signal of the first cycle is obtained from 2), the operation determined to be the synchronization state is of course obtained. Further, even if a synchronization detection signal of a plurality of cycles (for example, a second synchronization detection signal) is obtained from the first synchronization detection signal (a2), the synchronization state can be determined and established. As a result, even if the synchronization detection signal happens to be missing in the first cycle, it can be pulled into the synchronization state in the next cycle. Therefore, the error rate of the data obtained from the serial / parallel converter 100 can be reduced as compared with the related art.

In particular, this synchronization circuit is effective when the disk playback device performs special playback (high-speed fast-forward, high-speed reverse-forward playback, slow playback, etc.) and synchronization is disturbed.

FIG. 3 shows a synchronous circuit according to another embodiment of the present invention, and FIG. 4 shows signal waveforms at various parts of the circuit. The same parts as those in the embodiment of FIG. 1 are denoted by the same reference numerals.

In this embodiment, the synchronization signal detection / prediction circuit 13 includes the first and second window signals (b2),
(B2 ') is created. The window signal (b2) has the same pulse width as in the previous embodiment,
The pulse width of the window signal (b2 ') is set wider than this. The window signal (b2 ′) and the synchronization detection signal (a2) are input to an AND circuit 41, which outputs a second predictive middle pulse (c2 ′).
Is obtained. This predictive medium pulse (c
2 ′) and the periodic pulse (d
2) is supplied to the AND circuit 42. The output of the AND circuit 42 is input to the resynchronization condition determination circuit 43.

In the above embodiment, the AND circuit 1
7, the resynchronization condition determination circuit 43 sets the signal (e2) to the high level, and the synchronization signal detection prediction circuit 20 outputs the synchronization detection signal (as in the previous embodiment). It operates in synchronization with a2).

When the result of the logical product (high level) is not obtained from the AND circuit 17 and the result of the logical product (high level) is not obtained from the AND circuit 42, the resynchronization condition determination circuit 43 outputs The signal (e2) is set to low level. At this time, the synchronization signal detection / prediction circuit 20 is in a free-running state, and the entire circuit is re-synchronized from the beginning.
However, when the result of the logical product (high level) is not obtained from the AND circuit 17 but the result of the logical product (high level) is obtained from the AND circuit 42, the resynchronization condition determination circuit 43 It is checked whether or not the result of the AND operation (high level) is obtained from the AND circuit 42 in a cycle. At this time, when a high level is obtained from the AND circuit 42,
The resynchronization condition determination circuit 43 sets the output signal (e2) to high level. That is, it is determined that synchronization has been obtained.

The synchronizing circuit for obtaining the above-mentioned operation includes the second window signal (b2 ') and the second predictive middle pulse (c
By making 2 ′), the detection accuracy is relaxed. That is, the section before and after the predicted synchronization signal detection position is less strict than in the previous embodiment. However, instead of relaxing, it is determined that synchronization is obtained for the first time after confirming the detection multiple times.

In such an operation, the resynchronization does not start from the detection of the first synchronization signal, but determines whether or not the cycle of this synchronization signal is correct in the next cycle. Parallel conversion can be performed correctly. Even with such an operation, there is an effect that the occurrence of errors can be reduced as compared with re-synchronization from the beginning.

[0035]

As described above, according to the present invention, even if a correct synchronization signal can be detected, a synchronization signal cannot be detected at a predicted position due to the influence of noise or the like. A resynchronization operation can be obtained quickly without the need for pull-in. Therefore, if serial-to-parallel conversion is performed based on the synchronization signal at this time, correct data output can be obtained, and occurrence of errors can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing signal waveforms at various parts of the circuit of FIG. 1;

FIG. 3 is a diagram showing a second embodiment of the present invention.

FIG. 4 is a diagram showing the operation of each part of the circuit of FIG. 3;

FIG. 5 is a diagram showing a frame configuration of a logical sector recorded on a disk.

FIG. 6 is a diagram showing a configuration example of a conventional synchronous circuit.

FIG. 7 is a view showing signal waveforms for explaining the operation of the synchronization circuit of FIG. 6;

FIG. 8 is a diagram showing signal waveforms for describing a problem in operation of the circuit in FIG. 6;

[Explanation of symbols]

 Reference numeral 12: Synchronous signal detector, 13, 20: Synchronous signal detection prediction circuit, 14, 15, 17, 21: AND circuit, 18: Resynchronization condition judgment circuit, 23: Loss of synchronization judgment circuit, 30: Multiple synchronization judgment circuit, 100: Serial-parallel conversion circuit.

Claims (4)

[Claims] 1. Synchronous signal detecting means for detecting the synchronous signal from digital data having a frame structure composed of digital data including a synchronous signal and having a sector structure in which the plurality of frames are aggregated, and the synchronous signal detecting means A synchronous signal that counts a clock signal of a constant frequency in synchronization with the output of the synchronization signal, predicts a time for detecting the next synchronization signal, and outputs a window signal indicating a detection period of the synchronization signal within a certain period around the predicted time. A signal detection and prediction circuit, and means for performing synchronization control for digital data reproduction using the synchronization signal or a signal synchronized with the synchronization signal as a control signal when the synchronization signal is detected during the window signal. In the synchronization circuit, when the synchronization signal is detected in the shortest detection cycle of the window signal, a prediction error pulse is generated. Pulse generating means, and using the predictive predictive pulse from the target predictive pulse generating means as a trigger, during a period of an integral multiple of the synchronization signal, determine whether the predictive predictive pulse is obtained again, When a hit pulse is obtained, a synchronization circuit for performing synchronization control for reproducing digital data using a detected synchronization signal or a signal synchronized with the detected synchronization signal as a control signal. 2. Synchronous signal detecting means for detecting a synchronous signal from digital data having a frame structure composed of digital data including a synchronous signal and having a sector structure in which a plurality of the frames are aggregated; A synchronous signal detection and prediction circuit that counts a clock signal of a constant frequency in synchronization with the output of the detection means, predicts a time for detecting the next synchronous signal, and generates a window signal within a predetermined period before and after the predicted time. And a synchronization circuit that performs synchronization control for reproducing digital data using the synchronization signal or a control signal synchronized with the synchronization signal when a synchronization signal is detected during the window signal. First hit pulse generating means for generating a first predictive hit pulse when the sync signal is detected in the detection cycle of: A second hit pulse generating means for detecting a synchronization signal before and after a temporal position whose position is predicted using a second window signal having a wider period than the window signal; With the predictive medium pulse from the medium pulse generating means as a trigger, it is determined whether or not the predictive medium pulse is obtained again during a period of an integral multiple of the synchronization signal, and the predictive medium pulse is obtained. In this case, a means for performing synchronization control for reproduction of digital data using a detected synchronization signal or a signal synchronized with the detected synchronization signal as a control signal; and the predictive prediction from the second hit pulse generating means. Using the pulse as a trigger, it is determined whether or not the predictive medium pulse is obtained again during a period of an integral multiple of the synchronization signal.If the predictive medium pulse is obtained, the next predictive medium pulse is further obtained. Medium pulse It is determined whether or not it can be obtained, and when the next predictive intermediate pulse is obtained, synchronization control for reproducing digital data is performed using a detected synchronization signal or a signal synchronized with the detected synchronization signal as a control signal. And a synchronization circuit. 3. A synchronizing signal detecting means for detecting the synchronizing signal from digital data having a frame structure composed of digital data including a synchronizing signal and having a sector structure in which a plurality of the frames are aggregated, and the synchronizing signal detecting means. A synchronous signal that counts a clock signal of a constant frequency in synchronization with the output of the synchronization signal, predicts a time for detecting the next synchronization signal, and outputs a window signal indicating a detection period of the synchronization signal within a certain period around the predicted time. A signal detection and prediction circuit, and means for performing synchronization control for digital data reproduction using the synchronization signal or a signal synchronized with the synchronization signal as a control signal when the synchronization signal is detected during the window signal. In the synchronization circuit, when the synchronization signal is detected in the shortest detection cycle of the window signal, a prediction error pulse is generated. A pulse generation unit, when the predictive middle pulse from the predictive middle pulse generator is measured as a trigger and during the period of an integral multiple of the synchronization signal, the predictive middle pulse is obtained a plurality of times. A synchronous circuit for performing synchronous control for reproducing digital data by using a detected synchronous signal or a signal synchronized with the detected synchronous signal as a control signal. 4. A synchronizing signal detecting means for detecting a synchronizing signal from digital data having a frame structure composed of digital data including a synchronizing signal and having a sector structure in which a plurality of the frames are aggregated; A synchronous signal detection and prediction circuit that counts a clock signal of a constant frequency in synchronization with the output of the detection means, predicts a time for detecting the next synchronous signal, and generates a window signal within a predetermined period before and after the predicted time. And a synchronization circuit that performs synchronization control for reproducing digital data using the synchronization signal or a control signal synchronized with the synchronization signal when a synchronization signal is detected during the window signal. First hit pulse generating means for generating a first predictive hit pulse when the sync signal is detected in the detection cycle of: A second hit pulse generating means for detecting a synchronization signal before and after a temporal position whose position is predicted using a second window signal having a wider period than the window signal; In the case of a period of an integral multiple of the synchronization signal measured using the predictive medium pulse from the medium pulse generating means as a trigger, when the predictive medium pulse is obtained again,
Means for performing synchronization control for reproduction of digital data, using a detection synchronization signal or a signal synchronized with the detected synchronization signal as a control signal; and During the period of the integer multiple of the measured synchronization signal, it is determined whether the predictive medium pulse is obtained a plurality of times, if the predictive medium pulse is obtained a plurality of times, the detection synchronization signal Means for performing synchronization control for reproducing digital data using a signal synchronized with the detected synchronization signal as a control signal.