JPH11161613A - Electronic computer, computing method, and record medium storing computing process program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow the electronic computer not to immediately display the calculation result of an inputted fractional expression, but to let a user experientially master a process wherein the fractional expression is simplified by reduction. SOLUTION: When an arbitrary fractional expression is inputted with keys and displayed at a liquid crystal display part 16 and a 'reduction' key 12c is operated, the retrieval of the greatest common measure between denominators and numerators by fractional terms and the retrieval of the greatest common measure between the denominators and numerators of fractional terms in multiplication relation are performed in previously set retrieval order after mixed fraction/improper fraction and division/multiplication conversion, and numerals of combinations of the denominator and numerator whose greatest common measure is detected first are blinked and displayed as a reducible point. When the 'reduction' key 12c is repeatedly operated, the numerals of the denominator and numerator at the blinked and displayed reducible point are reduced and a next reducible point by the similar retrieval of the greatest common measure is blinked an displayed, so that a calculation result is derived and displayed by operating a '=' key 12d for a fractional expression which is simplified until it can not be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic computer for calculating and displaying fractions, a calculation method, and a recording medium storing a calculation processing program.

[0002]

2. Description of the Related Art Conventionally, in an electronic computer having a function of calculating a fraction, for example, when an arbitrary fractional expression is input and an execution of calculation is instructed, a reduction process, a commutation process and the like are executed by an internal calculation process. Then, only the finally calculated answer is displayed on the display screen as a calculation result.

[0003]

However, in the above-mentioned conventional electronic computer, when an arbitrary fractional expression is inputted and displayed and an operation for instructing a calculation is performed, a series of fractional calculation processes are immediately executed and only the answer is given. Is displayed, for example, when this computing device is used as an educational device, the actual given fraction formula, such as how the fractional process and the fractional process can be performed specific to the fraction, is used. There is a problem that the process of simplifying and calculating cannot be learned through experience.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems. Instead of displaying the calculation result of an inputted fractional expression immediately, the user can experience the process of simplifying the fractional expression by using a reduced number. It is an object of the present invention to provide a recording medium on which an electronic computer, a calculation method, and a calculation processing program that can be learned are recorded.

[0005]

That is, in the electronic computing device according to claim 1 of the present invention, when a fractional expression is input,
The entered fractional expression is displayed, a set of divisible numbers in the displayed fractional expression is searched, and a set of dividable numbers in the retrieved fractional expression is identified and displayed. Therefore, it is possible to confirm a divisible part in the fractional expression.

In the electronic computer according to a second aspect of the present invention, in the electronic computer according to the first aspect, the search for the divisible part is performed by the instruction means for instructing the search for the divisible part. Each time it is instructed, a set of numbers that can be reduced in the fractional expression is sequentially searched and identified and displayed.
It is possible to arbitrarily select a reduction target portion in the fractional expression.

According to a third aspect of the present invention, there is provided the electronic computer according to the first or second aspect, further comprising: Is reduced, and if a set of numbers that can be reduced is not searched for in the mathematical expression, the calculation result of the mathematical expression is derived. You can do it.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of an electronic circuit of the electronic computing device according to the embodiment of the present invention.

This electronic computer has a control unit (CPU) 11 composed of a computer or the like. Control unit (CP
U) 11 causes the recording medium reading unit 17 to read a system program stored in the ROM 13 or a computer control program stored in the external recording medium 18 in advance in response to a key operation signal from the key input unit 12. And controls the operation of each part of the circuit using the RAM 14 as a work memory.

The control unit (CPU) 11 includes the key input unit 12, the ROM 13, the recording medium reading unit 17,
The AM 14 is connected, and the liquid crystal display unit 16 is connected via the display drive circuit 15.

The key input unit 12 is provided with a data input key 12a composed of various numeric / symbol key groups such as numeric keys, operator keys, function keys, and fraction symbol keys.
Calculation mode for performing normal calculation processing corresponding to any input formula, function calculation mode for performing function calculation processing corresponding to any input formula, fraction calculation corresponding to any input fractional expression A "mode" key 12b which is operated when selecting and setting various operation modes such as a fraction calculation mode for performing a process, and which is operated when instructing a fraction processing to a fraction formula input and displayed in the fraction calculation mode. A "minute" key 12c, an "=" key 12d operated to derive and display a calculation result, and an "execution" key 12 operated to instruct setting of selected data and execution of calculation
e, Cursor keys "↑", "↓", "←" operated when moving the cursor or selecting data on the display screen
“→” 12f, a return key “△” 12g operated when returning the display data in the calculation process to the previous formula state and displaying the data in the calculation mode in each calculation mode, and changing the display data in the calculation process to the latter formula state An advance key "@" 12h or the like which is operated when the image is advanced and displayed is provided.

In the fraction calculation mode, the advance key "@" 12h is used to sequentially search for combinations of numerical values that can be reduced in the input fractional expression one by one according to a preset search procedure. Operated when searching and blinking.

FIG. 2 is a diagram showing an example of a procedure for searching for a divisible part with respect to a fraction formula set in advance in the electronic computer. That is, the search procedure of the divisible function for the fractional expression in the fraction calculation mode of the electronic computer is set in advance as shown in, for example, FIGS. 2A, 2B, and 2C. First, the denominator and the greatest common divisor between numerators of each fractional term of the input fractional expression are sequentially searched, and secondly, each fraction having a multiplication relationship (or converted). The denominator of the terms and the greatest common divisor between the numerators are set so as to be sequentially searched.

The ROM 13 stores in advance system program data that governs the overall processing of the electronic circuit of the present electronic computer, and also includes calculation processing related to the fraction calculation mode shown in FIGS. Control program data, which is subprogram data that governs processing in various calculation modes, is also stored in advance.

The RAM 14 stores a display data memory 14a in which display data to be displayed on the liquid crystal display 16 in the various calculation modes is developed and stored as bitmap pattern data, and input formula data. Expression data obtained by performing conversion of mixed fractions → provisional fractions, conversion of division → multiplication, conversions of approximations, common divisions, etc. with respect to the fraction formulas stored in the input formula memory 14b and the input formula memory 14b are converted for each conversion process. , A denominator in a fractional expression sequentially stored and calculated in the input expression memory 14b and the conversion expression memory 14c, and a numerical value of a divisible divisor that has the greatest common divisor between the numerators Is stored as the designation data of the numerical value to be blinked and displayed, the control address associated with the control processing of various calculation modes. Part work memory 14e for temporarily storing data input and output by (CPU) 11, and mode data indicating the calculation mode set by the mode selection is provided a memory area such as a mode data memory M to be stored.

Next, the operation of the electronic computer having the above configuration will be described. FIG. 3 is a flowchart showing a fraction calculation process of the electronic computer. FIG. 4 is a flow chart showing a reduction process accompanying the fraction calculation process of the electronic computer.

(Calculation Example 1) FIG. 5 is a diagram showing a calculation display state of a fractional expression including a mixed fraction and a division accompanying the fraction calculation process of the electronic computer.

As shown in FIG. 5A, the key input unit 12
Is selectively operated, and an arbitrary fractional expression to be calculated is "2 (7/5) @ 14/10 + 2 /
When "3" is input, the input formula data of the fractional expression is sequentially stored in the input formula memory 14b in the RAM 14, written into the display data memory 14a, and displayed on the liquid crystal display unit 16 (step S1). → S2, S4).

When the fractional expression including the fractional number and the division is input and displayed, as shown in FIG. 5B, when the "about" key 12c of the key input section 12 is operated, 4
Is started (step S3 → SB).

Then, first, it is determined from the data format of the expression data stored in the input expression memory 14b that the expression is a fractional expression, and the designation of numerical value blinking display in the blinking designation data memory 14d is performed on the minute expression. The presence / absence is determined (step B1 → B2).

Here, if it is determined that there is no designated data for numerically blinking display for the fractional expression stored in the expression data memory 14b, the fractional term "2 (7/5)" of the mixed fraction is changed to the fraction of the provisional fraction. Is converted to the term “17/5”, and further, the set of fraction terms related to division “17/5 ÷ 14/10” is converted to the set of fraction terms for multiplication “17/5 × 10/14”, and the conversion formula For the memory 14c, "17/5 × 10/14 + 2 /
3 "(steps B2 → B3, B4).

Then, with respect to the latest fraction formula stored in the conversion formula memory 14c, first, the denominator and the greatest common divisor between the numerators for each fractional term of the fraction formula are searched (step). B5).

That is, "17/5" → "October 14" →
The denominator for each fraction term and the greatest common divisor between the numerators are sequentially searched for "2/3". In this case, "10/1
When it is determined that the greatest common divisor “2” has been retrieved between the denominator and the numerator of “4”, the storage addresses of the numerical values of the denominator and the numerator of the fraction term “10/14” are stored in the blinking designation data memory 14d. As shown in FIG. 5B, the corresponding numerical values “14” and “10” of the denominator and the numerator are blinkingly displayed as the first combination searched as being approximately divisible (steps B6 → B7). ).

As shown in FIG. 5C, when the "approximately minutes" key 12c is operated in the state where the first numerical value blinking display that can be reduced is displayed, the conversion type memory 14c is displayed. Stored in the latest fraction formula “17/5 × 10/14 + 2 /
3 ”, it is determined that there is a denominator“ 14 ”and a numerator“ 10 ”blinking in the mathematical formula, and the blinking numerical value“ 14 ”is present in the fractional formula. "10" is reduced by the retrieved greatest common divisor "2" (step S3 → SB <B1).
→ B2 → B11>). Then, the latest fraction formula “17/5 × 5/7 + 2/3” that has been reduced is stored in the conversion formula memory 14c, written into the display data memory 14a, and displayed on the liquid crystal display unit 16. (Step B
12).

Then, the conversion type memory 14c
Stored in the latest fraction formula “17/5 × 5/7 + 2 /
A search process for the denominator for each fraction term and the greatest common divisor between the numerators for "3" is executed (step B5).

That is, “17/5” → “5/7” → “2
// 3 "and the denominator for each fraction term and the greatest common divisor between the numerators are sequentially searched. In this case, if it is determined that there is no search for the greatest common divisor in each of the fraction terms, second, the denominator of each of the fraction terms having a multiplication relationship and the greatest common divisor between the numerators are searched (step B6 → B8, B9).

That is, when the greatest common divisor “5” is searched in the denominator and the numerator of each fraction term of “17/5 × 5/7”, the largest common divisor “5” is searched. The storage addresses of the numerical values of the denominator "5" of one item and the numerator "5" of the second item are stored in the blinking designation data memory 14d, and as shown in FIG. "5" and "5" are searched as possible approximations, respectively.
Flashing display as the first combination (step B1
0 → B7).

As shown in FIG. 5D, when the "approximately minute" key 12c is further operated in the state where the second numerical value blinking display capable of reducing the number is displayed, the conversion type memory is displayed. 1
4c stored in the latest fraction formula “17/5 × 5/7 + 2”.
/ 3 ”, it is determined that the expression is a fractional expression.
It is determined that there is a denominator “5” of the first item and a numerator “5” of the second item, which are blinkingly displayed in the fraction formula,
The blinking denominator “5” and the numerator “5” are reduced by the retrieved greatest common divisor “5” (step S3 → SB <B1 → B2 → B11>). Then, the latest divided mathematical expression "17/1 × 1/7 + 2"
/ 3 "is stored in the conversion memory 14c, written into the display data memory 14a, and displayed on the liquid crystal display 16 (step B12).

Then, the conversion type memory 14c
Stored in the latest fraction formula “17/1 × 1/7 + 2 /
3 ”for the first greatest common divisor (step B
5) The second greatest common divisor is searched (step B9), and any combination of the denominator, numerator, and denominator of each of the fraction terms related to multiplication and the numerator is performed. If it is determined that the greatest common divisor is not retrieved, the divisor processing is terminated as it is (steps B5, B6 → B8 → B
(9, 10 → end), the latest fraction formula “17/1 × 1/7 + 2/3” remains displayed without any blinking numerical value meaning that there is no combination of numerical values that can be reduced. (Step SB → S4).

As shown in FIG. 5E, the "=" key 12d of the key input unit 12 is operated in a state in which all of the divisible parts are sequentially shown and processed in each case. And whether or not there is a combination of numerical values that can be reduced to a fraction, with respect to the latest fraction formula “17/1 × 1/7 + 2/3” stored in the conversion formula memory 14c. Is determined, and if a combination of numerical values that can be reduced is searched through the search processing of the first and second greatest common divisors as described above, the relevant numerical value is designated by blinking and displayed (step S5 → S6 → S7 → S8 → S
4).

In this case, the latest fraction formula "17/1 × 1/7 + 2/3" stored in the conversion formula memory 14c.
Then, it is determined that there is no combination of numerical values that can be reduced, and it is determined whether or not it is possible to divide between the mathematical expressions (steps S7 → S9).

Then, the above-mentioned fractional expression "17/1 × 1/7 +
With respect to “2/3”, it is determined that the denominator is “21” and it is determined that the separation is possible.
21 + 14/21 "is stored in the conversion memory 14c and displayed on the liquid crystal display 16 (step S10).
→ S4).

When the "=" key 12d is operated, as shown in FIG.
4c stored in the latest fraction formula “51/21 + 14/2”.
After determining whether there is a fraction, cannot be divided, or cannot be performed, the calculation process is executed on the target "1", the calculation result "65/21" is stored in the conversion formula memory 14c, and the liquid crystal display unit is displayed. 16 (Steps S5 → S6 →
S7 → S9 → S11 → S4).

As a result, the input fractional formula is displayed by flashing the dividable portions individually and sequentially processed by the divisor, and further processed by the divisor into the simplest fraction formula. After the conversion and display, the calculation result is derived and displayed.

(Calculation Example 2) FIG. 6 is a diagram showing a calculation display state of a fractional expression including division accompanying the fraction calculation process of the electronic computer.

As shown in FIG. 6A, the key input unit 12
Is operated selectively, and an arbitrary fractional expression to be calculated is input as “3/5 × 5/6 ÷ 7/10”, the input expression data of the fractional expression is stored in the RAM 14.
Are sequentially stored in the input type memory 14b, and are written in the display data memory 14a and displayed on the liquid crystal display unit 16 (steps S1 → S2, S4).

With the fractional expression including the division being input and displayed, as shown in FIG.
Is operated, the reduction processing shown in FIG. 4 is started (step S3 → SB).

Then, first, it is determined from the data format of the expression data stored in the input expression memory 14b that the expression is a fractional expression. The presence / absence is determined (step B1 → B2).

Here, if it is determined that there is no designated data for blinking the numerical value for the fractional expression stored in the expression data memory 14b, the conversion of the mixed fraction (no target) is performed and then the division is performed. A set of fraction terms “5/6 ÷ 7/1
“0” is converted into a set of multiplication fraction terms “5/6 × 10/7”, and “3/5 × 5/6 × 1” is stored in the conversion expression memory 14c.
0/7 ”(steps B2 → B3, B
4).

Then, with respect to the latest fraction formula stored in the conversion formula memory 14c, first, the denominator for each fractional term of the fraction formula and the greatest common divisor between numerators are searched (step). B5).

That is, “3/5” → “5/6” → “10
/ 7 ”and the denominator for each fractional term and the greatest common divisor between the numerators are sequentially searched. In this case, if it is determined that there is no search for the greatest common divisor in each of the fraction terms, second, the denominator of each of the fraction terms having a multiplication relationship and the greatest common divisor between the numerators are searched (step B6 → B8, B9).

That is, the numerator “5” of “5/6” and the numerator “1” of “5/7” with respect to the denominator “5” of “3/5”
“0”, → the numerator “3” of “3/5” and the numerator “10” of “10/7” for the denominator “6” of “5/6” →→ “10 /
The numerator “3” of “3/5” for the denominator “7” of “7”,
The denominator of each fractional term and the greatest common divisor between the numerators are sequentially searched, such as the numerator "5" of "5/6". First, "5/6" for the denominator "5" of "3/5"
When the first greatest common divisor “5” is searched for the numerator “5”, the denominator “5” of the searched first item of the greatest common divisor “5” and the numerator of the second item The storage address of each numerical value of "5" is stored in the blinking designation data memory 14d, and as shown in FIG. 6B, the corresponding numerical values "5" and "5" of the denominator and the numerator can be reduced to approx. 1 found
Flashing display as the first combination (step B1
0 → B7).

As shown in FIG. 6 (C), when the "minute" key 12c is further operated in the state where the first numerical value blinking display capable of reducing the number is displayed, the conversion type memory is displayed. 1
4c stored in the latest fraction formula “3/5 × 5/6 × 10
/ 7 ”, it is determined that the expression is a fractional expression.
It is determined that there is a denominator “5” of the first item and a numerator “5” of the second item, which are blinkingly displayed in the fraction formula,
The blinking denominator “5” and the numerator “5” are reduced by the retrieved greatest common divisor “5” (step S3 → SB <B1 → B2 → B11>). Then, the latest divided mathematical expression “3/1 × 1/6 × 10
/ 7 ”is stored in the conversion formula memory 14c, written into the display data memory 14a, and displayed on the liquid crystal display unit 16 (step B12).

Then, the conversion type memory 14c
First, the denominator and the greatest common divisor between the numerators of each fractional term of the fractional expression are searched for the latest fractional expression stored in (1) (step B5).

That is, this time, “3/1” → “1/6”
→ The denominator for each fraction term and the greatest common divisor between the numerators are sequentially searched for "10/7". In this case, when it is determined that there is no search for the greatest common divisor in each of the fraction terms, second, the denominator of each of the fraction terms having a multiplication relation and the greatest common divisor between the numerators are set in the same manner as described above. (Steps B6 → B8, B9).

In the preset search process,
When the second greatest common divisor “3” is searched between the denominator “6” of “1/6” and the numerator “3” of “3/1”, the search for the greatest common divisor “3” is performed. The storage addresses of the respective values of the denominator “6” of the second item and the numerator “3” of the first item are stored in the blinking designation data memory 14d, and FIG.
As shown in (C), the respective values “6” and “3” of the corresponding denominator and numerator are searched as being approximately divisible.
Flashing display as the first combination (step B1
0 → B7).

As shown in FIG. 6D, when the "about" key 12c is further operated in the state where the second numerical value blinking display capable of being reduced is displayed, the conversion type memory is displayed. 1
4c stored in the latest fraction formula “3/1 × 1/6 × 10
/ 7 ”, it is determined that the expression is a fractional expression.
It is determined that there is a denominator “6” of the second item and a numerator “3” of the first item, which are blinking in the fraction formula,
The blinking denominator “6” and the numerator “3” are reduced by the searched greatest common divisor “3” (step S3 → SB <B1 → B2 → B11>). Then, the latest divided mathematical expression “1/1 × 1/2 × 10
/ 7 ”is stored in the conversion formula memory 14c, written into the display data memory 14a, and displayed on the liquid crystal display unit 16 (step B12).

Then, the conversion type memory 14c
First, the denominator and the greatest common divisor between the numerators of each fractional term of the fractional expression are searched for the latest fractional expression stored in (1) (step B5).

That is, this time, “1/1” → “1/2”
→ The denominator for each fraction term and the greatest common divisor between the numerators are sequentially searched for "10/7". In this case, when it is determined that there is no search for the greatest common divisor in each of the fraction terms, second, the denominator of each of the fraction terms having a multiplication relation and the greatest common divisor between the numerators are set in the same manner as described above. (Steps B6 → B8, B9).

In the preset search process,
When the third greatest common divisor “2” is searched between the numerator “10” of “10/7” with respect to the denominator “2” of “1/2”, the search for the greatest common divisor “2” is performed. The storage addresses of the respective numerical values of the denominator “2” of the second item and the numerator “10” of the third item are stored in the blinking designation data memory 14d, and FIG.
As shown in (D), the corresponding numerical values “2” and “10” of the denominator and the numerator are blinkingly displayed as the third combination searched as being approximately divisible (step B).
10 → B7).

As shown in FIG. 6 (E), when the third numerical value blinking display that can be reduced is performed, as shown in FIG. 1
4c stored in the latest fractional expression “1/1 × 1/2 × 10
/ 7 ”, it is determined that the expression is a fractional expression.
It is determined that the denominator “2” of the second item and the numerator “10” of the third item are displayed blinking in the fraction formula, and the denominator “2” and the numerator “10” are displayed blinking.
Is reduced by the searched greatest common divisor “2” (step S3 → SB <B1 → B2 → B11>). Then, the latest divided mathematical expression "1/1 × 1/1"
× 5/7 ”is stored in the conversion memory 14c,
The data is written into the display data memory 14a and the liquid crystal display 16
(Step B12).

Then, the conversion type memory 14c
The latest fractional expression "1/1 x 1/1 x 5/7" stored in
For the first greatest common divisor (step B
5) The second greatest common divisor is searched (step B9), and any combination of the denominator, numerator, and denominator of each of the fraction terms related to multiplication and the numerator is performed. If it is determined that the greatest common divisor is not retrieved, the divisor processing is terminated as it is (steps B5, B6 → B8 → B
(9, 10 → end), the latest fraction formula “1/1 × 1/1 × 5/7” is displayed without any blinking numerical value which means that there is no combination of numerical values that can be reduced. (Step SB → S4).

As shown in FIG. 6 (F), the "=" key 12d of the key input unit 12 is operated in a state in which all of the dividable parts are sequentially shown and processed in each case. And the latest fraction formula “1/1 × 1/1 × 5/7” stored in the conversion formula memory 14c is determined to be a fraction, and a combination of numerical values that can be reduced Is determined, and when a combination of numerical values that can be reduced is searched through the search processing of the first and second greatest common divisors as described above, the corresponding numerical value is designated by blinking and displayed. (Steps S5 → S6 → S7 → S8 → S
4).

In this case, in the latest fraction formula “1/1 × 1/1 × 5/7” stored in the conversion formula memory 14c, it is determined that there is no combination of numerical values that can be reduced. It is determined whether division is possible between the fractional expressions (step S7 → S9).

Then, the above-mentioned fractional expression “1/1 × 1/1 × 5”
After a determination is made as to whether or not communication is possible with respect to "/ 7", a calculation process is executed, and the calculation result "5/7" is stored in the conversion formula memory 14c and displayed on the liquid crystal display unit 16 ( Steps S9 → S11 → S4).

As a result, in the input fractional expression, the possible divisors are blinked and displayed individually, and the divisors are sequentially processed and displayed. After being converted and displayed as a fractional expression, the calculation result is derived and displayed.

In this electronic computing device, the latest mathematical expression stored in the input-type memory 14b or the conversion-type memory 14c is compared with the advance key “１２” 12h in the key input unit 12 for each operation. In accordance with a search procedure of the previously set greatest common divisor similar to the above, only the search for a divisible part and its blinking display process are sequentially repeated,
Arbitrary combinations of numerical values that perform a reduction in a fractional expression can be arbitrarily selected.

FIG. 7 is a flow chart showing the "@" key processing accompanying the fraction calculation processing of the electronic computer. FIG. 8 is a diagram showing a search and display state of a divisible potential portion associated with the "@" key process in the fraction calculation process of the electronic computing device.

When the advance key "@" 12h in the key input section 12 is operated in the process of the fraction calculation process in FIG. The process (“▽” key process) is executed (step S12 → SC).

That is, for example, as shown in FIG. 8A, an arbitrary fractional expression “3/5 × 5/6 ÷ 7/10” is input with the selection operation of the data input key 12a, and the input expression While being stored in the memory 14b, it is displayed on the liquid crystal display unit 16 (steps S1 → S2, S4).
As shown in (B), when the “reduction” key 12c is operated (step S3 → SB), the division / multiplication conversion processing (steps B1 to B4) and the first reduction possible portion are performed. The search blinking display process is performed, and the converted minute expression “3 /
In the state stored in the conversion-type memory 14c as “5 × 5/6 × 10/7” (steps B5 to B10 → S4), FIG.
As shown in FIG. 3C, when the advance key "@" 12h in the key input unit 12 is operated, the conversion type memory 14c is operated.
A search and display process (“▽” key process) of a divisible potential portion with respect to the minute formula “3/5 × 5/6 × 10/7” stored in (1) is started (step S12 → SC).

When it is determined that there is designation data for numerical blinking display in the blinking designation data memory 14d for the fractional expression "3 / 5.times.5 / 6.times.10 / 7" stored in the conversion formula memory 14b, According to a preset search procedure for the divisible factor, the greatest common divisor between each denominator and the numerator other than the first flashable dividable location (see FIG. 8B) is searched. (Step C1 → C2orC
3 → C5 → C6).

That is, the following is the numerical combination of the denominator “5” of the fraction term “3/5” having the greatest common divisor “5” currently blinking and the numerator “5” of the fraction term “5/3”. The greatest common divisor “5” is searched between the denominator “5” of the fraction term “3/5” and the numerator “10” of the fraction term “10/7”, which is a numerical combination between the numerators. The designation data of blinking display for the denominator “5” and the numerator “10” is stored in the blinking designation data memory 14d, and the combination of the corresponding numerical values in the displayed fractional expression is, as shown in FIG. As the second divisible potential part, the first dividable part <FIG. 8 (C)> is flashed and displayed (steps C1 → C2, C3 → C5 → C6, C7 → C4).

Further, when the advance key "@" 12h of the key input unit 12 is operated, the next numerical combination between the denominator and the numerator having the greatest common divisor is sequentially searched for each key operation. As shown in FIG. 8 (D), a blinking display of a third divisible part, a blinking display of a fourth divisible part, and a divisible part one after another as shown in FIG. 8 (E). Search and its blinking display are repeated (step S12 → S
C).

As a result, it is possible to arbitrarily select a combination of numerical values for executing the reduction in the fractional expression. Therefore, according to the electronic computing device having the above-described configuration, an arbitrary fractional expression is key-input and displayed on the liquid crystal display unit 16, and “about minutes” is displayed.
When the key 12c is operated, the conversion process from the mixed fraction to the improper fraction and the conversion of the fractional term related to the division into the form of multiplication are performed. The denominator of the fraction terms related to the multiplication and the greatest common divisor between the numerators are searched according to a preset search order. Is flashed as a possible divisor, and when the "approximately" key 12c is repeatedly operated, the numerical values of the denominator and the numerator of the flashable divisible are reduced, and then the same as above. Of the next possible divisor is displayed by searching for the greatest common divisor, and the “=” key 12 for the simplified minute formula which is not divisible.
Since the calculation result is derived and displayed by the operation of d, for example, when this electronic computing device is used as an educational device, the actually given fractional expression is simplified and reduced to be calculated. You can learn the process experientially.

Further, according to the electronic computer having the above configuration,
When the advance key “▽” 12h is operated in a state where any of the divisible parts of the fractional expression are blinking and displayed, the search order of the greatest common divisor set in advance is determined for each key operation.
Combinations between denominators and numerators that can be reduced are searched sequentially,
Since the corresponding combination of numerical values is displayed blinking, it is possible to arbitrarily select a combination of numerical values that executes the reduction in the minute formula.

Further, according to the electronic computer having the above configuration,
By repeatedly operating the "approximately minute" key 12c, search display and possible reduction processing of successively divisible points are sequentially performed. Since the minute expression processing is also performed to simplify the minute expression, it is possible to learn the process of simplifying the given minute expression as much as possible.

The method described in the above embodiment, that is, each method such as the fraction calculation processing shown in the flowcharts of FIGS. 3, 4, and 7 is a program that can be executed by a computer as a memory card (RO).
M card, RAM card, etc.), magnetic disk (floppy disk, hard disk, etc.), optical disk (CD-
External recording medium 1 such as ROM, DVD, and semiconductor memory
8 and can be distributed. Then, the computer reads the program recorded on the external recording medium 18 by the recording medium reading unit 17, and the operation is controlled by the read program, so that the dividable expression of the fractional expression described in the embodiment can be reduced. , A blinking display, a fraction calculation function such as about minutes, passing minutes, etc., can be realized, and similar processing by the above-described method can be executed.

[0068]

As described above, according to the electronic computer according to the first aspect of the present invention, when a fractional expression is input, the entered fractional expression is displayed, and the entered fractional expression is displayed. The set of divisible numbers is searched, and the set of divisible numbers in the searched fractional expression is identified and displayed.
It is possible to confirm a divisible part in a fractional expression.

According to a second aspect of the present invention, there is provided the electronic computer according to the first aspect of the present invention, wherein the instructing means for instructing the search for the divisible part is used to specify the divisible part. Each time a search is instructed, a set of numerical values that can be reduced in the fractional expression is sequentially searched and identified and displayed, so that a reduction target portion in the fractional expression can be arbitrarily selected.

According to a third aspect of the present invention, there is provided the electronic computer according to the first or second aspect, further comprising: If the set of numerical values is reduced and the set of numerical values that can be reduced in the mathematical expression is not searched, the calculation result of the mathematical expression is derived, so that the mathematical expression is simplified as much as possible. Calculation can be performed.

Thus, according to the present invention, the calculation result of the input fractional expression is not immediately displayed, but it is possible to experience the process of simplifying the fractional expression by reducing it.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an electronic circuit of an electronic computing device according to an embodiment of the present invention.

FIG. 2 is an exemplary diagram showing an example of a procedure for detecting a divisible portion with respect to a preset fractional expression in the electronic computing device.

FIG. 3 is a flowchart showing a fraction calculation process of the electronic computer.

FIG. 4 is a flowchart showing a reduction process accompanying the fraction calculation process of the electronic computer.

FIG. 5 is a diagram showing a calculation display state of a fractional expression including a mixed fraction and a division involved in a fraction calculation process of the electronic computing device.

FIG. 6 is a diagram showing a calculation display state of a fractional expression including a division involved in a fraction calculation process of the electronic computing device.

FIG. 7 is a flowchart showing “▽” key processing accompanying the fraction calculation processing of the electronic computing device.

FIG. 8 is a diagram showing a search display state of a divisible potential portion associated with a “▽” key process in the fraction calculation process of the electronic computing device.

[Explanation of symbols]

 11: control unit (CPU), 12: key input unit, 12a: data input key, 12c: "minute" key, 12d: "=" key, 12g: "▽" key, 13: ROM, 14: RAM, 14a: display data memory, 14b: input type memory, 14c: conversion type memory, 14d: conversion designation data memory, 14e: work memory, 16: liquid crystal display unit, 17: recording medium reading unit, 18: external recording medium.

Claims (5)

[Claims] An input means for inputting a fractional expression, a display means for displaying the fractional expression input by the input means, and a set of divisible numerical values in the fractional expression displayed on the display means are searched. And a display control means for identifying and displaying a set of dividable numerical values in the fractional expressions searched by the reduced part search means. . 2. The dichotomous point search means has instructing means for instructing a search for a divisible part, and each time a search for a divisible part is instructed by the instruction means, 2. The electronic computing device according to claim 1, wherein the electronic computing device is a reduced part search means for sequentially searching a set of numerical values that can be reduced. 3. A reduction means for reducing a set of divisible values in the fractional expression identified and displayed by the display control means; and 2. A calculating means for deriving a calculation result of the fractional expression when a set of numerical values that can be reduced is not retrieved.
Or the electronic computing device according to claim 2. 4. A display step of displaying a fractional expression input by the input means on a display unit, and a reduced part search step of searching for a set of divisible values in the displayed fractional expression in the display step. A display control step of identifying and displaying a set of divisible numbers in the fractional expression searched in the reduced part search step. 5. A computer, comprising: display means for displaying an inputted fractional expression; reduced part search means for retrieving a set of divisible values in the fractional expression displayed on the display means; A recording medium on which a calculation processing program for functioning as display control means for identifying and displaying a set of numerical values that can be reduced in a fractional expression searched by a search means is displayed.