JPH11161542A - Rom reading circuit and rom reading method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a ROM reading circuit capable of more speedily performing a response to a host and accelerating the operating speed of a system as a whole. SOLUTION: This circuit is provided with a counter 2 for outputting the next address to a ROM 5 beforehand for the continuously accessed addresses. In this case, in the case that the address from the host is the same as the address of the counter 2, data pertinent to the address are immediately outputted from the ROM 5 to a data bus. In the case that the address from the host is different from the address of the counter 2, the address of the counter 2 is abandoned, a new address on an address bus is fetched and outputted to the ROM 5, the extension of access time is requested to the host until the host becomes able to read the output data of the ROM 5 and the data pertinent to the new address are outputted from the ROM 5 to the data bus after it becomes readable.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ROM readout circuit and a ROM readout method for making a response to a higher order faster and for speeding up the entire system.

[0002]

2. Description of the Related Art Conventionally, in a computer system, a system operating according to a program written in a ROM in advance operates while reading the program from the ROM.

FIG. 3 is a block diagram showing an example of a conventional ROM read circuit. FIG. 4 is a timing chart showing the operation of FIG.
3 shows an operation when the address on the address bus is an access to the ROM 5.

[0004] First, when an address is transmitted from the upper level to the address bus, it is directly transmitted to the ROM 5 and the decoder 1. The decoder 1 determines that the address transmitted from the upper
It is determined whether the address condition for access to OM5 is met. In this cycle, ROM5
, The decoder 1 outputs an active signal. The ROM 5 recognizes an access from a higher order when a signal output from the decoder 1 is input to a CS terminal.

After sending the address, the upper order sends a memory read signal. The AND circuit 6 that has received the memory read signal outputs an active signal because the memory read signal and the signal from the decoder 1 become active.
When this signal is input, the ready signal generation circuit 7 sends out a ready signal, and requests the higher order to extend the access time until the data output from the ROM 5 becomes readable. The memory read signal is
Since the active signal has already been input to the CS terminal, the ROM 5 outputs data corresponding to the previously received address. The buffer 4 inputs the active signal output from the AND circuit 7 to the EN terminal, and transmits the data transmitted from the ROM 5 onto the data bus.

The ready signal generation circuit 8 returns the ready signal to the timing when the ROM 5 starts sending data corresponding to the address on the address bus, and urges the higher order to complete the access time.

When the ready signal returns, the host begins to complete the cycle. When the host returns the memory read signal to its original state, the buffer 4 stops sending the data sent from the ROM 5 onto the data bus because the signal to the EN terminal becomes inactive.
5 stops sending data.

Cycle 24 shows the operation when the address on the address bus is not an access to ROM 5. When the memory read signal becomes active after the address is transmitted from the upper level to the address bus, the decoder 1 does not output the signal because the access is not to the ROM 5 in this case. Therefore, the buffer 4 is stored in the ROM 5
Is not sent out on the data bus, so there is no effect on the data bus.

[0009]

The above-mentioned conventional ROM
The read circuit has a problem that the access speed of the ROM is not high as compared with the higher speed. For this purpose, as described above, the ready signal generation circuit sends the ready signal to the higher order, and extends the access time to the higher order until the data output from the ROM becomes readable. I have.

It is an object of the present invention to provide a ROM read circuit and a ROM read method for making a response to a higher order faster and for speeding up the entire system.

[0011]

According to the present invention, there is provided a ROM reading circuit comprising: a ROM for outputting a memory content corresponding to an address input to an address terminal to a data terminal; and an input address corresponding to an address for accessing the ROM. A decoder that outputs an active signal while the condition is met, an AND circuit that outputs an active signal only when a memory read signal and a signal from the decoder are active, and a signal that is input from the AND circuit Sends data from the ROM onto the data bus only while is active, and a buffer that sends nothing on the data bus when the signal input from the AND circuit is inactive. Always outputs the held address, and when the signal input from the AND circuit becomes inactive, A counter for incrementing the address held therein, and when the signal input from the AND circuit becomes active, compares the content of the address input from the address bus with the content of the address input from the counter, A compare circuit that outputs an active pulse only when the active signal is input from the compare circuit, and outputs a ready signal that extends an upper operation cycle until the upper data can be read from the ROM when an active signal is input from the compare circuit. A ready signal generation circuit, wherein when the signal input from the compare circuit becomes active, the counter discards the held address and takes in a new address on the address bus.

According to the present invention, a next address to a continuously accessed address is sent to the ROM in advance, so that a response to a higher order is made faster and the whole system is made faster.

[0013]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a ROM reading circuit according to the present invention. ROM shown in FIG.
The read circuit includes a decoder 1, a counter 2, a compare circuit 3, a buffer 4, a ROM 5, an AND circuit 6, and a ready signal generating circuit 7.

[0015] The decoder 1 outputs the address RO
An active signal is output while the address condition for access to M5 is met. The counter 2 always outputs the held address. Also, counter 2
Increments the address held when the signal input to the CLK terminal becomes non-active,
When the signal input to the AD terminal becomes active, the held address is discarded and a new address on the address bus is fetched.

The compare circuit 3 compares the contents of the A terminal and the B terminal when the signal input to the CLK terminal becomes active, and outputs an active pulse only when the signals are different. The buffer 4 sends the data from the ROM 5 onto the data bus only while the signal input to the EN terminal is active. If the signal at the EN terminal is non-active, the buffer 4 Also do not send.

When the signals input to the CS terminal and the OE terminal become active, the ROM 5 outputs the contents of the memory corresponding to the address input to the address terminal to the data terminal. The AND circuit 6 outputs an active signal only when two inputs are active. When an active signal is input, the ready signal generation circuit 7
A signal for extending the higher-order operation cycle until the data output by M5 becomes readable is output as a ready signal.

Next, the operation of the embodiment of FIG. 1 will be described with reference to the drawings. FIG. 2 is a timing chart in the embodiment of the present invention.

Since the CS terminal and the OE terminal of the ROM 5 are always fixed in an active state, the ROM 5 always outputs data according to the input address.

Cycle 11 shows the operation when the address on the address bus matches the address condition for accessing the ROM 5, but is different from the address stored in the counter 2.

First, when an address is transmitted from the upper level onto the address bus, the decoder 1 determines whether or not the address transmitted from the upper level matches the address condition for accessing the ROM 5. In the case of cycle 11, since the access to the ROM 5 is made, the decoder 1
Outputs an active signal. Thereafter, when the memory read signal sent from the upper level becomes active, the AND circuit 6 outputs an active signal because the memory read signal and the signal from the decoder 1 become active.

However, in the compare circuit 3, when the signal input to the CLK terminal becomes active, the address on the address bus and the address held in the counter 2 are different. Output a simple pulse. When this pulse is input, the counter 2 discards the address held so far and holds the address currently on the address bus. When this pulse is input, the ready signal generation circuit 7 sends out a ready signal, and requests the higher order to extend the access time until the data output from the ROM 5 becomes readable.

When the signal from the AND circuit 6 is input to the EN terminal, the buffer 4 sends the data sent from the ROM 5 onto the data bus. At this time, the ROM 5
The data corresponding to the address on the address bus has not been transmitted.

When the ROM 5 receives from the counter 2 the same address as the address currently on the address bus,
The data corresponding to the address is output. At this time, since the buffer 4 has already received the signal from the AND circuit 6, the buffer 4 immediately outputs the data sent from the ROM 5 onto the data bus. The ready signal generation circuit 7
At the timing when M5 starts sending data corresponding to the address on the address bus, the ready signal is returned to the original state, and the host is urged to complete the access time.

When the ready signal returns, the host begins to complete cycle 11. When the host returns the memory read signal, the AND circuit 6 returns the output signal to non-active. At this time, the counter 2 increments the currently held address and prepares for the next access. For this reason, the ROM 5 tries to send data corresponding to the incremented address,
However, since the signal input to the EN terminal has returned to non-active, no data is transmitted, so that there is no effect on the data bus.

Cycles 12 and 13 are when the address on the address bus is an access to the ROM 5 and is the same as the address held in the counter 2, that is, when the next address is accessed following the cycle 11. The operation of FIG.

Similarly to the cycle 11, when the memory read signal becomes active after the address is transmitted from the upper address onto the address bus, the access to the ROM 5 is also performed in this cycle. However, since the address on the address bus is the same as the address held in the counter 2, the compare circuit 3 does not output a signal. Therefore, the ready signal generation circuit 7
No ready signal is output to the upper
Outputs the held address as it is. Since a signal is input to the EN terminal of the buffer 4, the cycle 1
As in 1, the data transmitted from the ROM 5 is transmitted onto the data bus.

Since the ROM 5 has received the same address as the address currently on the address bus from the counter 2 before the cycles 12 and 13 begin, the ROM 5 has begun to output data corresponding to the address. Buffer 4
Has already been input to the EN terminal,
The data sent from M5 is immediately output on the data bus.

As in the case of cycle 11, when the higher level returns the memory read signal to non-active, the AND circuit 6 returns the output signal to non-active. Cycle 11
Similarly, the counter 2 increments the currently held address and prepares for the next access.
Attempts to send data corresponding to the incremented address, but does not affect the data bus.

Cycle 14 shows the operation when the address on the address bus is not an access to ROM 5.

When the memory read signal becomes active after the address is transmitted from the host to the address bus, the decoder 1 does not access the ROM 5 in this case, so that the decoder 1
Does not output a signal. Therefore, buffer 4 contains RO
Since the data from M5 is not transmitted on the data bus, there is no effect on the data bus. Further, the counter 2 does not increment the held address.

[0032]

As described above, the present invention provides the RO
In a system operated by a program written in M, the next address for a continuously accessed address is sent to the ROM in advance, and the time required for data output from the low-speed ROM is apparently reduced. , Access from the host can be made faster, and the entire system can be made faster.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a ROM read circuit of the present invention.

FIG. 2 is a timing chart according to the embodiment of the present invention.

FIG. 3 is a block diagram showing an example of a conventional ROM read circuit.

FIG. 4 is a timing chart showing the operation of a conventional ROM read circuit.

[Explanation of symbols]

 Reference Signs List 1 decoder 2 counter 3 compare circuit 4 buffer 5 ROM 6 AND circuit 7 ready signal generation circuit

Claims (6)

[Claims] 1. A counter for outputting a next address to a ROM in advance for an address continuously accessed, and when an address transmitted from a higher order is the same as an address output from the counter, the address is immediately output from the ROM. The data corresponding to the address is output on the data bus, and if the address transmitted from the upper side is different from the address output by the counter, the address held by the counter is discarded and a new address on the address bus is discarded. The address is fetched into the counter and output to the ROM, and the data output from the ROM is requested to extend the access time to the higher order until the higher order becomes readable. ROM reading characterized by outputting data corresponding to various addresses on a data bus Circuit. 2. A ROM for outputting a memory content corresponding to an address input to an address terminal to a data terminal, and an active signal while the input address matches an address condition for accessing the ROM. A decoder that outputs an output signal; a logical product circuit that outputs an active signal only when a memory read signal and a signal from the decoder are active; and a logical product circuit that outputs a signal from the ROM only while a signal input from the logical product circuit is active. When the data is sent out on the data bus, and the signal input from the AND circuit is inactive, a buffer that sends nothing on the data bus and the held address are always output, A counter that increments the address held when the signal input from the AND circuit becomes inactive. A ROM readout circuit comprising: 3. When the signal input from the AND circuit becomes active, the contents of the address input from the address bus and the contents of the address input from the counter are compared. A compare circuit for outputting, and a ready signal generation circuit for outputting a ready signal for extending an upper operation cycle until an upper signal becomes readable when an active signal is input from the compare circuit, The ROM reading circuit according to claim 2, further comprising: 4. The counter according to claim 3, wherein when the signal input from the compare circuit becomes active, the counter discards the held address and takes in a new address on an address bus. ROM reading circuit. 5. An address which is successively accessed is set in the ROM in advance, and when an address transmitted from a higher order is the same as the address set in the ROM, the address is immediately transferred from the ROM to the address. The corresponding data is output on the data bus, and if the address transmitted from the upper level is different from the address set in the ROM, the address set in the ROM is discarded and a new address on the address bus is discarded. In a ROM, and after the upper layer becomes readable, data corresponding to a new address is output from the ROM to a data bus. 6. When the address set in the ROM is discarded and a new address on the address bus is set in the ROM, the data output from the ROM is transferred to the upper address by the time until the upper bit becomes readable. 6. The ROM reading method according to claim 5, wherein the access time is requested to be extended.