JPH11154677A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the manufacturing method of a semiconductor device, which can suppress the film-thickness difference of the interlayer insulating films after polishing, depending on the roughness and fineness of the ground pattern of interlayer insulating films without especially increasing the number of processes, when the interlayer insulating film is planarized by CMP(chemical- mechanical polishing). SOLUTION: When an interlayer insulating film 12 is formed on a semiconductor substrate 10 on which an element or wiring 11 is formed, the following processes are provided: a process which sets an upper region 122 having a film thickness or more which corresponds to a ground step different of the interlayer insulating film at least at the upper part of in the interlayer insulating film, so that the impurity density becomes higher than a lower region 121 other than the region 122 and a process which planarizes the surface of the interlayer insulating film through CMP.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for flattening an element and an interlayer insulating film on a wiring in a semiconductor device having a multilayer wiring structure.

[0002]

2. Description of the Related Art In a semiconductor device, a multilayer wiring technique is indispensable in order to increase the degree of integration. However, as wiring dimensions become finer, flatness due to a base step formed in an interlayer insulating film deteriorates. Such deterioration in the flatness of the interlayer insulating film makes it difficult to perform a lithography step and a processing step when forming a wiring on the interlayer insulating film and a through hole in the interlayer insulating film.

[0003] Therefore, a resist etch back method in which the underlying step of the interlayer insulating film is filled in advance with a resist having a high fluidity and is etched under the condition that there is no selectivity with the interlayer insulating film, or a chemical using a polishing material and a polishing pad. Chemical mechanical polishing (Chemical M polishing) to mechanically polish and flatten the surface of an interlayer insulating film
mechanical polishing (CMP) is used.

FIGS. 2A to 2C show steps of a conventional example of a method of planarizing the surface of an interlayer insulating film by CMP. First, a wiring 31 is formed on a semiconductor substrate 30 after element formation as shown in FIG. 2A, and then an interlayer insulating film 32 is deposited as shown in FIG. As shown, the surface of the interlayer insulating film 32 is polished and flattened by CMP.

However, the above-described resist etch-back method and CMP can eliminate the occurrence of local steps in the interlayer insulating film 32. However, when the interlayer insulating film 32 having a uniform thickness is deposited, the underlying Due to the density, the etching of the interlayer insulating film 32 proceeds rapidly in a wide space, and a thickness difference Δd of the interlayer insulating film 32 occurs in the entire wafer.

Accordingly, when a through hole is formed in the interlayer insulating film 32 and a wiring is formed on the interlayer insulating film 32,
This causes deterioration of the focus margin in the lithography process, variation in the depth of the through hole, and a reduction in the yield.

In order to solve such a problem, as shown in FIG. 3, a method of arranging a dummy pattern 41 in a space of a large space of a base pattern of an interlayer insulating film 32, or as shown in FIG. In addition, a method of arranging the etching stopper 51 in a portion of the interlayer insulating film 32 where a large space is provided in the underlying pattern has been considered.

However, in these methods, the number of steps for forming the dummy pattern 41 and the etching stopper 51 increases, and the method for arranging the dummy pattern 41 and the etching stopper 51 according to the base pattern for each different semiconductor device. There is a problem that the design is required and the wiring capacitance increases.

[0009]

As described above, according to the conventional method of flattening the surface of an interlayer insulating film, the etching of the interlayer insulating film proceeds quickly in a wide space due to the density of the underlying pattern, and the entire wafer is not etched. The thickness difference of the interlayer insulating film occurs, and when a wiring on the interlayer insulating film and a through hole of the interlayer insulating film are formed, a focus margin is deteriorated in a lithography process, and a variation in a depth of the through hole is caused. There was a problem that caused the yield to drop.

In order to solve the above-mentioned problem, a method of arranging a dummy pattern or an etching stopper in a large space of an underlying pattern of an interlayer insulating film is performed by a process for forming a dummy pattern and an etching stopper. And a design for arranging a dummy pattern or an etching stopper is required for each different semiconductor device, and there is a problem that a wiring capacity increases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and when the interlayer insulating film is planarized by CMP,
In particular, it is an object of the present invention to provide a method of manufacturing a semiconductor device capable of suppressing a difference in thickness of an interlayer insulating film after polishing depending on the density of a base pattern of the interlayer insulating film in a self-aligning manner without increasing the number of steps. I do.

[0012]

According to a method of manufacturing a semiconductor device of the present invention, when an interlayer insulating film is formed on a semiconductor substrate on which elements or wirings have been formed, at least an interlayer insulating film is formed above the interlayer insulating film. A step of setting the upper region having a thickness equal to or greater than the film thickness corresponding to the base step of the insulating film to have a higher impurity concentration than the other lower region; and a step of flattening the surface of the interlayer insulating film by chemical mechanical polishing. It is characterized by having.

[0013]

Embodiments of the present invention will be described below in detail with reference to the drawings. The present invention is based on the fact that the chemical reaction rate with the CMP polishing material changes according to the concentration of impurities introduced into the interlayer insulating film, and the change in the density of the interlayer insulating film causes the mechanical polishing of CMP. The focus was on the fact that the ease of change was known.

FIGS. 1A to 1C show an embodiment of a process of forming an interlayer insulating film according to a method of manufacturing a semiconductor device according to the present invention. First, as shown in FIG. 1A, an element such as a MOS transistor and an entire surface of a semiconductor substrate (wafer) 10 processed and formed up to an n-th layer wiring 11 as shown in FIG. Then, an interlayer insulating film 12 such as a SiO ₂ (silicon oxide) film or a TEOS (tetraethoxysilane) film is deposited with a uniform thickness by a CVD (chemical vapor deposition) method.

At this time, B introduced into the interlayer insulating film 12
A region (upper region 122) in which the concentration of an impurity such as (boron), P (phosphorus), or F (fluorine) is equal to or more than the film thickness corresponding to at least the underlying step of the interlayer insulating film in the upper part of the film.
Is set to be different from the other film thickness regions (lower region 121).

The setting for providing a difference in the impurity concentration of the interlayer insulating film 12 can be realized by adjusting the flow rate of the impurity gas introduced during the CVD. It is possible to make the impurity concentration of the upper region 122 of the interlayer insulating film 12 higher than that of the lower region 121 by increasing the amount of the introduction.

Next, as shown in FIG. 1 (c), the surface of the interlayer insulating film 12 is planarized by CMP. The convex portion of the interlayer insulating film 12 is polished faster because it is easier to be mechanically polished than the concave portion.

Therefore, at the convex portion of the interlayer insulating film 12,
A portion having a lower impurity concentration (a portion having a higher chemical reaction rate with the CMP polishing material) than the surface portion of the interlayer insulating film 12 is exposed earlier than the concave portion.

As described above, during the polishing, the CM where the base pattern exists and the space where the base pattern does not exist are separated.
There is a state where the impurity concentration on the surface of the interlayer insulating film 12 to be flattened by P is different.

At this time, the polishing rate of the surface of the interlayer insulating film 12 is increased in the portion of the interlayer insulating film 12 where the underlying pattern exists (the portion where the mechanical polishing is easy and the impurity concentration is low). In a space portion where there is no (a portion where mechanical polishing is difficult to be performed and the impurity concentration is high), the polishing rate of the surface of the interlayer insulating film 12 becomes slow. As a result, as shown in FIG. The difference in the thickness of the interlayer insulating film after polishing, which depends on the density of the underlying pattern of the film, is suppressed.

That is, according to the above embodiment, when the interlayer insulating film 12 is formed on the semiconductor substrate 10 on which the elements and the wirings 11 are formed, at least the interlayer insulating film 12 The upper region 122 having a thickness equal to or greater than the thickness of the underlying step is set so as to have a higher impurity concentration than the other lower region 121, and the number of steps is not increased. During CMP, the difference in film thickness of the polished interlayer insulating film, which depends on the density of the underlying pattern of the interlayer insulating film, can be suppressed in a self-aligned manner.

Moreover, since it is not necessary to dispose a dummy pattern or an etching stopper in a large space of the underlying pattern of the interlayer insulating film, the number of steps for forming the dummy pattern and the etching stopper is increased, or a different semiconductor is used. It is not necessary to design a dummy pattern or an etching stopper for each device, or to increase the wiring capacity.

Note that the step of the interlayer insulating film 12 before the CMP as described above depends not only on the density of the underlying wiring pattern but also on the element formed on the semiconductor substrate. The same method as that of the embodiment can be applied.

The change in the impurity concentration in the interlayer insulating film 12 as described above can also be realized by ion-implanting impurities to a predetermined depth in the interlayer insulating film after the deposition of the interlayer insulating film.

[0025]

As described above, according to the present invention, CMP
In the planarization of the interlayer insulating film by the method described above, a semiconductor device capable of self-aligningly suppressing a difference in film thickness of a polished interlayer insulating film depending on the density of an underlying pattern of the interlayer insulating film without increasing the number of steps. A manufacturing method can be provided.

[Brief description of the drawings]

FIG. 1 is a sectional view showing one embodiment of a step of forming an interlayer insulating film according to a method of manufacturing a semiconductor device of the present invention.

FIG. 2 is a cross-sectional view showing steps of a conventional example of a method of planarizing the surface of an interlayer insulating film by CMP.

FIG. 3 is a cross-sectional view showing a conventional method of arranging a dummy pattern in a portion of a base pattern of an interlayer insulating film having a large space.

FIG. 4 is a cross-sectional view showing a conventional method of arranging an etching stopper in a portion of a base pattern of an interlayer insulating film having a large space.

[Description of Reference Numerals] 10: wafer (semiconductor substrate), 11: wiring, 12: interlayer insulating film, 121: lower region of interlayer insulating film, 122: upper region of interlayer insulating film.

Claims (3)

[Claims] When an interlayer insulating film is formed on a semiconductor substrate on which an element or a wiring is formed, an upper region in the upper portion of the interlayer insulating film that is at least a thickness corresponding to a base step of the interlayer insulating film. A step of setting the impurity concentration to be higher than that of the other lower region, and a step of flattening the surface of the interlayer insulating film by chemical mechanical polishing. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the step of setting a difference in impurity concentration in the interlayer insulating film comprises:
A method for manufacturing a semiconductor device, comprising: adjusting a flow rate of an impurity gas introduced when depositing and forming an interlayer insulating film by a chemical vapor deposition method. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the step of setting a difference in impurity concentration in the interlayer insulating film includes:
A method of manufacturing a semiconductor device, characterized in that impurities are ion-implanted to a predetermined depth in the interlayer insulating film after the formation of the interlayer insulating film.