JPH1115430A - Electric field emission display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electric field emission display device relatively easily realizing a multi-level display. SOLUTION: This device is provided with an FED device main body 1 provided with a display substrate arranged with a pixel Pij having an electric field emission type emitter in matrix, and formed with gate wiring commonly driving the pixels in the row direction and emitter wiring commonly driving the electric field emission emitters in the column direction, and a counter substrate arranged oppositely on this display substrate and formed with an anode electrode and a fluorescent body film, a gate drive circuit 2 successively supplying a gate voltage pulse to the gate wiring and an emitter drive circuit 3 supplying an emitter voltage pulse deciding an emitter emission current value of each pixel together with the gate voltage pulse synchronized with the gate voltage pulse to the emitter wiring. At this time, the emitter drive circuit 3 generates the emitter voltage pulse combining pulse width control corresponding to M-level with pulse amplitude control answering to N-level and containing M×N-level of information.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a field emission display device which performs multi-tone display using a display substrate on which minute field emission type emitters are formed and arranged.

[0002]

2. Description of the Related Art In recent years, as a flat panel display, a field emission display (FED) using a small emitter as an electron source has been developed.
Emission Display) is attracting attention. The FED is composed of a display substrate on which a plurality of pixels having a field emission type emitter driven by a gate electrode are formed and arranged, and an opposite substrate on which an anode electrode and a phosphor film are formed facing the display substrate. You. The space between the display substrate and the counter substrate is evacuated. A plurality of gate lines that commonly drive the pixels in the row direction on the display substrate and a plurality of emitter lines that commonly drive the field emission emitters of the pixels in the column direction are taken out. Then, for example, while sequentially driving the gate wiring, synchronously, by applying image data for each line to the emitter wiring, a so-called line-sequential driving image display is performed.

In this type of FED, when displaying a full-color image, R (red), G (green), and B (blue)
Are formed by forming phosphor films for R, G, and B on an anode electrode facing the field emission type emitter of each of the R, G, and B dots as three pixels of the three primary color dots as one pixel. You. As the emitter wiring on the display electrode, three lines for R, G and B are arranged per pixel.

For example, by sequentially applying a positive gate voltage pulse (for example, +25 V) to the gate wiring,
Selection is performed line by line, and in synchronization with this, a negative emitter voltage pulse (for example, −25 V) is applied to each emitter wiring according to image data. +2 for gate wiring
In a dot where 5 V is applied and -25 V is applied to the emitter wiring, the gate-emitter voltage becomes 50 V and electrons are emitted at the tip of the emitter, and the electrons are generated on the anode electrode side where a high positive voltage is applied. Light is emitted by hitting the phosphor film. The gradation display of FED is
PWM (pulse width modulation) of the above emitter voltage pulse
It becomes possible by controlling the pulse width as a pulse.

[0005]

However, the FED
In the above, gray scale display by pulse width control of the emitter voltage pulse described above is relatively easy up to about 16 gray scales, but it is difficult to perform multi-gray scale display. For example, 6
When displaying 40 × 480 pixels at a frame frequency of 60 Hz and trying to realize 256 gradations by controlling the pulse width of the emitter voltage pulse, the emitter voltage pulse is expressed as
A unit pulse width of 1 / (60 × 480 × 256) = 135 [nsec] is required. At this time, the rise and fall times are 13.5 [nsec] as 1/10 of the pulse width. It is difficult to switch a high voltage pulse of -25 V at such a high speed using a normal MOS transistor in the output stage of the emitter line driver, and the power consumption becomes extremely large.

[0006] Instead of the pulse width control, it is conceivable to perform gradation display by variably controlling the gate-emitter voltage using an emitter voltage pulse as a PAM (pulse amplitude modulation) pulse. Not realistic to get. In the field emission type emitter, the relationship between the gate-emitter voltage and the emission current shows a non-linear characteristic (diode characteristic) in which the current rises sharply at about 30 V, so that the gate-emitter voltage is reduced to divide the emission current into 256. In addition, it is very difficult to divide the image into 256 at unequal intervals in terms of circuit.

The present invention has been made in consideration of the above circumstances, and has as its object to provide a field emission display device which can realize multi-tone display relatively easily.

[0008]

According to the present invention, there is provided a field emission type display device in which a plurality of pixels having a field emission type emitter driven by a gate electrode are arranged in a matrix, and a plurality of pixels which commonly drive pixels in a row direction are arranged. A display substrate on which a plurality of emitter wirings for commonly driving field emission emitters in the column direction are formed, and a counter substrate disposed opposite to the display substrate and having an anode electrode and a phosphor film formed thereon. A display device main body; gate driving means for sequentially supplying a gate voltage pulse to the plurality of gate lines; and an emitter emission current of each pixel together with the gate voltage pulse in synchronization with the gate voltage pulse to the plurality of emitter lines. Emitter driving means for supplying an emitter voltage pulse for determining a value, the emitter driving means comprising:
As the emitter voltage pulse, an M × N gradation defined by pulse width control corresponding to M gradations (M is an arbitrary integer) and pulse amplitude control corresponding to N gradations (N is an arbitrary integer) An emitter voltage pulse generator is provided for each emitter line for generating a pulse waveform containing information.

In the present invention, for example, the display device main body is for displaying a full-color image in which each pixel is composed of R, G, and B dots. It is assumed that a phosphor film constituting B dots is formed, and that the display substrate has three emitter lines for R, G and B per pixel as a plurality of emitter lines.

In the present invention, the emitter voltage pulse generating means may control the amplitude of the reference pulse by controlling the amplitude value by 1/2 ^m of the reference amplitude value in the lower m bits of the gradation data represented by n bits. P that generates pulse voltage of width
AM pulse generating means, and the upper (n-
m) a PWM pulse generating means for generating a pulse voltage having the reference amplitude value by controlling a pulse width in a range of 2 ^(nm) times the reference pulse width by bits, and a PAM pulse generating means and a PWM pulse generating means. And a synthesizing means for generating a pulse voltage obtained by synthesizing the output pulse voltage of the means in the time axis direction.

In the FED device according to the present invention, as the emitter voltage pulse, a pulse waveform including M × N gradation information by combining M gradation by pulse width control and N gradation by pulse amplitude control. By using
Multi-tone display control, which is difficult only with pulse width control or pulse amplitude control, can be realized relatively easily. For example, M = 1
It is also easy to perform 256 gradation display with 6, N = 16. The pulse voltage including the gradation information in the pulse width and the pulse amplitude as described above is, for example, PAM pulse generation means and PW
It can be made by combining M pulse generating means. That is, when the grayscale data is n bits, the PAM pulse generation means uses the lower M bits to １ ／ the reference amplitude value.
Generates a pulse voltage of reference pulse width whose amplitude value is controlled by ^m . In the PWM pulse generation means, the upper (nm)
A pulse voltage having a reference amplitude value in which the pulse width is controlled in a range of 2 ^(nm) times the reference pulse width by bits is generated. By synthesizing these pulse voltages in the time axis direction, n
It is possible to obtain a generally stepped pulse voltage including bit gradation data. In the case of 256 gradations, n = 8 and m = 4, and the pulse amplitude of 16 gradations and 1
A step-like pulse voltage is obtained by combining pulse widths of six gradations.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows the overall configuration of an FED device according to one embodiment, FIG. 2A shows a layout of four pixels on the display substrate 10 side of the FED main body 1, and FIG. 2 shows a cross-sectional structure of the FED main body 1 at the position AA ′.

As shown in FIG. 2B, the FED main body 1 includes a display substrate 10 and an opposing substrate 20 disposed opposite to the display substrate. The display substrate 10 is, for example, a silicon substrate 1
1 and a plurality of pixels P as shown in FIG.
ij (i = 1 to p, j = 1 to q) are arranged in a matrix. Each pixel Pij is composed of R, G, and B dots, and for example, four field emission emitters (hereinafter simply referred to as emitters) 12 each having a sharp tip in each dot region are formed. FIG. 2B shows only one emitter 12 for each dot for convenience.

The emitter wirings 13 (131R, 131G, 131B,...) For commonly driving the emitters 12 in the column direction are separated from each other by an insulating film 15, and three R, G, and B lines are arranged for each pixel. , And are taken out to the outside as emitter terminals E (E1R, E1G, E1B,...). Gate wirings (electrodes) 14 (141, 142,...) For commonly driving the respective emitters 12 in the row direction are formed on the substrate 11 via the insulating film 16, and holes for exposing the respective emitters 12 are processed. I have. Each gate wiring 14 is taken out as a gate terminal G (G1, G2,...).

The opposing substrate 20 is a transparent substrate 21 made of glass or the like.
And an anode electrode 22 made of a transparent conductive film such as ITO is formed on the surface thereof. On the anode electrode 22, R, G, and B corresponding to the R, G, and B dots of each pixel Pij are respectively provided. B phosphor film 23 (23R, 23G, 23
B) is formed. Although not shown, the space between the display substrate 10 and the counter substrate 20 is vacuum-sealed with a sealing material such as low-melting glass. In this case, preferably, a getter material such as a barium alloy or a zirconium alloy is sealed inside the FED main body 1.

As shown in FIG. 1, a gate drive circuit 2 for sequentially supplying a gate voltage pulse to a gate terminal G, and a drive circuit for the FED main body 1 having the above-described structure, An emitter driving circuit 3 for supplying an emitter voltage pulse corresponding to image data to the emitter terminal E is provided. The controller 4 controls the synchronization of the gate drive circuit 2 and the emitter drive circuit 3. Normally, in the case of performing line-sequential image display, image data of one line is sequentially sent to the emitter drive circuit 3, and image data constituting one line are simultaneously given to q × 3 emitter terminals E, One gate terminal G is selectively driven by the gate drive circuit 2 to display an image of one line. Thereafter, the gate terminal G is selectively driven sequentially for image data of one line.

FIG. 3 shows a gate terminal G and an emitter terminal E.
3 shows the operating voltage waveform of the embodiment. As shown in the figure, a positive gate voltage pulse having a pulse width τ is sequentially applied to the gate terminal G, and the pulse width τ becomes a display time of one line, and within this time, the emitter terminals E of R, G, and B are applied. Is supplied with a negative emitter voltage pulse modulated by gradation data. In the case of this embodiment, the emitter voltage pulse is obtained by combining the pulse width control corresponding to the M gray scale with the pulse amplitude control corresponding to the N gray scale, where M and N are arbitrary integers. Is a pulse waveform including information of M × N gradation defined by the width and the voltage value (amplitude).
In other words, as shown in FIG. 4, the pulse waveform is formed by stacking the hatched unit pulses in the range of M in the amplitude direction and the range of N in the pulse width direction in accordance with the degree of gradation. Is generally formed as a staircase waveform as shown by a solid line.

FIG. 5 shows a specific example of one pulse generating circuit 30 for generating the above-mentioned emitter voltage pulse in accordance with the grayscale data in the emitter driving circuit 3. The pulse generation circuit 30 converts the grayscale data into n bits (2 ⁿ
Circuit section for generating a PAM pulse having a reference pulse width and controlling the amplitude value by 1/2 ^{m of the} reference amplitude value from the lower m bits of data as the gradation, and decoding the upper (nm) bits And a circuit for generating a PWM pulse whose pulse width is controlled in a range of 2 ^(nm) times the reference pulse width. The circuit section that generates the PAM pulse is D
/ A converter 31 and PAM circuit 3 for generating a PAM pulse having a reference pulse width having an amplitude value corresponding to the output of the A / A converter 31
3, and a log amplifier 3 that logarithmically converts the amplitude value of the obtained PAM pulse so that a linear emitter current is obtained.
And 4. Further, the circuit unit that generates the PWM pulse using the upper (nm) bits is a PWM decoder 3
2. Output of log amplifier 34 and PWM
An analog adder 35 is used to combine the outputs of the decoder 32 in the time axis direction to obtain a staircase-like emitter voltage pulse.
Is provided. This pulse generation circuit 30 includes R,
It is provided for each of the G and B emitter terminals E.

Specifically, n = 8 (that is, 256 gradations)
FIG. 6 shows the waveforms of the output of the PAM circuit 33 and the output of the PWM decoder 32 when m = 4. PAM circuit 33
Is a pulse having a reference pulse width W0 whose amplitude value is controlled in steps of 1/16 of the reference amplitude value P0 according to the lower four bits A0 to A3 of the gradation data. The output of the PWM decoder 32 is the upper 4 bits A4 to A4 of the gradation data.
According to 7, the pulse has a reference amplitude value P0 whose pulse width is controlled in 16 steps in a range of the reference pulse width of 0 to 15W0. By combining these pulses in the time axis direction, it can be seen that 16 × 16 = 256 different emitter voltage pulses defined by different amplitudes and widths can be obtained.

The above-mentioned reference pulse width W0 is selected such that the maximum pulse width 15 × W0 of the obtained voltage pulse corresponds to the gate voltage pulse width τ shown in FIG. Also,
The reference amplitude value P0 to the minimum amplitude value P0 / 16 are divided and set within a voltage range where an emission current can be obtained within the breakdown voltage limit.

The amplitude of the PAM pulse obtained from the PAM circuit 33 changes linearly. However, the emission current is not proportional to the gate-emitter voltage, and has an exponential function as shown in FIG. From such an emission current-voltage characteristic, the emission current is I1, I2
The amplitude control of the emitter voltage pulse is performed so that the gate-emitter voltages V1, V2,..., V16 are equally divided as shown in FIG. 6, ie, PAM shown in FIG. It is necessary to perform amplitude control so that the amplitude steps of the circuit output are unequally spaced. The log amplifier 34 performs this amplitude control. That is, by passing the PAM pulse through the log amplifier 34, the exponential function characteristic of the emission current is corrected, and a linear characteristic that the current (= luminance) is proportional to the input voltage can be obtained.

The reason why the output current becomes linear by using the PAM pulse passed through the log amplifier 34 will be specifically described as follows. Normally, a gate voltage Vg that does not emit electrons alone is applied to the gate of the FED as a scanning voltage, and an emitter voltage Ve is applied to the scanning voltage. The gate-emitter voltage Vge is expressed by the following equation (1).

[0023]

Vge = Vg + | Ve |

When no amplitude modulation is performed, the gate voltage Vg
Is Vg, where Vemax is the maximum value of the emitter voltage Ve.
= | Vemax |. At this time, the emission current I is represented by the following exponential function.

[0025]

I = I0.exp [k1 (| Vemax | + | Ve |)]

When the voltage Vd of the PAM pulse for gradation output from the PAM circuit 33 in FIG. 5 is passed through the log amplifier 34, the obtained emitter voltage becomes the following equation (3).

[0027]

| Vemax | + | Ve | = k2 · log (Vd)

By substituting equation (3) for equation (2), the following equation (4) is obtained.

[0029]

## EQU4 ## I = I0.exp (k1, k2.log (V
d)) = I0 · k1 · k2 · Vd

As is apparent from Equation 4, the log amplifier 3
4, the luminance can be made proportional to the input voltage Vd.

FIG. 7 shows an example of the output waveform of each part in FIG. In the PWM decoder 32, any one of the PWM pulses having a pulse width of 0 to 15W0 is obtained within a period of 16W0.
As described above, a PAM pulse whose amplitude value is converted at irregular intervals is obtained from the log amplifier 34, and a pulse obtained by synthesizing them is obtained from the adder 35. The output of the adder 35 changes in units of the basic pulse width W0 along the time axis. For example, 640 × 480 pixels are converted to a frame frequency of 60
When displaying in Hz, the basic pulse width W0 is 1 / (60
× 480 × 16) = 2.17 [μsec]. Assuming that the rise and fall times are 1/10 of the pulse width,
217 [nsec], and switching can be easily performed. Further, since the pulse amplitude is also subjected to the PAM control, it does not change in units of 25 V, so that the power consumption is reduced.

For reference, FIG. 9 shows data obtained by applying a DC voltage between the gate and the emitter and setting the anode voltage to 0 V and measuring the emission current in the prototype FED. Specifically, it is an average characteristic obtained by measuring all the current-voltage characteristics of 384 points on the FED of the 24 × 16 pixel matrix. The display area of the FED is 4.8 mm x 9.6
mm, and the phosphor is coated with three colors of RGB and sealed with low melting point glass. The emitter material is TiN.

According to this embodiment, the gradation control is performed by the combination of the pulse width and the amplitude of the emitter voltage pulse, so that the multi-gradation such as 256 gradations, which cannot be realized by the control of the pulse width alone or the control of the amplitude alone. Control becomes possible. That is, in a full-color display in which each of R, G, and B has 256 gradations, 256 × 256 × 256 = 1,67
Display control of 7,216 colors becomes possible.

[0034]

As described above, according to the present invention, a multi-gradation display is provided by providing means for generating an emitter voltage pulse for performing a gradation display by a combination of pulse width control and pulse amplitude control. F that can be easily realized
An ED device can be obtained.

[Brief description of the drawings]

FIG. 1 is a diagram showing an overall configuration of an FED according to an embodiment of the present invention.

FIG. 2 is a layout and cross-sectional view of a display substrate side of the FED device main body of the embodiment.

FIG. 3 is a diagram showing operation waveforms of the FED device of the embodiment.

FIG. 4 is a diagram showing a configuration principle of an emitter voltage pulse of the embodiment.

FIG. 5 is a diagram illustrating a configuration example of an emitter voltage pulse generation circuit according to the same embodiment.

FIG. 6 is a diagram showing an output waveform of each part of the emitter voltage pulse generation circuit.

FIG. 7 is a diagram showing an output waveform of each part of the emitter voltage pulse generation circuit.

FIG. 8 is a diagram showing emission current-voltage characteristics of the example.

FIG. 9 is a diagram showing emission current characteristics of a prototype FED.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... FED device main body, 2 ... Gate drive circuit, 3 ... Emitter drive circuit, 4 ... Controller, 10 ... Display board, 12
... Field emission emitters, 13 emitter wirings, 14 gate wirings, 20 counter substrate, 22 anode electrodes, 23
... Phosphor film, 30 ... Emitter voltage pulse generation circuit, 31
... D / A converter, 32 ... PWM decoder, 33 ... P
AM circuit, 34 ... log amplifier, 35 ... analog adder.

Claims (4)

[Claims] A plurality of pixels having a field emission type emitter driven by a gate electrode are arranged in a matrix, and a plurality of gate lines for commonly driving pixels in a row direction and a plurality of pixels for commonly driving a field emission emitter in a column direction. A display substrate on which a plurality of emitter wirings are formed, a display device main body having a counter substrate disposed opposite to the display substrate and having an anode electrode and a phosphor film formed thereon, and a gate voltage sequentially applied to the plurality of gate wirings A gate driving unit for supplying a pulse; and an emitter driving unit for supplying an emitter voltage pulse to the plurality of emitter lines together with the gate voltage pulse to determine an emitter emission current value of each pixel in synchronization with the gate voltage pulse. The emitter driving means includes, as the emitter voltage pulse, a pulse width control corresponding to M gradations (M is an arbitrary integer). And an emitter voltage provided for each emitter wiring to generate a pulse waveform including information of M × N gradation defined by pulse control and pulse amplitude control corresponding to N gradations (N is an arbitrary integer) A field emission display device comprising pulse generation means. 2. The display device main body according to claim 1, wherein each of the pixels is for displaying a full-color image including R, G, and B dots, and R, G, and B dots are provided for each pixel on an anode electrode of the counter substrate. 2. A field emission device according to claim 1, wherein a constituent phosphor film is formed, and each of said plurality of emitter wires of said display substrate has three emitter wires for R, G and B per pixel. Type display device. 3. The emitter voltage pulse generation means controls the pulse voltage having a reference pulse width by controlling an amplitude value by 1/2 ^m of a reference amplitude value in lower m bits of gradation data represented by n bits. A PAM pulse generating means for generating, and a pulse width of 2 ^(nm) times the reference pulse width is controlled by upper (nm) bits of the gradation data to generate a pulse voltage of the reference amplitude value. 2. A PWM pulse generating means for generating a pulse voltage, wherein said PAM pulse generating means and a synthesizing means for generating a pulse voltage obtained by synthesizing output pulse voltages of said PWM pulse generating means in a time axis direction.
Field emission display device as described in the above. 4. The PAM pulse generating means includes: a D / A converter that converts lower-order m-bit data of the grayscale data into an analog value; 1/1 of a reference amplitude value according to an output of the D / A converter.
4. The field emission display according to claim 3, further comprising: a PAM circuit that generates a pulse voltage having a reference pulse width whose amplitude value is controlled by 2 ^m; and a log amplifier that logarithmically converts an output of the PAM circuit. apparatus.