JPH1115426A - Capacitive load drive circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a capacitive load drive circuit with simple and inexpensive constitution. SOLUTION: One end of a capacitive load Cp is grounded, and the other end is connected to an inductor L1. A parallel circuit between a serial circuit of a switch element SW1 with a diode D1 and the serial circuit of the switch element SW2 with the diode D2 is connected to the inductor L1, and a power collecting capacitor C1 is connected to this parallel circuit. The switch elements SW3, SW4 are connected to the capacitive load Cp, and the switch element SW11 switching a positive source Vcc with a negative source -Vcc is connected to the switch element SW3. The switch element SW12 switching the positive source (1/2) Vcc with the negative source -(1/2) Vcc is connected to the capacitor C1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitive load driving circuit for charging and discharging a capacitive load used in a driving device of a plasma display panel (PDP). The present invention relates to a capacitive load drive circuit.

[0002]

2. Description of the Related Art In an alternating current (AC) type PDP, two types of pulses (sustain discharge pulses) having phases shifted from each other by 180 degrees are applied to two types of electrodes, respectively. Therefore, AC
A conventional capacitive load drive circuit used for a type PDP needs to include two sustain discharge pulse generation circuits.

FIG. 10 is a circuit diagram showing an example of a conventional capacitive load drive circuit, FIGS. 11 and 12 are waveform diagrams for explaining the operation of the conventional capacitive load drive circuit, and FIG. 13 is a conventional capacitive load drive circuit. 3 is an equivalent circuit diagram of FIG. In FIG. 10, a capacitive load driving circuit includes a first sustain discharge pulse generating circuit 1;
And a second sustain discharge pulse generating circuit 2. The first and second sustain discharge pulse generating circuits 1 and 2 are each provided with a capacitive load C.
connected by p. The capacitance load Cp is one pixel in the AC type PDP, and is also called a panel capacitance.

The first sustain discharge pulse generating circuit 1 includes a capacitor C1, diodes D1 and D2, an inductor L1,
It is configured to include switch elements SW1 to SW4. One end of the capacitor C1 is grounded, and the other end is connected to a parallel circuit of a series circuit of the switch element SW1 and the diode D1 and a series circuit of the switch element SW2 and the diode D2. The diodes D1 and D2 are connected in opposite directions. This parallel circuit has an inductor L1
Is connected to the inductor L1, a switch element SW3 having one end connected to the power supply Vcc, and a switch element SW4 having one end grounded.

The second sustain pulse generating circuit 2 includes a capacitor C2, diodes D3 and D4, an inductor L2,
It comprises switch elements SW5 to SW8. One end of the capacitor C2 is grounded, and the other end is connected to a parallel circuit of a series circuit of the switch element SW5 and the diode D3 and a series circuit of the switch element SW6 and the diode D4. The diodes D3 and D4 are connected in opposite directions. This parallel circuit has an inductor L2
Is connected to the inductor L2. A switch element SW7 having one end connected to the power supply Vcc and a switch element SW8 having one end grounded are connected to the inductor L2.

In the capacitive load driving circuit thus configured, the first sustain discharge pulse generation circuit 1
The sustain discharge pulse shown in FIG. 11A is generated, and the second sustain discharge pulse generating circuit 2 generates the sustain discharge pulse shown in FIG. How these pulses are generated will be described later in detail. Further, the capacitive load drive circuit shown in FIG. 10 uses the energy lost by charging and discharging the capacitive load Cp as:
It is to be reduced by the inductors L1 and L2 and to be recovered by the capacitors C1 and C2. This circuit configuration is called a so-called power recovery circuit, and its principle is described in various documents (JP-A-6-274125, JP-A-8-137432, etc.).

When the first sustain discharge pulse generation circuit 1 is operating, the second sustain discharge pulse generation circuit 2 is equivalently connected to ground, and the second sustain discharge pulse generation circuit 2
Is operating, the first sustain discharge pulse generation circuit 1
Are equivalently connected to the ground. Therefore, when the first sustain discharge pulse generating circuit 1 is operating, the capacitive load driving circuit shown in FIG. 10 can be represented by an equivalent circuit shown in FIG. When the circuit 2 is operating, the capacitive load driving circuit illustrated in FIG. 10 can be represented by an equivalent circuit illustrated in FIG.

The operation of the capacitive load drive circuit shown in FIG. 10 will be described in detail with reference to FIGS. In FIG. 12, (A) shows the voltage Vcp across the capacitive load Cp,
(B) shows the current IL1 flowing through the inductor L1, (C) shows the voltage VL1 across the inductor L1, and (D) to (G) show the on / off timing of the switch elements SW1 to SW4.

The operation of the first sustain discharge pulse generating circuit 1 will be described with reference to an equivalent circuit shown in FIG. It is assumed that the capacity of the capacitor C1 is much larger (for example, 100 times or more) than the capacity of the capacitive load Cp, and the voltage VC1 is applied to both ends of the capacitor C1. At time t1 in FIG. 12, when the switch element SW1 is turned on, a voltage twice the voltage VC1 across the capacitor C1 is applied to the capacitive load Cp by the resonance circuit of the inductor L1 and the capacitive load Cp.
Is induced. At this time, the switch elements SW2 to SW4
Is off.

When the voltage Vcp across the capacitive load Cp reaches a peak, the switch element SW3 is turned on at time t3. After maintaining this state for a period corresponding to the sustain discharge pulse width, the switch element SW2 is turned on at time t4, and the switch element S
W1 and SW3 are turned off. Then, the charge stored in the capacitive load Cp is stored in the capacitor C1 through the inductor L1. When the voltage Vcp between both ends of the capacitive load Cp becomes 0, the switch element SW4 is turned on at time t6 to keep the voltage Vcp between both ends at 0. Note that the current I flowing through the inductor L1 is
L1 starts rising at time t1, reaches a peak at time t2, and becomes 0 at time t3. Further, it starts to fall at time t4, reaches a peak at time t5, and becomes 0 at time t6. The voltage VL1 between both ends of the inductor L1 is equal to the times t1, t3.
, And gradually decreases at times t4 and t6.

By the above operation, one pulse shown in FIG. 12A is applied to the capacitive load Cp. This pulse corresponds to one of the sustain discharge pulses in FIG. That is, the first sustain discharge pulse generation circuit 1 generates the sustain discharge pulse shown in FIG. The operation of the second sustain discharge pulse generation circuit 2 is exactly the same as the operation of the first sustain discharge pulse generation circuit 1. Switch element SW5, SW6, SW
7 and SW8 operate as switch elements SW2 and SW, respectively.
1, SW3 and SW4. Then, second sustain discharge pulse generating circuit 2 generates a sustain discharge pulse shown in FIG.

The capacitance of the capacitors C1 and C2 is equal to the capacitance load C
When the condition that the capacitance is much larger than the capacitance of p is satisfied and the operation described in FIG. 12 is repeated in the first and second sustain discharge pulse generation circuits 1 and 2, the capacitor C
The voltages VC1 and VC2 across the terminals C1 and C2 are automatically (1/2) V
cc. These series of operations are operations of the resonance circuit, and energy charged in the capacitive load Cp is stored in the capacitor Cp.
1, C2. And the capacity load C
As a result, a sustain discharge pulse shown in FIG. 11C is applied to p.

[0013]

The conventional capacitive load driving circuit shown in FIG. 10 requires two sustain discharge pulse generating circuits, ie, first and second sustain discharge pulse generating circuits 1 and 2, and has a structure. There has been a problem that the complexity and cost have been increased. The present invention has been made in view of such a problem, and has as its object to provide a capacitive load driving circuit having a simple and inexpensive configuration.

[0014]

According to the present invention, in order to solve the above-mentioned problems of the prior art, (1) a capacitive load (Cp)
In the capacitive load drive circuit for charging and discharging the circuit, a series circuit of a first switch element (SW1) and a first diode (D1) and a second switch element (SW2) and a second diode (D2) A parallel circuit in which a series circuit is connected in parallel; a power recovery capacitor (C1) having one end grounded and the other end connected to the parallel circuit; and one end connected to the other end of the capacitive load having one end grounded. And an inductor (L1) having the other end connected to the parallel circuit, a third switch element (SW3) connected to a connection point between the capacitive load and the inductor, and one end grounded. A fourth switch element (SW4) having an end connected to a connection point between the capacitive load and the inductor, and a fifth switch element connected to the third switch element for selectively switching between a positive power supply and a negative power supply.
And a sixth switch element (SW11) connected to the other end of the capacitor and selectively switching between a positive power supply and a negative power supply having a voltage value of の of the positive power supply and the negative power supply. SW12), and (2) a capacitive load (C
In the capacitive load drive circuit for charging and discharging p), a series circuit of a first switch element (SW1) and a first diode (D1), a second switch element (SW2) and a second diode (D2) A power recovery capacitor (C1) having one end grounded and the other end connected to the parallel circuit, and an inductor (one end connected to the parallel circuit). L1), a third switch element (SW3) connected between one end of the capacitive load and a power supply, and a fourth switch element connected at one end to ground and the other end to one end of the capacitive load. (SW4),
A fifth switch element (SW7) connected between the other end of the capacitive load and a power supply, and a sixth switch element (SW7) having one end grounded and the other end connected to the other end of the capacitive load.
8), and a seventh switch element (SW22) connected to the other end of the inductor and selectively connecting the inductor to the one end and the other end of the capacitive load. And provide a capacitive load drive circuit
(3) In a capacitive load driving circuit for charging and discharging a capacitive load (Cp), a series circuit of a first switch element (SW1) and a first diode (D1), and a second switch element (SW2) And a parallel circuit in which a series circuit with a second diode (D2) is connected in parallel, and a power recovery capacitor (C) having one end grounded and the other end connected to the parallel circuit.
1) a first inductor (L1) having one end connected to the parallel circuit and the other end connected to one end of the capacitive load;
A second inductor (L2) having one end connected to the parallel circuit and the other end connected to the other end of the capacitive load, and a third inductor connected between one end of the capacitive load and a power supply. A fourth switch element (SW3) having one end grounded and the other end connected to one end of the capacitive load;
4) a fifth switch element (SW7) connected between the other end of the capacitive load and a power source; and a sixth switch element (SW7) having one end grounded and the other end connected to the other end of the capacitive load. And (4) a capacitive load drive circuit for charging and discharging a capacitive load (Cp), wherein the first switch element (SW1) is provided. A first parallel circuit in which a series circuit of a second switch element (SW2) and a second diode (D2) is connected in parallel; A series circuit of a switch element (SW5) and a third diode (D3); and a fourth switch element (SW5).
6) and a second parallel circuit in which a series circuit of a fourth diode (D4) is connected in parallel, and power recovery in which one end is grounded and the other end is connected to the first and second parallel circuits. And a first inductor (L1) having one end connected to the first parallel circuit and the other end connected to one end of the capacitive load, and one end connected to the second parallel circuit. A second inductor (L2) connected to the other end of the capacitive load and a fifth switch element (SW3) connected between one end of the capacitive load and a power supply; Are grounded and the other end is connected to one end of the capacitive load, and the seventh switch element (SW7) is connected between the other end of the capacitive load and a power supply.
And an eighth switch element (SW8) having one end grounded and the other end connected to the other end of the capacitive load.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a capacitive load driving circuit according to the present invention will be described with reference to the accompanying drawings. FIG. 1 is a circuit diagram showing a first embodiment of the capacitive load drive circuit of the present invention, FIG. 2 is a circuit diagram for explaining the operation of the first embodiment shown in FIG.
FIG. 3 is a waveform diagram for explaining the operation of the first embodiment shown in FIG. 1, FIG. 4 is a circuit diagram for explaining the operation of the first embodiment shown in FIG. 1, and FIGS. 7 is a waveform diagram for explaining the operation of the first embodiment shown in FIG. 7, FIG. 7 is a circuit diagram showing a second embodiment of the capacitive load drive circuit of the present invention, and FIG. 8 is a third embodiment of the capacitive load drive circuit of the present invention. FIG. 9 is a circuit diagram showing an example of a capacitive load drive circuit according to a fourth embodiment of the present invention.
In FIGS. 1, 2, 4, 7 to 9, FIG.
The same parts as those described above are denoted by the same reference numerals, and description of overlapping parts may be omitted as appropriate.

<First Embodiment> In FIG. 1, a capacitive load driving circuit according to a first embodiment includes a capacitor C1 and a diode D.
1, D2, inductor L1, switch elements SW1 to SW
4, SW11 and SW12. One end of the capacitive load Cp is grounded, and the other end is connected to the inductor L1 of the capacitive load drive circuit. One end of the capacitor C1 is grounded, and the other end is connected to a parallel circuit of a series circuit of the switch element SW1 and the diode D1 and a series circuit of the switch element SW2 and the diode D2. The diodes D1 and D2 are connected in opposite directions. The other end of the capacitor C1 is connected to the terminal c of the switch element SW12. The power supply (1/2) Vcc is connected to the terminal a of the switch element SW12, and the power supply-(1/2) Vcc is connected to the terminal b. The capacity of the capacitor C1 is much larger than the capacity of the capacitive load Cp (for example, 100 times or more).

An inductor L1 is connected to the above parallel circuit, and one end of the inductor L1 is connected to the switch element SW1.
1 and a switch element SW4, one end of which is grounded. The power supply Vcc is connected to the terminal a of the switch element SW11, and the power supply -Vcc is connected to the terminal b.

As can be seen from a comparison between the configuration shown in FIG. 1 and the configuration shown in FIG. 10, the capacitive load drive circuit of the first embodiment omits the second sustain discharge pulse generation circuit 2 in FIG. , Switch element SW11 for selectively supplying power supply Vcc and -Vcc, and power supply (1/2) Vcc and-(1/2).
The configuration is such that a switch element SW12 for selectively supplying Vcc is added.

First, the circuit shown in FIG. 1 is equivalently shown in FIG. 2 when the switch elements SW11 and SW12 are respectively connected to the terminal a in order to select the positive power supply Vcc and (1/2) Vcc. It becomes a circuit configuration. FIG. 2 (A)
Works exactly the same as FIG. 2 shows time t1 shown in FIG.
The current flow from to t6 is indicated by a solid line or a broken line. FIG. 3 shows the operation at this time. 3A shows the voltage Vcp across the capacitive load Cp, FIG. 3B shows the current IL1 flowing through the inductor L1, and FIGS. 3C to 3F show the on / off timing of the switch elements SW1 to SW4.

At time t1 in FIG. 3, the switching element S
When W1 is turned on, a voltage twice as large as the voltage VC1 across the capacitor C1 is induced in the capacitive load Cp by the resonance circuit of the inductor L1 and the capacitive load Cp. At this time, the switch elements SW2 to SW4 are off. When the voltage Vcp across the capacitive load Cp reaches a peak, the switch element SW3 is turned on at time t3. After maintaining this state for a period corresponding to the sustain discharge pulse width, at time t4, the switching element SW2 is turned on, and the switching elements SW1 and SW3 are turned off. Then, the charge stored in the capacitive load Cp is stored in the capacitor C1 through the inductor L1. When the voltage Vcp between both ends of the capacitive load Cp becomes 0, the switch element SW is switched at time t6.
4 and keep the voltage Vcp at zero. The current IL1 flowing through the inductor L1 starts increasing at time t1, reaches a peak at time t2, and becomes 0 at time t3. Further, it begins to fall at time t4, reaches a peak at time t5, and reaches time t.
6 is 0.

By the above operation, one pulse shown in FIG. 3A is applied to the capacitive load Cp.
This pulse corresponds to one of the sustain discharge pulses in FIG. In this way,
The capacitive load driving circuit according to the first embodiment includes a switch element SW1
When SW1 and SW12 are connected to the terminal a, the sustain discharge pulse shown in FIG.

Next, when the switch elements SW11 and SW12 are connected to the terminal b to select the negative power supply -Vcc and-(1/2) Vcc, the circuit shown in FIG. 4 is obtained. FIG. 4 shows the current flow at the time points t1 to t6 shown in FIG. 5 by a solid line or a broken line. FIG. 5 shows the operation at this time. In FIG. 5, (A) shows the voltage Vcp across the capacitive load Cp,
(B) is the current IL1 flowing through the inductor L1, (C)-
(F) shows the ON / OFF timing of the switch elements SW1 to SW4.

At time t1 in FIG. 5, the switching element S
When W2 is turned on, a voltage twice as large as the voltage VC1 across the capacitor C1 is induced in the capacitive load Cp by the resonance circuit of the inductor L1 and the capacitive load Cp. At this time, the switch elements SW1, SW3, and SW4 are off. When the voltage Vcp across the capacitive load Cp reaches a peak (negative peak), the switch element SW3 is turned on at time t3. After maintaining this state for a period corresponding to the sustain discharge pulse width, at time t
4 to turn on the switch element SW1 and switch element SW1
2. Turn off SW3. Then, the charge stored in the capacitive load Cp is stored in the capacitor C1 through the inductor L1. When the voltage Vcp across the capacitive load Cp becomes 0,
At time t6, the switching element SW4 is turned on, and the voltage Vcp
Is kept at 0. The current IL1 flowing through the inductor L1
Starts falling at time t1, reaches a peak at time t2,
It becomes 0 at time t3. Further, it starts rising at time t4, reaches a peak at time t5, and becomes 0 at time t6.

By the above operation, one pulse shown in FIG. 5A is applied to the capacitive load Cp.
This pulse corresponds to one of the sustain discharge pulses in FIG. In this way,
The capacitive load driving circuit according to the first embodiment includes a switch element SW1
When SW1 and SW12 are connected to the terminal b, a sustain discharge pulse shown in FIG.

FIG. 6 shows the operation when the above-described FIGS. 2 and 4 are operated continuously. In FIG. 6, (A)
Is the voltage Vcp across the capacitive load Cp, and (B) is the inductor L
The current IL1 flowing through the switch element 1 (C)-(F) is the switching element S
On / off timing of W1 to SW4, (G), (H)
Indicates the timing of selection of the switch elements SW11 and SW12 (that is, the voltage value of the terminal c). FIG. 6 (G),
As shown in (H), switch elements SW11, SW12
Switches terminals a and b at times tp and tq. Time point tp
, The terminal a is switched to the terminal b, and at the time tq, the terminal is switched from the terminal b to the terminal a. Accordingly, the voltage of the terminal c in the switch element SW11 becomes Vcc.
And -Vcc, and the switching element SW12
The voltage at the terminal c is (1/2) Vcc and-(1/2)
Vcc. Note that the switch element SW
11 and SW12 are switched at time points tp and tq, and at the same time, the on / off timing of the switch elements SW1 and SW2 is also switched.

The time points tp and tq may be between time points t6 and t1. That is, the switch elements SW11, SW12
1 is to be applied to one electrode.
This is set between the falling edge of the pulse shown in FIG. 1A and the rising edge of the pulse shown in FIG. 11B to be applied to the other electrode. As a result of the above operation, as a result, the voltage between both ends shown in FIG.
Are applied. This figure 6
The pulse shown in (A) has the same waveform as the pulse shown in FIG. 11 (C), and the capacitive load drive circuit of the first embodiment operates substantially the same as the conventional capacitive load drive circuit. I understand. As described above, according to the first embodiment, all of the second sustain discharge pulse generation circuit 2 in FIG. 10 can be eliminated.

<Second Embodiment> In FIG. 7, a capacitive load driving circuit according to a second embodiment includes a capacitor C1 and a diode D
1, D2, inductor L1, switch elements SW1 to SW
4, SW7, SW8, and SW22. One end of the capacitor C1 is grounded, and the other end is connected to a parallel circuit of a series circuit of the switch element SW1 and the diode D1 and a series circuit of the switch element SW2 and the diode D2. The diodes D1 and D2 are connected in opposite directions. This parallel circuit has an inductor L1
Is connected, and the inductor L1 is connected to the switch element SW22.
Is connected to the terminal c. One end of the capacitive load Cp is connected to the switch element SW via a connection point between the switches SW3 and SW4.
22 and the other end is connected to a switch element SW7,
The terminal b of the switch element SW22 via the connection point of SW8
It is connected to the. A power supply Vcc is connected to the switch elements SW3 and SW7.

As can be seen from a comparison between the configuration shown in FIG. 7 and the configuration shown in FIG. 10, the capacitive load drive circuit of the second embodiment is different from the switch element in the second sustain discharge pulse generation circuit 2 in FIG. Components other than SW7 and SW8 are omitted, and a switch element SW22 is added.

Switch elements SW1 to SW4, SW7, S
The on / off operation of W8 is the same as in FIG. Switching of the switch element SW22 is performed in the same manner as the switch elements SW11 and SW12 of the first embodiment, in which the pulse shown in FIG. 11A to be applied to one electrode and the pulse shown in FIG. It is set between the rising of the pulse shown in FIG. As described above, according to the second embodiment, most of the second sustain pulse generating circuit 2 in FIG. 10 can be reduced.

<Third Embodiment> In FIG. 8, a capacitive load driving circuit according to a third embodiment includes a capacitor C1 and a diode D.
1, D2, inductors L1, L2, switch element SW1
To SW4, SW7, and SW8. One end of the capacitor C1 is grounded, and the other end is connected to a series circuit of the switch element SW1 and the diode D1 and the switch element S1.
It is connected to a parallel circuit of a series circuit of W2 and diode D2. The diodes D1 and D2 are connected in opposite directions. This parallel circuit includes inductors L1 and L2
Is connected. The inductor L1 is connected to the switch SW
3 and SW4 are connected to one end of the capacitive load Cp, and the inductor L2 is connected to the switch elements SW7 and SW8.
Is connected to the other end of the capacitive load Cp. A power supply Vcc is connected to the switch elements SW3 and SW7.

As can be seen from a comparison between the configuration shown in FIG. 8 and the configuration shown in FIG. 10, the capacitive load drive circuit of the third embodiment is different from the switch element in the second sustain discharge pulse generation circuit 2 in FIG. SW7, SW8 and inductor L2
The configuration is omitted except for the above. Switch element SW1
The operation of turning on / off SW4, SW7 and SW8 is shown in FIG.
Is the same as Thus, according to the third embodiment, FIG.
A considerable portion of the second sustain pulse generating circuit 2 at 0 can be reduced.

<Fourth Embodiment> In FIG. 9, a capacitive load driving circuit according to a fourth embodiment includes a capacitor C1 and a diode D.
1, D2, D3, and D4, inductors L1 and L2, and switch elements SW1 to SW8. One end of the capacitor C1 is grounded, and the other end is connected to the switch element SW.
1 and a diode D1 and a switching element SW2
And a series circuit of a switching element SW5 and a diode D3, and a parallel circuit of a series circuit of a switching element SW5 and a diode D3 and a series circuit of a switching element SW6 and a diode D4. Diode D1, D2 or D
3 and D4 are connected in opposite directions. The inductors L1 and L2 are connected to these parallel circuits.

The inductor L1 is connected to switches SW3 and SW
4 is connected to one end of the capacitive load Cp via a connection point, and the inductor L2 is connected to the other end of the capacitive load Cp via a connection point between the switch elements SW7 and SW8. A power supply Vcc is connected to the switch elements SW3 and SW7.

As can be seen from a comparison between the configuration shown in FIG. 9 and the configuration shown in FIG. 10, the capacitive load drive circuit of the fourth embodiment is different from the capacitor C2 in the second sustain discharge pulse generation circuit 2 in FIG. Is omitted. The on / off operation of the switch elements SW1 to SW8 is shown in FIG.
Is the same as Thus, according to the fourth embodiment, FIG.
It is possible to reduce a part of the second sustain discharge pulse generation circuit 2 (capacitor C2) at 0.

[0035]

As described in detail above, the capacitive load drive circuit of the present invention can reduce all or a part of one of the two sustain discharge pulse generation circuits by the above-described configuration. A simple and inexpensive configuration can be achieved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram for explaining the operation of the first embodiment shown in FIG.

FIG. 3 is a waveform chart for explaining the operation of the first embodiment shown in FIG. 1;

FIG. 4 is a circuit diagram for explaining the operation of the first embodiment shown in FIG. 1;

FIG. 5 is a waveform chart for explaining the operation of the first embodiment shown in FIG. 1;

FIG. 6 is a waveform chart for explaining the operation of the first embodiment shown in FIG. 1;

FIG. 7 is a circuit diagram showing a second embodiment of the present invention.

FIG. 8 is a circuit diagram showing a third embodiment of the present invention.

FIG. 9 is a circuit diagram showing a fourth embodiment of the present invention.

FIG. 10 is a circuit diagram showing a conventional example.

FIG. 11 is a waveform chart for explaining the operation of the conventional example.

FIG. 12 is a waveform chart for explaining the operation of the conventional example.

FIG. 13 is an equivalent circuit diagram of a conventional example.

[Explanation of symbols]

C1 Capacitor Cp Capacitive load D1 to D4 Diode L1, L2 Inductor SW1 to SW8, SW11, SW12, SW22 Switch element Vcc, (1/2) Vcc Positive power supply -Vcc,-(1/2) Vcc Negative power supply

Claims (4)

[Claims] In a capacitive load driving circuit for charging and discharging a capacitive load, a series circuit of a first switch element and a first diode and a series circuit of a second switch element and a second diode are connected in parallel. A connected parallel circuit; one end is grounded; the other end is a power recovery capacitor connected to the parallel circuit; and one end is connected to the other end of the grounded capacitive load, and the other end is An inductor connected to a parallel circuit, a third switch element connected to a connection point between the capacitive load and the inductor, one end grounded, and another end connected to a connection point between the capacitive load and the inductor A fourth switch element connected to the third switch element, a fifth switch element selectively switching between a positive power supply and a negative power supply, and a positive power supply connected to the other end of the capacitor. And a sixth switch element for selectively switching between a positive power supply and a negative power supply having a voltage value that is 1/2 of the negative power supply. 2. A capacitive load driving circuit for charging and discharging a capacitive load, wherein a series circuit of a first switch element and a first diode and a series circuit of a second switch element and a second diode are connected in parallel. A connected parallel circuit, one end is grounded, the other end is a power recovery capacitor connected to the parallel circuit, one end is an inductor connected to the parallel circuit, and one end of the capacitive load is connected to a power supply. A third switch element connected therebetween, a fourth switch element having one end grounded and the other end connected to one end of the capacitive load, and a fourth switch element connected between the other end of the capacitive load and a power supply A fifth switch element, one end of which is grounded and the other end of which is connected to the other end of the capacitive load; and a sixth switch element which is connected to the other end of the inductor. One end and the other end And a seventh switch element selectively connected to the circuit. 3. A capacitive load driving circuit for charging and discharging a capacitive load, wherein a series circuit of a first switch element and a first diode and a series circuit of a second switch element and a second diode are connected in parallel. A connected parallel circuit, one end is grounded, the other end is a power recovery capacitor connected to the parallel circuit, and one end is connected to the parallel circuit, and the other end is connected to one end of the capacitive load. A first inductor, one end connected to the parallel circuit, the other end connected to the other end of the capacitive load, and a third inductor connected between one end of the capacitive load and a power supply A fourth switch element having one end grounded and the other end connected to one end of the capacitive load; and a fifth switch element connected between the other end of the capacitive load and a power supply. , One end is grounded and the other is front Capacitive load drive circuit, characterized in that constructed and a sixth switch element connected to the other end of the capacitive load. 4. A capacitive load driving circuit for charging and discharging a capacitive load, wherein a series circuit of a first switch element and a first diode and a series circuit of a second switch element and a second diode are connected in parallel. A second parallel connection in which a connected first parallel circuit, a series circuit of a third switch element and a third diode, and a series circuit of a fourth switch element and a fourth diode are connected in parallel; A power recovery capacitor having one end grounded and the other end connected to the first and second parallel circuits; and one end connected to the first parallel circuit, and the other end connected to the capacitive load. A first inductor connected to one end, a second inductor connected to the second parallel circuit at one end, and a second inductor connected at the other end to the other end of the capacitive load; Fifth switch element connected between A sixth switch element having one end grounded and the other end connected to one end of the capacitive load; a seventh switch element connected between the other end of the capacitive load and a power supply; And an eighth switch element having the other end connected to the other end of the capacitive load.