JPH1115407A - Wiring board and plasma display panel driving device using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To successively scan horizontal pixel lines in upper/lower areas of a PDP with shift outputs different in direction by wiring an output terminal on a wiring layer of a wiring board with a first wiring pattern, wiring another output terminal on another wiring layer through a through hole with a second wiring pattern and intersecting the first, second wiring patterns to a laminated direction. SOLUTION: This driving device 12 performs the operation successively shifting the horizontal pixel line of the upper half of the PDP 11 electrically connected to the wiring board 1 from a row electrode pair answering to the upper end position of the screen of the PDP 11 toward the row electrode pair corresponding to the central position and scanning by controlling two IC chips 101 loaded on the wiring board 1 so as to shift operate alternately. Further, the driving device 12 performs the operation successively shifting the horizontal pixel line of the lower half of the PDP 11 from the row electrode pair corresponding to the lower end position of the screen of the PDP 11 toward the two electrode pair corresponding to the central position, and these two operation are performed simultaneously.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a wiring board for mounting an IC chip having a shift register function, and
The present invention relates to a driving device for a plasma display panel using the wiring substrate.

[0002]

2. Description of the Related Art Plasma display panels (hereinafter referred to as PDs)
As is well known, various studies have recently been made as one of thin two-dimensional screen displays, and one of them is an AC discharge matrix type plasma display panel having a memory function. ing. FIG. 5 is a diagram showing a schematic configuration of a driving device of a plasma display panel including such a PDP.

In FIG. 5, a driving device 100 includes:
The input video signal is converted into digital pixel data corresponding to each pixel, and pixel data pulses corresponding to the pixel data are applied to the column electrodes D1 to Dm of the PDP 11. The PDP 11 includes the column electrodes D1 to Dm, and row electrodes x1 to xn and y1 to yn which are orthogonal to the column electrodes and constitute one row by a pair of X and Y.

Each of these column electrode and row electrode pairs is formed with a dielectric (not shown) interposed therebetween. One pixel cell is formed at the intersection of one column electrode and row electrode, and each pixel electrode is formed on each row electrode pair. The plurality of pixels thus formed constitute each horizontal pixel line of the PDP 11.

The drive unit 100 includes reset pulses RPx and RPy for forcibly exciting the discharge between all the row electrode pairs of the PDP 11 to form wall charges, a scan pulse SP for writing pixel data, Each drive pulse such as sustain pulses IPx and IPy for maintaining the discharge light emission is generated and applied to the row electrodes x1 to xn and y1 to yn of the PDP 11.

The driving device 100 simultaneously applies each pixel data pulse corresponding to each pixel of one horizontal pixel line to each of the column electrodes D1 to Dm at a predetermined timing with respect to each driving pulse. As a result, the PDP 11 writes the pixel data for each row, and the scan pulse S
The pixel data is written for each row scanned and driven by P, and light emission display of pixels is performed for each horizontal pixel line corresponding to each row electrode pair.

FIG. 6 is a diagram showing a scan pulse drive circuit included in the drive device 100. In FIG. 1, a scanning pulse driving circuit is composed of an integrated circuit (IC chip) 101, a shift register 102, a latch circuit 1
03 and a switching circuit 105. The scanning pulse driving circuit performs a switching control operation in accordance with various control signals to generate a scanning pulse SP, and outputs the shift register 102, the latch circuit 103, and the switching circuit 10
5 is operated appropriately, the scanning pulse S is output from the output terminal (OUT1 to OUTm) corresponding to each row electrode pair of the PDP 11.
P is sequentially shifted and output.

Further, by performing a switching control operation by a control signal supplied from the switching control signal output circuit 104 of the sustain pulse, the scan pulse SP
The two pulses are mixed in such a manner that the waveforms of the sustain pulses IPx and IPy are superimposed on the waveform of the pulse.

As described above, the driving device 100 includes an integrated circuit (IC chip) 10 having a shift register function using the shift register 102 and the latch circuit 103 described above.
1 generates a scan pulse SP on which the waveforms of the sustain pulses IPx and IPy are superimposed, and generates an integrated circuit (IC chip).
Shift output from the output terminals (OUT1 to OUTm).

[0010] This IC chip 101
Each output terminal (OUT1 to OUTm) is connected to each row electrode pair of the PDP 11. In this case, each output terminal (OUT1 to OUT
m) is wired, for example, to each connection terminal of a connector provided on a wiring board, and the connectors are connected collectively by fitting them into other connectors to which each row electrode pair of the PDP 11 is connected.

FIG. 7 is a layout diagram of each output terminal (OUT1 to OUTm) of the IC chip 101. IC chip is 101,
In general, the output terminals (OUT1 to OUT1 to OUT4) which are formed by a flat package having a planar quadrangular shape and correspond to the number (here, m) of row electrode pairs of the PDP 11 as shown in FIG.
m) are derived by approximately half (OUT1 to OUTn and OUTn + 1 to OUTm) on opposite sides of the IC chip 101, and the scanning pulse SP is shifted by one shift operation of the IC chip 101 in FIG. Are provided so as to be sequentially shifted and output from OUT1 to OUTm along the direction indicated by the arrow.

In FIG. 7, only one output terminal of each row electrode pair is shown, and the other output terminal side common to each row electrode pair is not shown.
The chip 101 also has an output terminal corresponding to the data electrode and an input terminal from a driving device and the like, but these terminals are not shown here.

Conventionally, when the PDP 11 is formed on a large screen, many row electrode pairs are required. Therefore, the PDP 11 is scanned by using the above-described IC chip 101 to scan the PDPs.
When each of the 11 horizontal pixel lines is sequentially scanned in one direction, the driving time of the scanning pulse SP corresponding to one screen is long, and each pixel has uniform luminance from the start to the end of scanning of the screen. It is difficult to display.

Therefore, in such a case, the PDP
Among the horizontal pixel lines of the PDP 11, each row electrode pair corresponding to the upper half horizontal pixel line is sequentially scanned from the row electrode pair corresponding to the upper end position of the screen of the PDP 11 to the row electrode pair corresponding to the center position. By simultaneously scanning each row electrode pair corresponding to the remaining lower half horizontal pixel lines from the row electrode pair corresponding to the lower end position of the screen of the PDP 11 toward the row electrode pair corresponding to the center position, While shortening the scanning time for one field,
The occurrence of uneven brightness is prevented. That is, in one screen, sequential scanning from the upper end of the upper half to the center and sequential scanning from the lower end of the lower half to the center are performed simultaneously.

[0015]

However, in order to use the above-described scanning method, an IC chip 101 is attached to a single-layer wiring board 102 provided in a driving device 100, and as shown in FIG. A plurality of wiring patterns corresponding to the respective output terminals (OUT1 to OUTm) led out on both opposite sides of the IC chip 101 are formed on the wiring board 102, and one side of each wiring pattern is connected to each of the output terminals (OUT1 to OUTm). OUTm), the other side of each wiring pattern is connected to connection terminals (T1 to Tm) arranged in a connector or the like, and each connection terminal (T1 to Tm) is arranged in the order of arrangement of the row electrode pairs of the PDP 11. If an attempt is made to connect them to other connected connectors collectively, there will be places where the respective wiring patterns are short-circuited. Therefore, each output terminal (OUT1 to OUTm) and each row electrode pair cannot be individually connected.

Each of the output terminals (OUT1 to OUTm) led out to the opposite side surfaces of the IC chip 101 is connected to the wiring board 10.
In the case where a wiring pattern that leads to each row electrode pair of the PDP 11 without short-circuiting on the
The scanning output direction of each output terminal of either the upper half horizontal pixel line or the lower half horizontal pixel line of the DP 11 is opposite to the direction in the above-described method.

FIG. 8B shows a wiring pattern in this case. Here, the horizontal pixel line in the lower half of the PDP 11 is scanned in the reverse direction.

Also, in the case where two such IC chips 101 are prepared and the output terminals led out on one side of each integrated circuit are used, as shown in FIG.
To prevent each wiring pattern from short-circuiting, one IC chip 101 is turned upside down and the wiring board 102
Must be mounted on top. In FIG. 9, the IC chip 101 which is mounted on the wiring board 102 by turning over the IC chip 101
Are shown with diagonal lines.

For this reason, conventionally, as shown in FIG.
Two types of ICs whose shift output directions are set opposite to each other
The chips 101 and 103 are mounted on the wiring board 102, and the output terminal led out on one side surface of each IC chip is connected to each row electrode pair.
It was supplied to each horizontal pixel line of DP11.

As a result, if two expensive integrated circuits (IC chips) having the same type of shift register function are used when the drive circuit of the PDP 11 is formed,
Since the C chip is mounted upside down, the wiring work of the wiring board of the drive circuit is complicated and the number of steps is increased, so that the manufacturing cost is increased. When two expensive integrated circuits (IC chips) having different types of shift register functions are used,
As compared with the case where two IC chips of the same type are used, the types of assembled parts are increased, and at the time of assembling, it is necessary to select or confirm the IC chips, thereby increasing the cost.

The present invention has been made in view of the above-described problems, and has a structure in which one integrated circuit (IC chip) having a shift register function is mounted and horizontal pixel lines in upper and lower regions of a PDP are moved in different directions from each other. It is an object of the present invention to provide a wiring board capable of sequentially scanning with the shift output of the above, and a driving device for a plasma display panel using the wiring board.

[0022]

According to the first aspect of the present invention,
In a wiring board on which an IC chip having a shift register function is mounted, the wiring board is a multi-layered wiring board having through holes, and a predetermined output terminal among the output terminals of the shift register of the IC chip is one of the wiring boards. The wiring layer is wired in a first wiring pattern, another predetermined output terminal is wired in another wiring layer of the wiring board through a through hole in a second wiring pattern, and the first and second wiring patterns are formed on the wiring board. Intersect with the stacking direction of

According to a second aspect of the present invention, a plurality of electrodes of a plasma display panel including a shift register, wherein a plurality of electrodes are arranged by shift output from the shift register, are connected to an upper end of the plasma display panel. After scanning along the first scanning direction from the electrode corresponding to the lower (or lower) position to the lower (or upper) direction, from the electrode corresponding to the lower (or upper) position of the plasma display panel upward (or downward). A driving apparatus for a plasma display panel configured to sequentially supply a scanning pulse to a plurality of electrodes by scanning along a second scanning direction, wherein the shift register is mounted on a multilayer wiring board having through holes. The shift register is configured by an IC chip, which is connected to the output terminal of the shift register in the first scanning direction. A predetermined output terminal is wired to one wiring layer of the wiring board in a first wiring pattern, and another predetermined output terminal corresponding to the second scanning direction is connected to another wiring layer of the wiring board via a through hole. A driving device for a plasma display panel, wherein two driving patterns are arranged, and the first and second wiring patterns intersect with a laminating direction of a wiring substrate.

According to a third aspect of the present invention, in the wiring board according to the first aspect, the IC chip is formed in a plane quadrangular shape, and a predetermined output terminal and another predetermined output terminal are provided on opposite side surfaces thereof. After the terminals are respectively derived and sequentially shifted from the output terminal corresponding to the upper end (or lower end) position of one of the side surfaces toward the output terminal corresponding to the lower end (or upper end) position, the lower end ( Or a shift register function of sequentially shifting from an output terminal corresponding to the upper (or upper) position to an output terminal corresponding to the upper (or lower) position.

According to a fourth aspect of the present invention, there is provided a driving apparatus for a plasma display panel according to the second aspect, wherein
The IC chip is formed in a plane quadrangular shape, and an output terminal corresponding to the first scanning direction and an output terminal corresponding to the second scanning direction are respectively derived on opposite side surfaces thereof, and upper ends of one side surface of both side surfaces are provided. After sequentially shifting from the output terminal corresponding to the (or lower end) position to the output terminal corresponding to the lower end (or upper end) position, the output terminal corresponding to the lower end (or upper end) position of the other side surface is shifted to the upper end (or lower end). A) a shift register function of sequentially shifting toward an output terminal corresponding to a position.

[0026]

Since the present invention is constructed as described above, each output terminal of the shift register of the IC chip mounted on the wiring board is connected to each row electrode pair of the corresponding PDP without short-circuiting each other. In addition, the same type of IC chip having a shift register function is mounted on a wiring board, and the mounted IC is mounted.
By performing the shift operation of the chip, the upper half and lower half horizontal pixel lines of the PDP electrically connected to the wiring board can be sequentially shifted in the opposite directions to each other. Therefore, the types of components used for the wiring board can be reduced, and the number of steps for attaching the IC chip to the wiring board can be reduced.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a preferred embodiment of the present invention will be described with reference to FIGS. 1 and 2
FIG. 1 is an example of a structural view of a wiring board according to an embodiment of the present invention. FIG. 1 is a cross-sectional view showing a schematic structure of a main part of a wiring board on which two IC chips 101 are mounted, and FIG. 1 shows an example of a wiring pattern arrangement when a wiring board on which two IC chips 101 are mounted is viewed from above.

The wiring board 1 has a multilayer structure formed by two or more wiring layers. Here, the wiring substrate 1 is described as a multilayer structure having four wiring layers (first to fourth wiring layers).

As shown in FIG. 1, a wiring board 1 includes a first wiring layer 2, an insulating layer 3, a second wiring layer 4, a flat base material 5 having an insulating property, a third wiring layer 6, and an insulating layer. 7, the fourth wiring layer 8 has a multilayer structure in which the first wiring layer 8 is sequentially stacked,
A resist layer 9 and a resist layer 10 are provided on the fourth wiring layer 8, respectively.

Further, two IC chips 101 are mounted on the upper surface of the wiring board 1, and the output terminals (OUT1 to OUTm) of each IC chip 101 are connected to each other by a conductive adhesive member 13 such as solder or conductive paste. It is formed so as to be wired to a wiring pattern provided on one wiring layer 2.

The wiring pattern provided on the first wiring layer 2 includes a first wiring pattern 1a individually connected to output terminals (OUT1 to OUTm) led out on both side surfaces of one IC chip 101, and a second wiring pattern 1a. Of the output terminals (OUT1 to OUTm) led out on both sides of the IC chip 101, the connection patterns 1b individually connected to the output terminals (OUT1 to OUTn) led out on one side and the other one side. Derived output terminal (OU
Tn + 1 to OUTm).

The connection pattern 1b has output terminals (OUT1 to OU).
Tn) is electrically connected to a second wiring pattern 1d formed in the second wiring layer 4 through a through hole 1e provided in the wiring board 1 corresponding to each of the wiring patterns Tn). The connection pattern 1c is connected to the third wiring pattern 1g formed in the third wiring layer 6 through the through hole 1f provided in the wiring board 1 corresponding to each of the output terminals (OUTn + 1 to OUTm). Connect conductively.

FIG. 2 is a view showing the arrangement of the wiring patterns of the respective wiring layers at the same time from the upper surface of the wiring board 1. In FIG. 2, the wiring patterns provided on the first wiring layer 2, namely, The first wiring pattern 1a and the connection pattern 1b are shown by solid lines, the second wiring pattern 1d formed on the second wiring layer 4 is shown by a two-dot chain line, and the third wiring pattern formed on the third wiring layer 6 is shown. 1 g is indicated by a dashed line.

As shown in FIG. 2, these wiring patterns correspond to the output terminals (OUT1 to OU) of the two IC chips 101, respectively.
Tm) are conductively connected to connection terminals (T1 to T2m) arranged in a connector or the like provided on the wiring board 1, respectively.

As can be seen from FIG. 2, each output terminal (OUT1 to OUT1) led out to one side of one side of the upper IC chip 101.
OUTn) are wired to the connection terminals (T1 to Tn) in the order of arrangement.

The output terminals (OUTn + 1 to OUTm) led out to the other side of the upper IC chip 101 are wired to the connection terminals (Tn + 1 to Tm) in the order of alignment.

As shown in FIG. 2, the first wiring patterns 1a wired in the first wiring layer 2 do not intersect with each other and, as shown in FIG.
1 are sequentially connected to the connection terminals T1 to Tm along the shift output direction of the scan pulse SP output from the upper IC.
When the chip 101 performs one shift operation, the scan pulse SP is sequentially output from T1 to Tm.

On the other hand, each output terminal (OUT1 to OUTn) led out to one side of the lower IC chip 101 is connected to a corresponding connection pattern 1b as shown in FIG. These connection patterns 1b are conductively connected to the second wiring patterns 1d formed in the second wiring layer 4 via the corresponding through holes 1e, and each connection terminal (Tm + 1 to Tm + n) Are arranged in the order of arrangement.

The through hole 1e is formed so as to electrically connect only the second wiring pattern 1d corresponding to the connection pattern 1b.

The output terminals (OUTn + 1 to OUTm) led out to the other side of the lower IC chip 101 are shown in FIG.
Are connected to the corresponding connection patterns 1c. These connection patterns 1c are conductively connected to the third wiring patterns 1g formed in the third wiring layer 6 through the corresponding through holes 1f, and each connection terminal (Tm + n + 1 to T2m) Are arranged in the order of arrangement.

The through hole 1f is formed so as to electrically connect only the third wiring pattern 1g corresponding to the connection pattern 1c.

In this case, the second wiring pattern 1d and the third wiring pattern 1g have portions that cross each other in the middle of the respective wiring patterns. The third wiring layer 6 on which the third wiring pattern 1g is formed is electrically isolated by the insulating base material 5 and therefore does not short-circuit with each other.

The second wiring layer 4 on which the second wiring pattern 1d is formed and the first wiring layer 2 on which the first wiring pattern 1a is formed are insulated except for the portion where the through hole 1e is formed. Since they are electrically isolated by the insulating layer 3 having a property, they are not short-circuited to each other.

The third wiring layer 6 on which the third wiring pattern 1g is formed and the first wiring layer 2 on which the first wiring pattern 1a is formed are insulated except for the portion where the through hole 1e is formed. Since they are electrically isolated by the insulating layer 3 having a property, they are not short-circuited to each other.

The second wiring pattern 1d wired in the second wiring layer 4 and the third wiring pattern 1g wired in the third wiring layer 6 cross each other but are electrically isolated. Then, along the shift output direction of the scan pulse SP output from the lower IC chip 101,
Since it is connected to each connection terminal of Tm + 1 ~ T2m, the lower IC
When the chip 101 performs one shift operation, the scan pulse SP is sequentially output from Tm + 1 to T2m. This shift operation is performed simultaneously with the shift operation from T1 to Tm by the upper IC chip 101.

The wiring board 1 is, as shown in FIG.
PDP 11 with two IC chips 101 mounted
Of each connection terminal (T1-T2m)
Are sequentially electrically connected to the row electrode pairs corresponding to the horizontal pixel lines arranged in the PDP 11.

The driving device 12 controls the driving of each of the IC chips 101 at the same time, and causes both IC chips to perform the shift operation at the same time. Thus, the scanning pulse SP is simultaneously generated from each IC chip 101, and sequentially shifted and output from each output terminal (OUT1 to OUTm).

Thus, the upper IC chip 10 in FIG.
1 performs a shift operation, the row electrode pairs corresponding to the upper half horizontal pixel lines of the PDP 11 connected to the respective connection terminals (T1 to Tm) are sequentially driven.
One upper half horizontal pixel line sequentially scans from the row electrode pair corresponding to the upper end position of the screen of the PDP 11 to the row electrode pair corresponding to the center position.

When the lower IC chip 101 in FIG. 2 performs the shift operation, the row electrode pair corresponding to the lower half horizontal pixel line of the PDP 11 connected to each connection terminal (Tm + 1 to T2m) is connected. Since they are driven sequentially, the PDP 11
The lower half horizontal pixel line sequentially scans from the row electrode pair corresponding to the lower end position of the screen of the PDP 11 to the row electrode pair corresponding to the center position.

As described above, the driving device 12 includes the wiring board 1
By controlling the two IC chips 101 mounted thereon to be shifted alternately, the upper half horizontal pixel line of the PDP 11 electrically connected to the wiring board 1 corresponds to the upper end position of the screen of the PDP 11 Scanning from the row electrode pair to the row electrode pair corresponding to the center position, and shifting the lower half horizontal pixel line of the PDP 11 from the row electrode pair corresponding to the lower end position of the screen of the PDP 11 to the center position. The operation of sequentially shifting and scanning toward the corresponding row electrode pair is simultaneously performed.

In the embodiment described above, two I-types of the same type are mounted on the wiring board 1 attached to the driving device 12.
C chip 101 is connected to each wiring pattern, and PDP 11
In the above description, the horizontal pixel lines corresponding to the upper half and the lower half of the screen are scanned in opposite directions. However, the present invention is not limited to this, and one side of each output terminal formed on both sides of one IC chip is described. Side output terminals are connected to each wiring pattern corresponding to the upper half and the lower half of the screen of the PDP 11,
Horizontal pixel lines corresponding to the upper half and the lower half of the screen of the DP 11 may be respectively scanned in opposite directions.

FIG. 3 shows another embodiment of the present invention, and shows a configuration in which one shift register IC chip 101 performs scanning in the shift direction as described in the above embodiment. In this embodiment, the driving circuit IC chip 111 of the PDP is mounted on the same substrate as the shift register IC chip 101. The output terminals OUT1 to OUTm led to one side surface of the IC chip 101 are terminals T1 to Tm located at the upper half of the connection terminals (T1 to T2m) of the drive circuit IC chip 111.
Are connected by a first wiring pattern 1a. The shift direction of the output terminals OUT1 to OUTm is
Since the direction is Tm, the connection terminals of the drive circuit IC chip 111 are also in the direction from T1 to Tm (direction from the upper side to the center).
Is scanned.

On the other hand, the output terminal OUTm
+1 to OUT2m are connected to the terminals T2m to Tm + 1 located on the lower half of the connection terminals of the drive circuit IC chip 111 by the second wiring pattern 1d. Output terminal OUTm + 1 to OU
Since the shift direction of T2m is from OUTm + 1 to OUT2m, the connection terminal of the drive circuit IC chip 111 is from T2m.
Scanning is performed in the direction of Tm + 1 (direction from the lower side toward the center).

The IC chip 101 is, as shown in FIG.
It is mounted on a double-sided (two-layer) wiring board having wiring patterns formed on the front and back surfaces, respectively, and the first wiring pattern 1a is formed on the front surface. Also, a second wiring pattern 1d is formed on the back surface, and is led out to the front surface via a through hole. Each of the wiring patterns 1a and 1d is formed so as to intersect the lamination direction of the substrate as shown in FIG. With the above configuration, one IC chip 101
Driven by the driving circuit IC chip 111
DP simultaneously scans the horizontal pixel lines corresponding to the upper half and the lower half of the screen in the opposite directions.

In the above-described embodiment, the PD
The horizontal pixel lines in the upper half of the screen of P11 are sequentially shifted from the row electrode pair corresponding to the upper end position of the screen of the PDP 11 toward the row electrode pair corresponding to the central position, and are scanned. Horizontal pixel line to PD
The case where the scanning is performed by sequentially shifting from the row electrode pair corresponding to the lower end position of the screen of P11 to the row electrode pair corresponding to the center position has been described. Are sequentially shifted from the row electrode pair corresponding to the center position of the PDP 11 to the row electrode pair corresponding to the upper end position, and the lower half horizontal pixel line of the PDP 11 is shifted to the row corresponding to the center position of the PDP 11 screen. The scanning may be sequentially shifted from the electrode pair toward the row electrode pair corresponding to the lower end position. Also,
The wiring board according to the present invention is not limited to the driving circuit of the PDP,
If the scanning direction and the shift direction are as shown in the above-described embodiments, the present invention can be applied to those circuit configurations.

[0056]

According to the present invention, the output terminals of the shift register of the IC chip mounted on the wiring board are connected to the corresponding terminals without short-circuiting. The same type of I having a shift register function
The C chip is mounted on the wiring board, and the mounted IC chip is shifted to sequentially shift the upper and lower horizontal pixel lines of the PDP electrically connected to the wiring board in directions opposite to each other. can do. Therefore, the types of components used for the wiring board can be reduced, and the number of steps for attaching the IC chip to the wiring board can be reduced.

[Brief description of the drawings]

FIG. 1 is an example of a structural diagram of a wiring board according to an embodiment of the present invention.

FIG. 2 is an example of a wiring pattern according to an embodiment of the present invention.

FIG. 3 is an example of a wiring pattern according to another embodiment of the present invention.

FIG. 4 is an example of a structural diagram of a wiring board according to another embodiment of the present invention.

FIG. 5 is a diagram showing a schematic configuration of a driving device of a plasma display panel including a PDP.

FIG. 6 is a diagram illustrating a scan pulse driving circuit included in the driving device.

FIG. 7 is a layout diagram of output terminals (OUT1 to OUTm) of the IC chip.

FIG. 8 is formed for mounting an IC chip on a single-layer wiring board.

FIG. 9 is an example of a wiring pattern of a single-layer wiring board when one IC chip is mounted upside down.

FIG. 10 shows a case where the shift output directions are set opposite to each other.
This is an example in which various types of IC chips are mounted on a wiring board.

[Explanation of symbols]

 1 ... wiring board 1a ... first wiring pattern 1b ... connection pattern 1c ... connection pattern 1d ... second wiring pattern 1e ...・ Through hole 1f ・ ・ ・ ・ ・ ・ ・ Through hole 1g ・ ・ ・ ・ ・ ・ ・ Third wiring pattern 2 ・ ・ ・ ・ ・ ・ First wiring layer 3 ・ ・ ・ ・ ・ ・ Insulating layer 4 ・ ・ ・ ・ ・ ・ Second Wiring layer 5 Base 6 Third wiring layer 7 Insulating layer 8 Fourth wiring layer 9 Resist Layer 10 Resist layer 11 PDP 12 Driving device 13 Adhesive member 100 Driving device 101 IC chip 102 · Wiring board 111 ··· IC chip for drive circuit

Claims (4)

[Claims] 1. A wiring board on which an IC chip having a shift register function is mounted, wherein said wiring board is a multi-layered wiring board having through holes, and a predetermined output among output terminals of a shift register of said IC chip. The terminal is firstly connected to one wiring layer of the wiring board.
Another predetermined output terminal is wired to another wiring layer of the wiring board via the through hole in a second wiring pattern, and the first and second wiring patterns are stacked on the wiring board. A wiring board, which intersects the direction. 2. A plasma display panel including a shift register, wherein a plurality of electrodes are arranged by a shift output from the shift register, the plurality of electrodes corresponding to an upper end (or lower end) position of the plasma display panel. After scanning along the first scanning direction going downward (or upward) from the electrode, along the second scanning direction going upward (or downward) from the electrode corresponding to the lower end (or upper end) position of the plasma display panel. What is claimed is: 1. A driving device for a plasma display panel, wherein a scanning pulse is sequentially supplied to said plurality of electrodes by scanning, wherein said shift register comprises an IC chip mounted on a wiring board having a multilayer structure having through holes. The IC chip corresponds to the first scanning direction among the output terminals of the shift register. A predetermined output terminal is wired to one wiring layer of the wiring board in a first wiring pattern, and another predetermined output terminal corresponding to the second scanning direction is connected to another wiring of the wiring board via the through hole. A driving apparatus for a plasma display panel, wherein the first wiring pattern and the second wiring pattern intersect with a stacking direction of a wiring board. 3. The wiring board according to claim 1, wherein the IC chip is formed in a plane quadrangular shape, and the predetermined output terminal and the another predetermined output terminal are respectively led out on opposite side surfaces thereof. After sequentially shifting from the output terminal corresponding to the upper end (or lower end) position of one of the side surfaces to the output terminal corresponding to the lower end (or upper end) position, the lower end (or upper end) position of the other side surface A shift register function of sequentially shifting from an output terminal corresponding to (1) to an output terminal corresponding to an upper end (or lower end) position. 4. The driving device for a plasma display panel according to claim 2, wherein the IC chip is formed in a plane quadrangular shape, and the output terminals corresponding to the first scanning direction and the output terminals on opposite side surfaces thereof. Output terminals corresponding to the two scanning directions are respectively derived, and sequentially shifted from the output terminal corresponding to the upper end (or lower end) position of one of the side surfaces to the output terminal corresponding to the lower end (or upper end) position. And a shift register function of sequentially shifting from an output terminal corresponding to a lower end (or upper end) position of the other side surface to an output terminal corresponding to an upper end (or lower end) position. apparatus.