JPH11149496A - Device and method for supporting gated clock design and computer readable storage medium storing gated clock design supporting program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a gated clock design supporting device with which gated clock design is enabled by using an optimum enable signal with a high power consumption reduction effect. SOLUTION: Non-load conditions are extracted (3) corresponding to a memory cell and based on these conditions, enable signal candidates in gated clock design are generated (4). While analyzing (5) the parameters such as area, delay time and power consumption provided with these enable signal candidates, any enable signal is selected (8) and a gated clock circuit using this selected enable signal is added to a logic circuit to be designed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gated clock design support apparatus for automating a logic circuit design using a computer, particularly for supporting a gated clock design with a high effect of reducing power consumption.
And a gated clock design support method.

[0002]

2. Description of the Related Art In recent years, semiconductor chips such as LSIs tend to be highly integrated and large in size, and their power consumption is also increasing. The gated clock design is developed for the purpose of generating a logic circuit with low power consumption when designing a circuit. In the following description, an operation of changing a logic circuit by a gated clock design is referred to as clock gating.

Here, the above-described gated clock design will be briefly described.

FIG. 15 is a partial circuit diagram showing a part of a synchronous logic circuit to be logically designed, and shows a logic circuit which is not clock-gated.

In FIG. 1, FF0, FF1,... FF3
Reference numeral 1 denotes a D flip-flop, and a 32-bit data register is configured by 32 flip-flops. The clock signal CLK is supplied to the clock input port CK of each flip-flop at the same timing, and the data calculated by the data operation circuit 11 is written to the data input port D at the rising timing of the clock signal CLK.

It is known that such a logic circuit consumes the most power when the flip-flop operates at the rising and falling edges of the clock signal. But,
Since the clock signal is always input to the flip-flop in a fixed time frame regardless of the presence or absence of data, wasteful power is consumed during non-load time when there is no need to load data.

FIG. 16 is a circuit configuration diagram of a clock-gated logic circuit, and shows an example in which an AND gate 12 is inserted as a gating circuit on the clock line in FIG.

An AND logic circuit (not shown) for controlling the clock output is connected to the AND gate 12, and an enable signal E of "1" or "0" is applied to the enable logic in accordance with the timing of the clock signal CLK. It is provided from a circuit to an AND gate 12.

In FIG. 16, when the enable signal E is set to "1", a logical product is established with the rise of the clock signal CLK, so that data is written. On the other hand, when the enable signal is set to “0”, the logical product is not established even when the clock signal CLK rises, so that no data is written. As described above, when there is no need to write data, by setting the enable signal E to “0” in accordance with the timing of the clock signal CLK, wasteful power consumption in the flip-flop can be prevented.

In such a gated clock design, the effect of reducing power consumption greatly differs depending on a method of generating an enable signal for determining whether to supply a clock to a memory element such as a register or a memory. Heretofore, there has been a method of designing an enable signal manually by a designer or automatically generating an enable signal by CAD from a control structure of a logic circuit.

[0011]

However, in the conventional gated clock design technique, a method for generating an optimum enable signal has not been proposed from the viewpoint of a power consumption reduction effect or the like. For this reason, it is not possible to determine whether the designed enable signal is the most effective signal and has the greatest power consumption reduction effect, and a gated clock design may be performed using a less optimal enable signal. Was.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to provide a gated clock capable of designing a gated clock using an optimum enable signal having a large power consumption reduction effect. An object of the present invention is to provide a design support device and a gated clock design support method.

[0013]

To achieve the above object, a gated clock design support apparatus according to a first aspect of the present invention is characterized by a gated clock design support apparatus for performing a gated clock design for a logic circuit. ,
A circuit information storage unit for storing information on a logic circuit to be designed; a non-load condition extraction unit for extracting a non-load condition for a storage element based on the information on the logic circuit; , An enable candidate generation unit that generates an enable signal candidate that is a signal candidate to be an enable signal, and a parameter analysis that analyzes an area, a delay time, and power consumption required when the enable signal candidate is designed as a gated clock as an enable signal. Unit, a candidate information storage unit for storing information including an analysis result of the parameter analysis unit as enable signal candidate information on the enable signal candidate, and constraint information on the area, delay time, and power consumption of a logic circuit to be designed. A design constraint input unit for inputting, and the enable No. based on the candidate information and the restriction information, the enable signal selecting unit to select an enable signal that satisfies the design constraints from the enable signal candidates,
A gated clock circuit adding section for adding a gated clock circuit using the enable signal selected by the enable signal selecting section to the logic circuit to be designed.

According to a second aspect of the invention, there is provided a gated clock design support apparatus according to the first aspect, further comprising a condition input unit for inputting a condition that does not require data loading to the storage element, The extraction unit is configured to extract a non-load condition for a storage element based on the condition input from the condition input unit and information on the logic circuit.

According to a third aspect of the invention, there is provided a gated clock design support apparatus according to the first or second aspect, wherein the enable signal selecting section displays the enable signal candidate information in the candidate information storage section in a graph or table. Display means for displaying on a display in the form of (1), and a predetermined enable signal is selected from contents displayed on the display by the display means in accordance with an external operation.

The gated clock design support method according to the fourth invention is characterized in that a non-load condition extracting step of extracting a non-load condition for a storage element based on information on a logic circuit to be designed, An enable candidate generating step of generating an enable signal candidate which is a candidate for a signal to be an enable signal in the gated clock design; and reducing an area, a delay time, and power consumption required when the enable signal candidate is designed as a gated clock as an enable signal. A parameter analysis step of analyzing; a candidate information storage step of storing information including an analysis result of the parameter analysis step in a storage device as enable signal candidate information relating to the enable signal candidate; an area and a delay of the logic circuit to be designed Time and power consumption An enable signal selecting step of selecting an enable signal that satisfies a design constraint from the enable signal candidates based on the constraint information and the enable signal candidate information, and using the enable signal selected in the enable signal selecting step. A gated clock circuit adding step of adding a gated clock circuit to the logic circuit to be designed.

According to a fifth aspect of the invention, there is provided a gated clock design support apparatus according to the fourth aspect, wherein a condition that does not require data loading is input to the storage element before the non-load condition extracting step. Performing a condition inputting step, wherein the non-loading condition extracting step extracts a non-loading condition for the storage element based on the condition input from the condition inputting step and the information on the logic circuit to be designed. It is.

According to a sixth aspect of the present invention, there is provided a gated clock design support method according to the fourth or fifth aspect, wherein the enable signal selecting step includes the step of converting enable signal candidate information in the storage device into a graph or table format. And a predetermined enable signal is selected from the contents displayed on the display in accordance with an external operation.

A seventh aspect of the present invention is a computer-readable recording medium storing a gated clock design support program, which is characterized in that a non-load condition for extracting a non-load condition for a storage element based on information on a logic circuit to be designed. Extracting means; enable candidate generating means for generating an enable signal candidate that is a candidate for a signal to be an enable signal in the gated clock design from the non-load condition; when the enable signal candidate is designed as a gated clock as an enable signal, Parameter analysis means for analyzing required area, delay time, and power consumption; candidate information storage means for storing information including an analysis result of the parameter analysis means in a storage device as enable signal candidate information regarding the enable signal candidate; Logic to design Area of road, on the basis of the restriction information on the delay time and power consumption and the enable signal candidate information, the enable signal selecting means to select an enable signal that satisfies the design constraints from the enable signal candidates,
A gated clock circuit adding unit for adding a gated clock circuit using the enable signal selected by the enable signal selecting unit to the logic circuit to be designed. is there.

According to an eighth aspect of the present invention, a computer-readable recording medium storing a gated clock design support program is characterized in that, in the seventh aspect, a data is stored in a storage element before the non-load condition extracting means. A condition input unit for inputting a condition that does not need to be loaded is performed. The non-load condition extraction unit performs a non-load condition extraction for the storage element based on the condition input from the condition input unit and the information on the logic circuit to be designed. It is to extract load conditions.

According to a ninth aspect of the present invention, a computer-readable recording medium storing a gated clock design support program is characterized in that, in the seventh or eighth aspect, the enable signal selecting means includes an enable signal in the storage device. The object of the present invention is to display signal candidate information on a display in the form of a graph or a table, and select a predetermined enable signal from display contents on the display according to an external operation.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a gated clock design support device, a gated clock design support method, and a computer-readable recording medium storing a gated clock design support program according to the present invention will be described.

(First Embodiment) FIG. 1 is a functional block diagram of a gated clock design support apparatus according to a first embodiment of the present invention.

This gated clock design support device is:
In order to perform a gated clock design for a logic circuit, a circuit information storage unit 1, a non-load condition input unit 2, a non-load condition extraction unit 3, and an enable signal candidate generation unit 4
, An area / delay / power analysis unit 5, an enable signal candidate information storage unit 6, a design constraint input unit 7, an enable signal selection unit 8, and a gated clock circuit addition unit 9.

The circuit information storage unit 1 stores a logic circuit to be designed, that is, circuit information to be designed (for example, FIG.
6 and 9 are stored. The non-load condition input unit 2 inputs a non-load condition (hereinafter referred to as a non-load condition) that does not require data loading to a storage element (for example, a flip-flop) in the circuit information.

The non-load condition extracting unit 3 extracts a non-load condition for the flip-flop based on the condition input from the non-load condition input unit 2 and circuit information to be designed. The enable candidate generation unit 4 generates an enable signal candidate which is a signal candidate to be an enable signal in the gated clock design from the non-load condition.

The area / delay / power analysis unit 5 analyzes the area, delay time, and power consumption required when the generated enable signal candidate is designed as a gated clock as an enable signal. Enable signal candidate information storage unit 6
Stores the enable signal candidate and, in connection with this, stores parameter information including the analysis result of the area / delay / power analysis unit 5 as enable signal candidate information.

The design constraint input unit 7 receives constraint information on the area, delay time, and power consumption of the logic circuit to be designed, and the enable signal selection unit 8 performs design based on the enable signal candidate information and the constraint information. An enable signal satisfying the constraint is selected from the enable signal candidates.

The gated clock circuit adding section 9
Adds a gated clock circuit using the enable signal selected by the enable signal selection unit 8 to the logic circuit to be designed and stores it in the circuit information storage unit 1.

FIG. 2 is a block diagram showing a configuration of a computer for realizing the gated clock design support device shown in FIG.

In the figure, reference numeral 11 denotes a CPU for executing a program.
The CPU 11 has a main storage device 13, a cache memory 14, a memory controller 15, a bus controller 16, a VRAM 17, a display control unit 18, an input device control unit 20, a disk control unit 21, 22 are connected.

The main memory 13 is a DRAM or an SR.
It is a memory configured by the AM and temporarily storing a program to be executed, data for calculation, and data of a calculation result. The cache memory 14 is a CPU on the memory hierarchy.
11 is a high-speed memory interposed between the main storage device 13 and the main storage device 13, and secures a copy of a part of data on the main storage device 13,
The CPU 11 performs reading and writing with respect to the main storage device 13 on behalf of the CPU 11.

The memory controller 15 is provided in the main storage device 1
3 or controls data transfer between the cache memory 14 and the CPU 11. The bus controller 16
It controls data transfer between the CPU 11 and the bus 12. The VRAM 17 is a video RAM that stores data to be displayed on the CRT 19.

The display controller 18 is a circuit constituted by a graphic processor and for displaying data and images on the CRT 19. The input device control unit 20 controls the operation of an input device 23 such as a keyboard and a mouse, and the disk control units 21 and 22 control driving of a hard disk 24 and a CD-ROM 25 as external storage devices, respectively.

Here, the circuit information storage section 1 and the enable signal candidate information storage section 6 of the gated clock design support apparatus shown in FIG. Further, the non-load condition input unit 2 and the design constraint input unit 7 are configured by the input device 23 and the like. Further, the CD-ROM 25 stores CAD software including a gated clock design support program of the present invention (see FIGS. 3 and 4 described later). By loading this gated clock design support program into the main storage device 13 and executing it by the CPU 11, FIG.
The functions of the non-load condition extraction unit 3, enable signal candidate generation unit 4, area / delay / power analysis unit 5, enable signal selection unit 8, and gated clock circuit addition unit 9 shown in FIG. Therefore, in this case, the CD-ROM 25
The present invention is configured as a computer-readable recording medium storing the gated clock design support program of the present invention.

Next, the operation of the gated clock design support apparatus of the present embodiment will be described with reference to the flowcharts shown in FIGS.

First, for each of the storage elements stored in the circuit information storage unit 1, a condition for loading data into this storage element is determined by the non-load condition extraction unit 3 (step S in FIG. 3).
101). Next, it is determined whether or not non-load condition information is input from the non-load condition input unit 2 (step S10).
2). When the non-load condition extraction unit 3 receives the non-load condition information, the sum of the negative of the load condition and the input non-load condition is set as the non-load condition for the target storage element (step S103). If there is no input of the non-load condition information, the negative of the load condition is set as the non-load condition (step S104).

Next, in the enable signal candidate generator 4,
With respect to the non-load conditions generated in steps S103 and S104, storage elements having the same non-load condition are collected as a storage element group (step S105). Step S1
One memory element group generated in step 05 is taken out (step S106). If not, the process ends (step S107).

When the enable signal can be taken out, a candidate for the enable signal is created from the logic representing the non-load condition for the taken out storage element group (step S108 in FIG. 4). The enable signal candidates created in step S108 are stored in the enable signal candidate information storage unit 6, and the storage unit 6
One more candidate is extracted (step S109). If not, the process proceeds to step S113 (step S1).
10). If it can be extracted, the area / delay / power analysis unit 5 calculates the area, delay time, power consumption, and non-load probability of the logical part that generates the extracted enable signal candidate, and stores it in the enable signal candidate information storage unit 6. (Step S111).

Next, the area that increases when the extracted enable signal candidate is used as an enable signal and the power consumption that is reduced are calculated (step S11).
2). Here, returning to step S109, the next enable signal candidate is extracted.

When the processing of steps S111 and S112 is performed on all the enable signal candidates, and the information is stored in the enable signal candidate information storage section 6, the delay time and area input from the design constraint input section 7 are obtained. The enable signal that satisfies the restrictions and the like and has the greatest power reduction effect is selected from the enable signal candidate information storage unit 6 (step S113).

Then, a circuit for realizing a gated clock is added using the selected enable signal (step S114). Here, returning to step S106, the next storage element group is taken out. When the processing of steps S108 to S114 is performed on all the storage element groups, the processing ends.

Next, the operation of each component will be described in detail with reference to a specific example.

First, it is assumed that a logic circuit having the partial circuit shown in FIG. In the figure, FF0, FF1,..., FF31 represent flip-flops of storage elements. The flip-flop has a data input pin D, a clock input pin CK, and a data output pin Q.

M0, M1,..., M31 are multiplexers, and the signal S input to the control pin
When the value of e is "0", the signal value of the input pin 0 is output, and when the value of the signal Se is "1", the signal value of the input pin 1 is output. Specifically, the multiplexers M0, M1,..., M31 are, as shown in FIG.
Two-input AND gates 41 and 42 and two-input OR gate 43
It has a logical structure consisting of

Each of the multiplexers M0, M1,..., M31
The signal Se input to the control pin is a two-input NA using signals a, b, c, and d as shown in FIG.
ND gate 31, 2-input OR gate 32, and 2-input A
Generated by the ND gate 33.

First, in step S101, the non-load condition extracting unit 3 sets the flip-flops FF0 to FF3
The condition for loading data into 1 is obtained as follows.

The logic of the data input pin D of the flip-flop FF0 is as follows: ∧ (a * (b + c * d)) * I0 + (a * (b + c *
d)) * Out. Here, * represents a logical product, + represents a logical sum, and ∧ represents a logical negation. Out is flip-flop FF0
Is output, and when this signal is selected, data is held. When I0 is selected, it indicates data loading. From this, when Out = 0 and I0 = 1 are substituted into the logic of the data input pin D, 条件 (a * (b + c * d)) is obtained as a condition for loading data. The same operation is performed for FF1 to FF31, and all conditions for loading data are obtained as ∧ (a * (b + c * d)).

Next, in step S102, it is determined whether or not non-load condition information has been input from the non-load condition input unit 2. In this case, it is assumed that there is no input. Therefore, in step S104, the load condition に お い て (a *
A * (b + c * d), which is the negative of (b + c * d)), is the non-load condition of the flip-flops FF0, FF1,.

In step S105, the storage elements having the same non-load condition are put together. Here, FF0, FF1,.
Since the FFs 31 have the same non-load condition a * (b + c * d), they are put together as a storage element group.

In step S106, the storage element group is taken out, and in step S108, the enable signal candidate generation unit 4
Generates an enable signal candidate whose non-load condition is "1" when the signal value of the enable signal candidate is "1". In this case, since the non-load condition is a * (b + c * d), the enable signal candidates are a * b, a * c * d, a
* (B + c * d). These three signals are stored in the enable signal candidate information storage unit 6.

In step S109, one candidate is extracted from the enable signal candidates. Here, it is assumed that a * b has been extracted. In step S111, the area / delay / power analysis unit 5 calculates the area, delay time, power consumption, and non-load probability of the logic part that generates the enable signal candidate a * b shown in FIG. The area is the area occupied by the AND gate, and the delay time is the larger one of the times that the signals a and b reach the output terminal via the AND gate. The non-load probability is a probability that the signal value of the signal a * b becomes “1”, and the power consumption of this logical part is obtained during the analysis. Known examples of the power consumption analysis based on the signal probability include F.S. Najm, “Tra
nsite Density, A Stochas
ticMeasure of Activity in
Digital Circuits "(Procee
Ding of 28th Design Autom
ation Conference).

In this embodiment, the enable signal candidate a *
It is assumed that an area 1.5, a delay time 2.8, a power consumption 2.0, and a non-load probability 0.65 are obtained for b. This result is stored in the enable signal candidate information storage unit 6.

Next, in step S112, when the gated clock design is performed using the enable signal candidates a * b, the area of the whole circuit to be increased and the power consumption of the whole circuit to be reduced are obtained. The increase in the area of the entire circuit takes into account the increase in the area of the enable flip-flop required to remove the glitch of the signal, in addition to the logic portion for generating the enable signal candidate (described later in detail).

When the enable signal candidate matches the negative of the load condition, the multiplexer existing on the input side of the flip-flop can be deleted, so that the area of the multiplexer that can be deleted is reduced. In this embodiment, the enable signal candidate a * b does not match the negation of the load condition,
Assume that the increasing area is 10.5.

The power consumption to be reduced is obtained by the power consumption analysis based on the signal probability. The larger the non-load probability of the enable signal candidate, the larger the power consumption to be reduced. Here, the power consumption to be reduced is 30.
Assume that it was 5.

The operations in steps S111 and S112 are also performed for enable signal candidates a * c * d and a * (b + c * d). As a result of performing the operations of steps S111 and S112 on the logical portion for generating the enable signal candidates a * c * d and a * (b + c * d) shown in FIGS. Candidate information storage 6
Assume that information as shown in FIG.

Next, in step S113, first, the design constraint input from the design constraint unit 7 is referred to. Here, only the delay constraint on the enable logic is set.
Assume that 0 is given. Referring to the information stored in the enable signal candidate information storage unit 6, the enable signal candidate a * (b + c * d) has a logic part delay time of 4.5,
Does not meet constraints. Therefore, the enable signal candidate a *
The enable signal selector 8 selects the one with the larger power consumption reduced by b and a * c * d. As a result, the enable signal selector 8 selects a * b as the enable signal.

In step S114, the selected signal a
A gated clock circuit with * b as an enable signal is generated in the gated clock circuit adding unit 9, and the circuit shown in FIG. 9 is stored in the circuit information storage unit 1. That is, the circuit shown in FIG. 9 is different from the circuit shown in FIG.
A gated clock circuit including a two-input NAND gate 51, a flip-flop 52, and an AND gate 53 is added.

Here, the flip-flop 52 is an enable flip-flop necessary for removing the glitch of the signal described above. A case where the flip-flop 52 is not provided will be described with reference to a timing chart of FIG.

When the flip-flop 52 is not provided, the NAND gate 5 for taking the NAND of the signals a and b is used.
One output signal EC is directly input to one input terminal of the AND gate 53 as an enable signal, and the clock signal CLK is input to the other input terminal.
In this case, if the signal EC rises at time t4 during the “H” level period (t1 to t2) of the clock signal CLK, the rise of this signal (time t4) and the fall of the clock signal CLK (time t3) ), A glitch P occurs in the clock GCLK supplied to the clock input pins CK of the flip-flops FF0 to FF31.

In this embodiment, considering this point, the NA
A flip-flop 52 is inserted between the ND gate 51 and the AND gate 53. This flip-flop 52
Is synchronized with the falling edge of the clock signal CLK.
Since C is fetched and output, even if signal EC rises during the “H” level period (t1 to t2) of clock signal CLK, output signal E of flip-flop 52 is output.
N is guaranteed to rise during the “L” level period (t2 to t3) of the clock signal CLK as an enable signal (time t5). As a result, no glitch occurs in the clock GCLK, and malfunction of the circuit can be avoided.

As described above, in the present embodiment, the non-load condition for the storage element is extracted, and the enable signal candidate in the gated clock design is generated based on the condition. Then, the enable signal is selected in consideration of parameters such as the area, delay time, and power consumption of the enable signal candidate. As a result, an effective gated clock design using an optimum enable signal having a large effect of reducing power consumption becomes possible.

(Second Embodiment) In the present embodiment, the case where the non-load condition shown in FIG. 11 is input from the non-load condition input unit 2 in the same configuration as that shown in FIGS. Is what you do. According to the present embodiment for inputting a non-load condition, it is possible to consider conditions that cannot be completely extracted by the non-load condition extraction unit 3 and don't care conditions that do not appear on the logic circuit. Can also generate an optimal enable signal. It is assumed that the information stored in the circuit information storage unit 1 is the same as that shown in FIGS.

In step S101, similarly to the first embodiment, the conditions for loading data into the flip-flops FF1 to FF31 are all ∧ (a * (b + c *).
d)) is obtained. In this case, since there is a non-load condition input, in step S103, the load condition is negated a *.
Let a * (b + c) + $ d, which is the sum of (b + c * d) and the input non-load condition $ d, be the non-load conditions for the flip-flops FF1 to FF31.

In step S105, the flip-flops FF1 to FF31 are put together as a storage element group. In step S108, an enable signal candidate is generated from the non-load condition a * (b + c) + ∧d for this storage element group. Here, a * b, a * c, ∧d, a * (b +
c), a * b + ∧d, a * c + ∧d, a * (b + c *
d), a * (b + C) + ∧d are generated as enable signal candidates.

The operations of steps S111 and S112 are performed on each enable signal candidate, and enable signal candidate information shown in FIG. It is assumed that the design constraint input from the design constraint unit 7 is given 4.0 as the delay constraint on the enable logic, as in the first embodiment.

In step S 113, among the information stored in the enable signal candidate information storage section 6, the enable signal candidate a * b + ∧d which satisfies the delay constraint and has the largest power consumption to be reduced is selected. Is chosen.

In step S114, the selected signal a
A gated clock circuit with * b + $ d as an enable signal is generated in the gated clock circuit adding unit 9, and the circuit shown in FIG. 13 is stored in the circuit information storage unit 1. In other words, the circuit shown in FIG. 13 is different from the circuit shown in FIG. 9 in that the NAND gate 51 is replaced with a two-input AND gate 62 and a two-input NOR gate 63.
Inverter 6 for inverting signal d at one terminal of gate 63
1 output terminal is connected.

(Third Embodiment) In the present embodiment, in a configuration similar to that shown in FIGS. 1 to 4, when the enable signal selecting unit 8 selects an enable signal from the enable signal candidates, the enable signal The candidate information is provided to the user by displaying it on the CRT 19 in the form of a graph or a table, and the user selects an enable signal.

In this example, it is assumed that the information shown in FIG. 12 generated in the second embodiment is stored in the enable signal candidate information storage unit 6. For the eight enable signal candidates, a graph shown in FIG. 14 is generated with the reduced power consumption as the vertical axis and the increased area as the axis, and the CR
It is displayed on T19. The user can select an enable signal by designating a point on the displayed graph. Also, the table shown in FIG.
It is possible to display on the RT 19 and specify the enable signal by the user.

In this case, the enable signal selection unit 8 selects the candidate specified here, and the gated clock circuit addition unit 9 generates a gated clock circuit using the specified signal as an enable signal.

[0073]

As described above in detail, according to the gated clock design support apparatus, the gated clock design support method, and the computer-readable recording medium storing the gated clock design support program according to the present invention, the gated clock is provided. In the design, there is no case where a design is performed using a non-optimal enable signal as in the related art, and an optimal enable signal having a large power consumption reduction effect can be always used. As a result, an effective gated clock design with a large power consumption reduction effect becomes possible.

[Brief description of the drawings]

FIG. 1 is a functional block diagram of a gated clock design support device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a computer for realizing the gated clock design support device shown in FIG.

FIG. 3 is a flowchart showing an operation of the gated clock design support device shown in FIG.

FIG. 4 is a continuation of the flowchart of FIG. 3;

FIG. 5 is a circuit diagram illustrating an example of a logic circuit stored in a circuit information storage unit 1;

FIG. 6 is a diagram showing a logical structure diagram of a multiplexer in FIG. 5;

FIG. 7 is a logical structure diagram illustrating an example of an enable signal candidate.

FIG. 8 is a diagram illustrating an example of information stored in an enable signal candidate information storage unit in the first embodiment.

FIG. 9 is a circuit diagram showing an example of a logic circuit generated using the gated clock design support device of the first embodiment.

FIG. 10 is a timing chart showing the occurrence of a glitch.

FIG. 11 is a diagram illustrating an example of information of a non-load condition input from a non-load condition input unit 2 according to the second embodiment.

FIG. 12 is a diagram illustrating an example of information stored in an enable signal candidate information storage unit in the second embodiment.

FIG. 13 is a circuit diagram showing an example of a logic circuit generated using the gated clock design support device of the second embodiment.

FIG. 14 is a diagram illustrating an example of a graph displaying information stored in an enable signal candidate information storage unit.

FIG. 15 is a partial circuit diagram showing a part of a conventional logic circuit to be logically designed.

FIG. 16 is a circuit configuration diagram of a conventional clock-gated logic circuit.

[Explanation of symbols]

 Reference Signs List 1 circuit information storage unit 2 non-load condition input unit 3 non-load condition extraction unit 4 enable signal candidate generation unit 5 area / delay / power analysis unit 6 enable signal candidate information storage unit 7 design constraint input unit 8 enable signal selection unit 9 gated Clock circuit addition section

Claims (9)

[Claims] 1. A gated clock design support device for performing a gated clock design on a logic circuit, comprising: a circuit information storage unit for storing information on a logic circuit to be designed; and a memory based on the information on the logic circuit. A non-load condition extraction unit that extracts a non-load condition for the element; an enable candidate generation unit that generates, from the non-load condition, an enable signal candidate that is a signal candidate to be an enable signal in gated clock design; A parameter analysis unit that analyzes an area, a delay time, and power consumption required when a gated clock is designed as an enable signal, and stores information including an analysis result of the parameter analysis unit as enable signal candidate information regarding the enable signal candidate. Candidate information storage unit A design constraint input unit for inputting constraint information on an area, a delay time, and power consumption of a logic circuit to be designed; and an enable signal satisfying a design constraint based on the enable signal candidate information and the constraint information. An enable signal selecting unit for selecting from the candidates; and a gated clock circuit adding unit for adding a gated clock circuit using the enable signal selected by the enable signal selecting unit to the logic circuit to be designed. Gated clock design support device. 2. A condition input unit for inputting a condition that does not require data loading to a storage element, wherein the non-load condition extraction unit includes a condition input from the condition input unit and information on the logic circuit. 2. The gated clock design support device according to claim 1, wherein a non-load condition for the storage element is extracted based on the following. 3. The display device according to claim 2, wherein the enable signal selection unit includes display means for displaying the enable signal candidate information in the candidate information storage unit on a display in the form of a graph or a table. 3. The gated clock design support device according to claim 1, wherein a predetermined enable signal is selected according to an external operation. 4. A non-load condition extracting step of extracting a non-load condition for a storage element based on information about a logic circuit to be designed, and from the non-load condition, a signal candidate to be an enable signal in gated clock design. An enable candidate generating step of generating a certain enable signal candidate; a parameter analyzing step of analyzing an area, a delay time, and power consumption required when the enable signal candidate is designed as a gated clock; and an enable for the enable signal candidate. A candidate information storing step of storing information including an analysis result of the parameter analyzing step in a storage device as signal candidate information; constraint information relating to an area, a delay time, and power consumption of the logic circuit to be designed; and the enable signal candidate information And base Selecting an enable signal that satisfies design constraints from the enable signal candidates; and adding a gated clock circuit using the enable signal selected in the enable signal selecting step to the logic circuit to be designed. And a gated clock circuit adding step. 5. The method according to claim 1, wherein before the non-load condition extracting step,
Performing a condition inputting step of inputting a condition that does not require data loading to the storage element; and the non-loading condition extracting step is based on the condition input from the condition inputting step and information on the logic circuit to be designed. 5. The gated clock design support method according to claim 4, wherein a non-load condition for the storage element is extracted. 6. The enable signal selecting step includes displaying enable signal candidate information in the storage device on a display in a graph or table format, and selecting a predetermined enable signal from display contents on the display according to an external operation. The gated clock design support method according to claim 4 or 5, wherein 7. A non-load condition extracting means for extracting a non-load condition for a storage element based on information on a logic circuit to be designed, and a signal candidate to be an enable signal in gated clock design based on the non-load condition. Enable candidate generating means for generating a certain enable signal candidate; parameter analyzing means for analyzing the area, delay time, and power consumption required when the enable signal candidate is designed as a gated clock; and enable for the enable signal candidate. Candidate information storage means for storing information including the analysis result of the parameter analysis means in a storage device as signal candidate information; constraint information on the area, delay time, and power consumption of the logic circuit to be designed; and the enable signal candidate information Satisfy design constraints based on Enable signal selecting means for selecting the enabled enable signal from the enable signal candidates, and gated clock circuit adding means for adding a gated clock circuit using the enable signal selected by the enable signal selecting means to the logic circuit to be designed And a computer-readable recording medium storing a gated clock design support program. 8. A condition input means for inputting a condition that does not require data loading to a storage element is provided before the non-load condition extraction means, wherein the non-load condition extraction means receives an input from the condition input means. 8. A computer-readable recording medium storing a gated clock design support program according to claim 7, wherein a non-load condition for a storage element is extracted based on the determined condition and the information on the logic circuit to be designed. . 9. The enable signal selecting means displays enable signal candidate information in the storage device on a display in the form of a graph or a table, and selects a predetermined enable signal from display contents on the display according to an external operation. A computer-readable recording medium storing a gated clock design support program according to claim 7 or 8.