JPH11149446A - Method and device for transferring serial data - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce system costs by reducing the capacitance of a program in data transfer between a microcomputer and an external LSI, shortening a period for development, accelerating processing, effectively utilizing the function of the microcomputer and reducing external hardwares. SOLUTION: This device has a serial control circuit 12 provided on a microcomputer 10A for serially transferring data between the microcomputer 10A and an external LSI 14 and a wait control circuit 13 for performing the wait control of an instruction execution cycle for a CPU 11 consisting of the microcomputer 10A, and the serial control circuit 12 performs the transfer of serial data by executing a data transfer instruction or data input/output instruction. In this case, the serial control circuit 12 reports the end of data transfer to the wait control circuit 13 so that a wait state can be canceled.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer having a means for serial data transfer with an external device, and more particularly to a wait cycle inserted during execution of a data transfer instruction or a data input / output instruction until data transfer is completed. The present invention relates to a serial data transfer method and apparatus for simplifying and speeding up data transfer processing.

[0002]

2. Description of the Related Art A conventional example will be described in detail with reference to the drawings.

FIG. 8 is a block diagram showing a configuration of a conventional data transfer device using a bus interface.

[0004] The data transfer device shown in FIG. 8 is schematically constituted by a microcomputer 10a, an external LSI 82, and a bus interface for connecting these. The microcomputer 10a has a CPU 1 inside.
1, a bus control circuit 80, and a wait control circuit 13, and are connected to an external LSI 82 via a bus interface including an external control circuit 81.

Next, a data transfer (at the time of reading) operation by the conventional bus interface shown in FIG. 8 will be described in detail with reference to the drawings.

FIG. 9 is a timing chart at the time of data reading of a conventional data transfer device. FIG. 10 shows a program at the time of data reading in a conventional data transfer device using a bus interface. FIG. 11 is a flowchart showing a processing procedure at the time of data reading in a conventional data transfer device using a bus interface.

In data transfer by a bus interface, wait control is generally widely used. In the wait control, when a data transfer instruction or a data input / output instruction is executed, data transfer is performed by inserting a wait cycle corresponding to an access time of a target external LSI. This is because it takes more time to access the external LSI than to access inside the microcomputer.

[0008] The microcomputer 10a is an external LSI.
When reading data from 82,
The read operation is performed by executing the read command (step S100) as shown in FIG. Specifically, when the CPU 11 executes the read command (step S1100 in FIG. 11, the same applies hereinafter), a bus control signal (address signal or control signal) is output from the bus control circuit 80 (step S1101), and the external control circuit 81 And the external LSI 82.

When the CPU 11 executes the read instruction, it activates a data read start signal 1b,
Notifying the wait control circuit 13 of the start of the read operation,
The monitoring of the WAIT signal is started.

The external control circuit 81 generates RD and CS signals required for accessing the external LSI 82 from the address and control signals (step S110).
2), supply to the external LSI 82 and the weight control circuit 13. When the RD and CS signals are input, the external LSI 82 starts outputting data (step S1103), and the bus control circuit 80 starts reading data from the data bus (step S1104).

When the time required for data transfer has elapsed, the external control circuit 81 activates the WAIT signal,
It notifies the wait control circuit 13 (T30). As a result, the wait control circuit 13, which has continued monitoring (step S1105) until the WAIT signal becomes active,
At the timing when the WAIT signal becomes active (timing T90 in FIG. 9), the wait state is released (step S1106), and the data read end signal 1a is activated to notify the bus control circuit 80 and the CPU 11.

When the data read end signal 1a is input, the bus control circuit 80 stops outputting a bus control signal (address signal or control signal) and ends the read operation (step S1107). When the data read end signal 1a is input, the CPU 11 terminates the execution of the read command after the actual read operation (step S1108), and makes the data read start signal 1b inactive.

When the data read start signal 1b becomes inactive, the wait control circuit 13 makes the data read end signal 1a inactive. And CP
When a series of operations of the wait control ends, U11 starts executing the next instruction (step S110).
9).

Next, another conventional example will be described with reference to the drawings.

FIG. 12 is a block diagram showing a configuration of a conventional data transfer device using a serial interface.

The data transfer device shown in FIG. 12 is schematically constituted by a microcomputer 10b, an external LSI 14, and a serial interface for connecting these. The microcomputer 10b has C inside
It includes a PU 11, a serial control circuit 120, and an interrupt control circuit 121, and is connected to the external LSI 14 via a serial interface.

Next, the data transfer (at the time of reading) operation by the conventional serial interface shown in FIG. 12 will be described in detail with reference to the drawings.

FIG. 13 is a block diagram showing a configuration of serial control circuit 120 shown in FIG. FIG. 14 is a timing chart of a conventional data transfer device using a serial interface at the time of data reading. FIG. 15 shows a program at the time of data reading in a conventional data transfer device using a serial interface. FIG. 16 is a flowchart showing a processing procedure at the time of data reading in a conventional data transfer device using a serial interface.

As shown in FIG.
0 is the shift register 20 and the control register 130
, A latch circuit 22, a clock control circuit 23, a clock selection circuit 24, a counter 25, and an interrupt generation circuit 131. The serial control circuit 1
The control of the operation, mode, etc. of 20 is performed by setting the control register 180 (command input, etc.).
Here, the description will be made assuming that the read operation (8 bits) and the CLK signal are set to be valid.

In data transfer by the serial interface, a clock synchronous three-wire serial is generally widely used.

The microcomputer 10b is an external LSI
In the case of reading data from 14, the read command (step S150) as shown in FIG. 15 is executed, and then the actual read operation is performed by interrupt processing. Specifically, C
When the PU 11 executes the read instruction (step S160)
0), the SCK signal is output from the serial control circuit 120 (step S1601), and supplied to the external LSI 14. The external LSI 14 starts outputting data when the SCK signal is input (step S1602).

The serial control circuit 120 reads data from the SI signal in synchronization with the SCK signal (step S1603). When the read operation ends (step S1604, step S1604),
1605), and generate an INT signal (step S160)
6, timing T140), and notifies the interrupt control circuit 121.

When the INT signal is input, the interrupt control circuit 121 activates the interrupt request signal 12a and requests the CPU 11 to perform an interrupt process (step S1607). Upon receiving the interrupt (step S1608), the CPU 11 suspends the processing until the interrupt is enabled (step S1609). When the interrupt processing becomes possible, the CPU 11 performs pre-interrupt processing (step S1610), and refers to the vector table. Then, a jump instruction to the interrupt processing routine is executed (step S1612).

The CPU 11 performs the processing described above,
The interrupt process is started (step S1613), and after the actual read operation (step S1614, step S15)
1) Perform post-interrupt processing (step S161)
5), end the interrupt processing. Upon completion of the series of operations of the interrupt processing, the CPU 11 starts executing the next instruction (step S1616).

Next, the operation of the serial control circuit 120 will be described.
This will be described in detail with reference to FIG.

The clock selection circuit 24 selects the CLK signal output from the CPU 11 and the SCK signal input from the outside. In this description, the control register 1
It is assumed that the CLK signal is selected by setting 30.

The CPU 11 issues a read command (step S15).
0: dummy read of the shift register 20), the clock control circuit 23
And outputs the clock signal 2a selected in step (1) as the SCK signal, and activates the read start signal 2b to the counter 25. Data from the external LSI 14 is input from the SI signal, and the clock control circuit 2
3 is stored in the shift register 20 in synchronization with the clock signal 2c from the third register.

The counter 25 reads the read start signal 2b
Is input, the clock signal 2a (SCK signal)
When the eighth clock signal 2a, for example, is input as the number of waits for the time required for data transfer, the read end signal 2d is activated and notified to the clock control circuit 23 and the interrupt generation circuit 131. I do. The clock control circuit 23 outputs the read end signal 2d
Is input, the output of the SCK signal is stopped. When the read end signal 2d is input, the interrupt generation circuit 131 activates the INT signal and notifies the CPU 11 that the data input from the SI signal has ended.

However, in the above-mentioned conventional data transfer apparatus, when the microcomputer and the external LSI are connected by a bus interface, the microcomputer, especially a product in which the memory and the peripheral I / O functions are integrated into one chip, requires a signal. Since most of the lines are multiplexed, if these are used as signals for the bus interface, there is a problem that signals for peripheral I / O cannot be used. Also, the signals for the bus interface are specified with emphasis on versatility,
When connecting an external LSI, there is a problem that hardware must be added to the outside.

On the other hand, a microcomputer and an external LSI
In the case of a conventional data transfer device in which a microcomputer is connected with a serial interface, the conventional serial interface built into the microcomputer performs actual data input / output processing in the data transfer using an interrupt. There has been a problem that the capacity is increased, the development efficiency is reduced, and the processing time is increased.

[0031]

As described above,
In the above-mentioned conventional technology, in the case of a data transfer device configured by connecting a microcomputer and an external LSI via a bus interface, many signal lines are required for connection and an external control circuit is required. However, there is a problem that the function of the device is deteriorated and the hardware scale is increased.

On the other hand, a microcomputer and an external LSI
Is connected by a serial interface, the number of connected signal lines is reduced,
Since a program for data transfer involves complicated processing such as interruption, there is a problem (defect) that the program capacity is increased, development efficiency is reduced, and processing time is increased.

Accordingly, an object of the present invention is to reduce the program capacity, shorten the development period and speed up the processing in the data transfer between the microcomputer and the external LSI, to effectively use the microcomputer function, and to reduce the external hardware. It is an object of the present invention to provide a serial data transfer method and apparatus capable of reducing the system cost by the method.

[0034]

In order to achieve the above object, according to the present invention, a wait cycle is inserted into a data transfer instruction or a data input / output instruction after the start of data transfer.
The wait is automatically released after the data transfer is completed. Specifically, execution of a data transfer command or a data output command results in two or three commands.
The serial data transfer with the external LSI is performed by the serial data transfer signal. After the execution of the instruction is started, the bus cycle enters a wait state. After the end of serial data transfer, the wait control circuit requests release of wait,
The wait state is released.

Further, according to the present invention, the control register is set in advance so as to notify the wait control circuit after the data transfer is completed, and the execution of the data transfer instruction or the data input / output instruction causes the execution of two or three lines. Serial data transfer with an external LSI is performed by a serial data transfer signal. After the execution of the instruction is started, the bus cycle enters a wait state. After the end of the serial data transfer, the wait control circuit requests the release of the wait, and the wait state is released.

Further, according to the present invention, the number of waits corresponding to the time required for data transfer is set in advance in the wait register, and two or three serial registers are executed by executing a data transfer instruction or a data input / output instruction. Serial data transfer with an external LSI is performed via a data transfer signal. After the execution of the instruction is started, the bus cycle enters a wait state. The wait control circuit inserts wait cycles for the number of waits set in the wait register, and then releases the wait state.

Further, according to the present invention, the control register is set in advance so as to notify the wait control circuit after the data transfer is completed. And serial data transfer with an external LSI via the serial data transfer signal. After the execution of the instruction is started, the bus cycle enters a wait state. The wait control circuit inserts wait cycles for the number of waits set in the wait register, and then releases the wait state.

According to the present invention, after the data transfer is started, the data transfer instruction or the data input / output instruction is waited for.
By inserting a cycle and automatically releasing the wait after the data transfer is completed, the external LSI can be executed only by executing a data transfer instruction or a data output instruction.
This makes it possible to reduce the program capacity, shorten the development period, and speed up the processing. In addition, since an external LSI can be connected only by a serial interface, connecting a microcomputer to the external LSI using a bus interface as in the prior art allows peripheral I / O to be connected.
There is no need to use some of the functions or to add external hardware between the microcomputer and the external LSI. This makes it possible to make effective use of the microcomputer functions and to reduce the system cost by reducing the external hardware. Reduction is possible.

[0039]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the serial data transfer device of the present invention.

The serial data transfer device of the present invention shown in FIG.
, A serial control circuit 12 and a weight control circuit 13
And an external LSI 14.

FIG. 2 shows the serial control circuit 1 shown in FIG.
FIG. 2 is a block diagram showing an internal configuration of the second embodiment.

The serial control circuit 12 shown in FIG. 2 comprises a serial register 20, a control register 21, a latch circuit 22, a clock control circuit 23, a clock selection circuit 24, a counter 25, an interrupt generation circuit 26,
The access control circuit 27 is provided. The operation mode of the serial control circuit 12 is set by setting the control register 21. In the following description, the read operation (8 bits), the CLK signal valid, the interrupt generation circuit 2
The description will be made assuming that 6 is set invalid and the access control circuit 27 is set valid.

Hereinafter, the data transfer (at the time of reading) operation in the first embodiment of the present invention shown in FIG. 1 will be described in detail with reference to the drawings.

FIG. 3 is a timing chart at the time of data reading in the embodiment of the present invention. FIG. 4 is a program at the time of data reading of the serial data transfer device according to the embodiment of the present invention. FIG. 5 is a diagram showing the data transfer of the serial data transfer device according to the embodiment of the present invention.
It is a flowchart which shows the processing procedure at the time of a read.

The microcomputer 10A is an external LSI
When data is read from 14, a read operation is performed by executing a read command (step S40) as shown in FIG. Specifically, when the CPU 11 executes the read command (Step S500 in FIG. 5), the serial control circuit 1
2 outputs an SCK signal (step S501) and supplies it to the external LSI 14. When executing the read command, the CPU 11 activates the data read start signal 1b, notifies the wait control circuit 13 of the start of the read operation, and starts monitoring the SWAIT signal. External LS
Upon receiving the SCK signal, the I14 starts outputting data (step S502).

The serial control circuit 12 reads data from the SI signal in synchronization with the SCK signal (step S503). When the read operation ends (steps S504 and S505), the serial control circuit 12
It generates a WAIT signal (step S506, timing T30) and notifies the wait control circuit 13.

The wait control circuit 13 continues monitoring until the SWAIT signal becomes active (step S).
507), when the SWAIT signal becomes active (timing T30), the wait state is released, the data read end signal 1a is made active, and the CPU 11 is notified (step S508). When the data read end signal 1a is input, the CPU 11 ends the execution of the read command after the actual read operation (step S50).
9) Make the data read start signal 1b inactive.

When the data read start signal 1b becomes inactive, the wait control circuit 13 makes the data read end signal 1a inactive. CPU11
After the series of operations of the wait control is completed, the execution of the next instruction is started (step S510).

Next, the operation of the serial control circuit 12 will be described in detail with reference to FIG. As described above, the clock selection circuit 24 outputs the CLK output from the CPU 11.
Select the signal and the SCK signal input from the outside,
In this description, it is assumed that the CLK signal is selected by the setting of the control register 21.

When the CPU 11 executes the read command (step S40: dummy read of the shift register 20), the clock control circuit 23
Then, the clock signal 2a selected in step (1) is output as the SCK signal, and the read start signal 2b is activated to notify the counter 25. Data from the external LSI 14 is supplied by an SI signal, and the clock control circuit 23
, And are sequentially stored in the shift register 20 in synchronization with the clock signal 2c.

When the read start signal 2b is supplied, the counter 25 starts counting the clock signal 2a (SCK signal), for example, the eighth clock signal 2a which is the count number for the time required for data transfer. Is input, the read end signal 2d is made active and the interrupt generation circuit 26 and the access control circuit 27 are notified. The clock control circuit 23 stops outputting the SCK signal when the read end signal 2d is supplied.

Since the interrupt generation circuit 26 and the access control circuit 27 are set to inactive and active, respectively, by the control signal 2e and the control signal 2f supplied from the control register 21, the access control circuit 27 terminates the read. When the signal 2d is supplied, the SWAIT signal is activated to notify the CPU 11 that the data input from the SI signal has been completed.

Next, a second embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 6 is a block diagram showing a second embodiment of the serial data transfer device of the present invention.

The serial data transfer device of the present invention shown in FIG.
, Serial control circuit 12 and wait register 60
, A weight control circuit 13 and an external LSI 14.

The wait register 60 is a register for setting the number of waits in the instruction execution cycle of the CPU 11, and it is assumed that an arbitrary value is revised for convenience of explanation. The serial control circuit 12 has the same configuration as that of FIG. 2 used in the description of the first embodiment of the present invention.

Further, the operation mode of the serial control circuit 12 is performed by setting the control register 21, but in the following description, the read operation (8 bits), CLK
The description will be made on the assumption that the signal is valid, the interrupt generation circuit 26 is invalid, and the access control circuit 27 is invalid.

Hereinafter, a data transfer (at the time of reading) operation in the second embodiment of the present invention shown in FIG. 6 will be described in detail with reference to the drawings. The timing chart at the time of data reading and the program at the time of data reading have the same configuration as that shown in FIGS. 3 and 4 used in the description of the first embodiment of the present invention. FIG. 7 is a flowchart showing a processing procedure at the time of data reading of the serial data transfer device in FIG.

The microcomputer 10B is an external LSI
When reading data from 14, the CPU 11
The read operation is performed by executing the read command (step S40) as shown in FIG. Specifically, when the CPU 11 executes the read command (step S
700), the SCK signal is output from the serial control circuit 12 (step S701), and supplied to the external LSI 14. When the CPU 11 executes the read instruction, the data
Activate the read start signal 1b and start the read operation by the wait register 60 and the wait control circuit 1
Notify 3.

Upon receiving the data read start signal 1b, the wait register 60 starts monitoring the number of waits (step S702), and the wait control circuit 13 receives the data read start signal 1b. Then, monitoring of the SWAIT signal is started (step S70).
8).

The external LSI 14 starts outputting data when the SCK signal is supplied (step S703). The serial control circuit 12 synchronizes with the SCK signal and continues reading data from the SI signal until the read is completed (steps S704, S705, and S70).
6). When the set wait number is reached, the wait register 60 activates the SWAIT signal (step S707) and notifies the wait control circuit 13.

The wait control circuit 13 continues monitoring (step S708) until the SWAIT signal becomes active, and when it becomes active (timing T30),
The wait state is released (step S709), and the data
The read end signal 1a is activated to notify the CPU 11.

The CPU 11 outputs a data read end signal 1
When a is supplied, after the actual read operation, the execution of the read instruction is terminated (step S710), and the data read start signal 1b is made inactive. When the data read start signal 1b becomes inactive, the wait control circuit 13 makes the data read end signal 1a inactive. When the series of operations of the wait control is completed, the CPU 11 starts executing the next instruction (step S711).

Next, the operation of the serial control circuit 12 will be described in detail with reference to FIG.

The clock selection circuit 24 selects the CLK signal output from the CPU 11 and the SCK signal input from the outside. In the present invention, description will be made assuming that the CLK signal is selected by the setting of the control register 21.

The CPU 11 issues a read instruction (step S4).
0: dummy read of the shift register 20), the clock control circuit 23
Then, the clock signal 2a selected in step (1) is output as the SCK signal, and the read start signal 2b is activated to notify the counter 25.

Data from the external LSI 14 is supplied by an SI signal, and is sequentially stored in the shift register 20 in synchronization with the clock signal 2c from the clock control circuit 23. When the counter 25 is supplied with the read start signal 2b, the counter 25 starts counting the clock signal 2a (SCK signal), and receives, for example, an eighth clock signal 2a which is a count for the time required for data transfer. And the read end signal 2d are activated, and the interrupt generation circuit 2
6 and the access control circuit 27.

The clock control circuit 23 stops outputting the SCK signal when the read end signal 2d is input. At this time, the interrupt generation circuit 26 and the access control circuit 27
Are set inactive by the control signal 2e and the control signal 2f supplied from the control register 21, respectively. Therefore, the interrupt generation circuit 26 and the access control circuit 27 do not generate the INT signal and the SWAIT signal even when the read operation ends.

In the above description, in the data transfer operation, data read (input) by execution of a read instruction
Has been described as an example, but it goes without saying that a similar effect can be obtained also in writing (outputting) data by executing a write instruction.

In the present invention, the control register 21
By setting the interrupt generation circuit 26 to be valid and the access control circuit 27 to be invalid, the data transfer according to the conventional method is also possible.

[0072]

As described above, according to the present invention, the program capacity can be reduced, the development period can be shortened, the processing can be speeded up, and the microcomputer function can be effectively used. Thus, system cost can be reduced by reducing external hardware.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a serial data transfer device according to the present invention.

FIG. 2 is a block diagram showing an internal configuration of a serial control circuit 12 in FIG.

FIG. 3 is a timing chart at the time of data reading according to the embodiment of the present invention.

FIG. 4 is a program at the time of data reading of the serial data transfer device according to the embodiment of the present invention.

FIG. 5 is a flowchart showing a processing procedure at the time of data reading of the serial data transfer device according to the embodiment of the present invention.

FIG. 6 is a block diagram showing a second embodiment of the serial data transfer device of the present invention.

FIG. 7 is a flowchart showing a processing procedure at the time of data reading of the serial data transfer device according to the embodiment of the present invention.

FIG. 8 is a block diagram showing a configuration of a conventional data transfer device using a bus interface.

FIG. 9 is a timing chart at the time of data reading of a conventional data transfer device.

FIG. 10 shows a program at the time of data reading in a data transfer device using a conventional bus interface.

FIG. 11 is a flowchart showing a processing procedure at the time of data reading in a conventional data transfer device using a bus interface.

FIG. 12 is a block diagram showing a configuration of a conventional data transfer device using a serial interface.

FIG. 13 is a block diagram showing a configuration of a serial control circuit 120 in FIG.

FIG. 14 is a timing chart of a conventional data transfer device using a serial interface when data is read.
It is a chart.

FIG. 15 is a program at the time of data reading in a conventional data transfer device using a serial interface.

FIG. 16 is a flowchart showing a processing procedure at the time of data reading in a conventional data transfer device using a serial interface.

[Explanation of symbols]

 Reference Signs List 10 microcomputer 11 CPU 12 serial control circuit 13 wait control circuit 14 external LSI 1a data read end signal 1b data read start signal 20 shift register 21 control register 22 latch circuit 23 clock control circuit 24 clock selection circuit 25 counter 26 interrupt Generation circuit 27 Access control circuit 2a Clock signal 2b Read start signal 2c Clock signal 2d Read end signal 2e Control signal 2f Control signal T30 Timing of SWAIT signal S40 Read command 60 Wait register 80 Bus control circuit 81 External control circuit 82 External LSI T90 WAIT signal timing S100 Read command 120 Serial control circuit 121 Interrupt control circuit 12a Interrupt request signal 13 0 Control register 131 Interrupt generation circuit T140 Timing of INT signal S150 Read command S151 Read command

Claims (10)

[Claims] A serial control circuit provided on the CPU side for serially transferring data between the CPU and an external LSI; and a wait control circuit for performing weight control of an instruction execution cycle of the CPU. A serial data transfer device in which the serial control circuit transfers serial data by executing a data transfer instruction or a data input / output instruction, wherein the serial control circuit notifies the wait control circuit of the end of the data transfer. A serial data transfer device for canceling a wait state by using the serial data transfer device. 2. The serial control circuit includes: an interrupt generation circuit that generates an interrupt request signal at the end of data transfer; a unit that outputs the interrupt request signal to the outside; 2. A serial register according to claim 1, further comprising: a control register for setting whether to notify or output the interrupt request signal.
Data transfer device. A serial control circuit provided on the CPU side for serially transferring data between the CPU and the external LSI; and a wait control circuit for performing weight control of an instruction execution cycle of the CPU. A serial data transfer device in which the serial control circuit transfers serial data by executing a data transfer instruction or a data input / output instruction, wherein the serial control circuit sets a predetermined number of wait cycles required for the data transfer Means for monitoring the number of wait cycles, and means for generating a wait cycle number progress signal when the number of wait cycles exceeds a predetermined number of wait cycles, the weight control circuit comprising: Releasing the wait state upon detection of the wait cycle number elapsed signal. Serial data transfer apparatus according to claim. 4. The serial control circuit includes: an interrupt generation circuit for generating an interrupt request signal at the end of data transfer; a means for outputting the interrupt request signal to an external device; And a control register for setting whether the notification is made or outputting the interrupt request signal.
Data transfer device. 5. The serial data transfer according to claim 1, wherein the data transfer between the CPU and the external LSI through the serial interface is a clock synchronous three-wire serial. apparatus. 6. A serial control circuit provided on the CPU side for transferring data serially between the CPU and the six external LSIs, and a wait control circuit for performing weight control of an instruction execution cycle of the CPU. A serial data transfer method in which the serial control circuit transfers serial data by executing a data transfer instruction or a data input / output instruction, wherein the serial control circuit monitors completion of the data transfer, Detecting the end of the transfer of the data, and sending a detection signal to the wait control circuit. 7. The serial control circuit generates an interrupt request signal at the end of data transfer, outputs the interrupt request signal to the outside, and notifies the wait control circuit at the end of the data transfer, or the interrupt request signal. 7. The serial data transfer method according to claim 6, wherein a signal is output. 8. A serial control circuit provided on the CPU side for serially transferring data between the CPU and an external LSI, and a wait control circuit for performing weight control of an instruction execution cycle of the CPU. A serial data transfer method in which the serial control circuit transfers serial data by executing a data transfer instruction or a data input / output instruction, wherein the serial control circuit sets a predetermined number of wait cycles required for the data transfer Monitoring the number of wait cycles, and when the number of wait cycles elapses a predetermined number of wait cycles, generates a wait cycle number elapse signal; and the wait control circuit outputs the wait cycle number elapse signal. Serial data transfer characterized by releasing wait state when detected Law. 9. The serial control circuit generates an interrupt request signal at the end of data transfer, outputs the interrupt request signal to the outside, notifies the wait control circuit after the wait cycle has elapsed, or outputs the interrupt request signal. 9. The serial data transfer method according to claim 8, wherein a request signal is output. 10. A data transfer between a CPU and an external LSI through a serial interface by a clock synchronous three-wire serial.
The serial data transfer device according to any one of the above.