JPH11149441A - Bus bridge circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a bus bridge circuit with which the efficiency of a system can be improved by decreasing the number of times for loading wait to a CPU in the case of reading data from various kinds of extension equipment on a general-purpose bus. SOLUTION: When a write address coincidence signal (WM) is made active, an address cache controller 11 applies a latched read address to an address/data multiplexer 14. Further, the address cache controller 11 controls a bus controller 13 and starts burst read from the address applied to the address/data multiplexer 14, and data are fetched by a read FIFO 17. When the data required for a CPU 2 are already fetched into the read FIFO 17, without loading wait to the CPU, the address cache controller 1 transfers data to the CPU.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus bridge circuit installed between a local bus and a general-purpose bus of a computer and arbitrating both buses.

[0002]

2. Description of the Related Art As shown in FIG. 6, a local bus 300 on the CPU 2 side of a computer device is replaced with a general-purpose bus 400 such as a PCI bus to which various extension devices 200 are connected.
A bus bridge circuit 100 is provided in order to convert the data into. The bus bridge circuit 100 is required to have a function of buffering the speed difference in order to connect the local bus 300 that can operate at high speed to the general-purpose bus 400 that is slower than the local bus 300. At this time, it is important that the efficiency of the high-speed local bus 300 is not reduced as much as possible.

Conventionally, in a bus bridge circuit, an FIF
Circuits for temporarily storing data such as O have been used. FIG. 7 is a block diagram showing an example of a conventional bus bridge circuit. As shown in FIG.
, Control signals for both the local bus 300 and the general-purpose bus 400 are input. The bus controller 13 arbitrates the cycles of the buses 300 and 400 and outputs a command signal, a ready signal, and the like. Further, it controls the address / data multiplexer 14 and the FIFO controller 15.

[0004] The address / data multiplexer 14 comprises:
General-purpose bus 4 using the same bus for address and data
For 00, it mainly works to switch between address and data. The FIFO controller 15 has a write FIFO
16 and the read FIFO 17 to control data capture and output. The write FIFO 16 has a CP
U2 is a target on the general-purpose bus 400 (various extension devices 2
00) is held. Also,
The read FIFO 17 holds data that the CPU 2 reads from the target.

In the data write operation from the CPU 2, as long as the write FIFO 16 has a free space, the CPU 2 does not wait and the data is sequentially taken into the write FIFO 16. General purpose bus 4 from write FIFO 16
Data writing to the target connected to 00 is performed sequentially according to the speed of the target. On the other hand, CPU2
In the data read operation, the data of an address continuous from the first accessed address is read ahead from the target and taken into the read FIFO 17. C
The PU 2 can take out the data once taken into the read FIFO 17 with no wait.

[0006]

However, in the conventional bus bridge circuit, since the circuit starts operating after the CPU 2 starts read access to the target, the general-purpose bus is started after the cycle of the local bus 300 is started. 4
At 00, it takes time until the actual data transfer cycle starts. For example, a delay occurs in the bus bridge circuit to synchronize both buses. In a bus where addresses and data are shared, such as a PCI bus,
First, the address phase is executed, and then the actual data transfer cycle starts. For this reason, there is a problem that the bus controller 13 must always wait for the CPU in the first access. further,
Since it takes time until data is stored in the read FIFO 17, the read operation of the CPU 2
If the data transfer operation to O17 has caught up, the wait must also be applied. That is, the conventional bus bridge circuit includes the local bus 300
However, there is a problem that the efficiency of the system is reduced and the efficiency of the system is reduced.

The present invention has been made to solve such a problem, and can reduce the number of times the CPU is waited when reading data from various extension devices on a general-purpose bus. An object of the present invention is to provide a bus bridge circuit capable of improving efficiency.

[0008]

A bus bridge circuit according to the present invention is provided between a local bus of a computer and a general-purpose bus, and a read cycle for an extension device connected to the general-purpose bus is started. Before reading the data from the extension device by predicting the read address in the read cycle and causing the read data holding means to hold the data. The prediction reading means may include a plurality of address storage means for storing the read address output to the local bus and the write address generated immediately before the read cycle in which the read address was output. Predictive reading means for outputting a write address match signal when the write address output to the local bus matches a write address stored in the address storage means; Then, the configuration may further include general-purpose bus read control means for reading data from the read address stored in the address storage means and causing the read data holding means to hold the data. The predictive reading means includes a second comparing means for outputting a read address match signal when the read address from which the data held in the read data holding means has been read matches the read address output to the local bus; And a transfer unit for transferring the data held in the read data holding unit to the local bus side when the read address match signal is output. And the prediction reading means includes:
A third comparing means for outputting an address match signal when the read address stored in the address storage means matches the write address output to the local bus; and a read data holding means when the address match signal is output. The configuration may further include a retained data management unit that invalidates retained data. In addition, expansion equipment
For example, a video controller having a video memory.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of a computer device including a bus bridge circuit according to the present invention. As shown in the figure, the bus bridge circuit 1
A local bus 300 output from the CPU 2, a video controller (video memory) 3, and various memories I
/ O4 is connected to the connected general-purpose bus 400.
The bus bridge circuit 1 arbitrates buses operating asynchronously, and controls bidirectional data transfer.

FIG. 2 is a block diagram showing one configuration example of the bus bridge circuit 1. As shown in FIG. The address cache controller 11 receives the local bus control signal and outputs an address latch signal (AL), a write address latch signal (WA) and a read address latch signal (RA) to the address cache 12. The address cache 12
, A write address match signal (WM) and a read address match signal (RM) are input from the
Control of the general-purpose bus 400 and control of the FIFO controller 15 and the read FIFO 17. Further, it manages whether or not valid data is held in the read FIFO 17. The address cache 12 stores a write address and a read address. The address cache 12 compares the stored address with the address in the current cycle, outputs the comparison result to the address cache controller 11, and outputs one selected address to the address / data multiplexer 14.

The bus controller 13 receives control signals from both the local bus 300 and the general-purpose bus 400 and signals from the address cache controller 11. The bus controller 13 arbitrates the cycles of both buses and outputs a command signal, a ready signal, and the like.
The bus controller 13 further controls the address / data multiplexer 14 and the FIFO controller 15. The address / data multiplexer 14 switches the address and the data to the general-purpose bus 400 using the same bus as the address and the data. Further, the address of the local bus 300 and the address of the address cache 12 are selected. The FIFO controller 15 controls a write FIFO 16 and a read FIFO 17,
Control data capture and output. Write FIFO1
6 holds data written by the CPU 2 to a target (video controller 3 or various memories / I / Os 4) on the general-purpose bus 400. The read FIFO 17 holds data read from the target by the CPU 2.

FIG. 3 is a block diagram showing the internal configuration of the address cache 12. The address latch 12a
Temporarily holds the local bus address. The address storage / comparison circuit 12b receives the latched address from the address latch 12a and the local bus address from the local bus 300, and further receives an address latch signal from the address cache controller 11. The address storage / comparison circuit 12b outputs an address stored therein and outputs a signal of a comparison result. The address storage / comparison circuit 12b
Are mounted in plural sets. The address selector 12c receives the latched read address and the write address coincidence signal from all the address storage / comparison circuits 12b, and outputs the latched output from the address storage / comparison circuit 12b where the write address coincidence signal is active. A read address is selected and output as a latched read address.

FIG. 4 shows each address storage / comparison circuit 12b.
FIG. 2 is a block diagram showing an internal configuration of the device. The write address latch 121 receives the latched address from the address latch 12a and the write address latch signal from the address cache controller 11, and latches the write address generated immediately before the read operation. The read address latch 122 inputs a local bus address from the local bus 300 and a read address latch signal from the address cache controller 11, and latches the read address. The write address comparison circuit 123 receives the address from the write address latch 121 and the local bus address and outputs a write address match signal. Further, the read address comparison circuit 124 receives the latched read address from the read address latch 122 and the local bus address (write address and read address from the CPU 2) and outputs a read address match signal.

In this embodiment, the read data holding means is realized by the read FIFO 17, and the address storage means is the write address latch 121 and the read address latch 12 in the address storage / comparison circuit 12b.
2 is realized. The first comparing means is realized by the write address comparing circuit 123 in the address storage / comparing circuit 12b, and the second comparing means and the third comparing means are realized by the read address comparing circuit 124.
The general-purpose bus read control means is realized by the address cache controller 11 and the bus controller 13, and the transfer means and the held data management means comprise the address cache controller 11 and the FIFO controller 15.
And is realized in.

Next, the operation will be described with reference to the flowchart of FIG. Since the operation of the write FIFO 16 is the same as that of the conventional bus bridge circuit, the description thereof will be omitted, and the description will focus on the operation around the address cache, which is a feature of the present invention.

First, the address cache controller 1
1 determines whether the CPU 2 performs a read operation or a write operation based on a local bus control signal (step S1). If it is determined that the write operation is performed, the address cache controller 11 outputs an address latch signal and causes the address latch 12a to latch the write address (Step S2).

Subsequently, each address storage / comparison circuit 12b
The read address comparison circuit 124 compares the latched read address (see step S14 described later) with the write address. If they match, the read address comparison circuit 124 activates the read address match signal. When the read address match signal becomes active, if the data previously read from the latched read address has already been taken into the read FIFO 17,
Invalidates the contents of the read FIFO 17 (step S
3). As described later, when a latched read address exists, data from the latched read address may be stored in the read FIFO 17.
The fact that the latched read address matches the write address means that the data stored in the read FIFO 17 is rewritten at the write destination connected to the general-purpose bus 400. That is, the read FI
This means that the data stored in the FO 17 becomes old data. Therefore, such data is invalidated.

Next, each address storage / comparison circuit 12b
The write address comparison circuit 123 compares the address latched in the write address latch 121 with the write address (step S4). If they match, the write address comparison circuit 123 activates the write address match signal. When the write address match signal is inactive, the process returns to step S1, and when active, the process proceeds to step S5. In step S5, the address cache controller 11 continues to
2 monitors the local bus 300 for access to the general-purpose bus 400. If so, the process returns to step S2. If not, the process proceeds to step S6.

In step S6, the address storage / comparison circuit 12b for which the write address coincidence signal has become active
Is selected by the address selector 12c. Then, the selected latched read address is provided to the address / data multiplexer 14. Further, the address cache controller 11 controls the bus controller 13 to start a burst read from the address given to the address / data multiplexer 14 and to read the read FIFO.
Data is taken into O17. Also, read FIFO
17 stores information indicating that valid data read from the latched read address is held and information indicating which address storage / comparison circuit 12b has used the latched read address. The data write operation itself is performed via the write FIFO 16 as in the conventional case.

As described above, the CPU 2 is connected to the general-purpose bus 4
When a data write operation from a target connected to 00 is started, data from a read address in a data read operation performed in association with a past data write operation is captured and held in the read FIFO 17. Further, the read address is held as a latched read address.

When the read operation is determined in step S1, the address cache controller 11 activates the read address match signal from the address storage / comparison circuit 12b that outputs the latched read address used for the data read. And lead FIF
It is determined whether the data in O17 is valid (step S
11). Here, the read address comparison circuit 124 in the address storage / comparison circuit 12b compares the latched read address from the read address latch 122 with the read address on the local bus 300. The read address match signal is active and the read FI
If the data in the FO 17 is valid, the data required by the CPU 2 has already been taken into the read FIFO 17. On the other hand, when the read address match signal is inactive or the data in the read FIFO 17 is invalid, the data required by the CPU 2 does not exist in the read FIFO 17.

If the data required by the CPU 2 has already been taken into the read FIFO 17, the process of step S12 is performed. In step S12, the address cache controller 11 outputs a local bus control signal, and
Transfer data to Then, the process returns to step S1.

If valid data has not been taken into the read FIFO 17, the process of step S13 is performed. In step S13, a process similar to the normal read operation is performed. That is, the address cache controller 11 outputs a local bus control signal and
After the data is loaded into the read FIFO 17 or in parallel with the loading, the data is transferred to the CPU 2.

Subsequently, in step S14, the address cache controller 11 outputs a write address latch signal and a read address latch signal to the address storage / comparison circuit 12b whose address has not been latched yet. Write address latch 1 which received signal
21 and the read address latch 122 latch the latched address and the local bus address (read address from the CPU 2) from the address latch 12a, respectively. When there is no address storage / comparison circuit 12b whose address is not latched, an address latch signal is output to the address storage / comparison circuit 12b that has latched the address at the oldest time in the past. Then, the process returns to step S1. By the process of step S14, the write address in the current data write process and the read address in the data read process following the data write process are stored.

As described above, when the bus bridge circuit 1 according to the present invention performs a write operation on a target connected to the general-purpose bus 400, the bus bridge circuit 1 performs a read operation performed along with a past write operation on the same address. Read data from the read address used for
It is set in the IFO 17. If the data that the CPU 2 wants to read this time has already been set in the read FIFO 17, the data is transferred from the read FIFO 17 to the local bus 300 as it is. In other words, the bus bridge circuit 1 according to the present invention memorizes and learns the operation of the local bus, predicts the read data in advance, and pre-reads the data, thereby improving the data reading efficiency of the CPU 2 from the general-purpose bus 400. In particular, when a target such as a video controller having a video memory having a large correlation between a data write and a subsequent data read is targeted, such a prediction process is highly effective.

In this embodiment, the read address is predicted in the write operation immediately before the read operation. However, the present invention is not limited to the write operation, but may be configured to monitor another specific local bus cycle and predict the next read cycle based on the result.

[0027]

As described above, according to the present invention, before a read cycle for an extension device connected to a general-purpose bus is started, a bus bridge circuit is extended by predicting a read address in the read cycle. The configuration is provided with a predictive reading unit that reads data from the device and causes the read data holding unit to hold the data, so that the number of times the CPU waits when reading data from an extended device such as a video controller on a general-purpose bus is reduced. This has the effect of improving system efficiency. In the case where the predictive read means is configured to include a plurality of address storage means for storing the read address output to the local bus and the write address generated immediately before the read cycle in which the read address was output, This has the effect that the read address can be predicted based on the write operation immediately before the read operation. A first comparing unit that outputs a write address match signal when the write address output to the local bus matches the write address stored in the address storage unit; and a write address match signal is output. And a general-purpose bus read control means for reading data from the read address stored in the address storage means and holding the data in the read data holding means. There is an effect that high data can be prepared in the read data holding unit in advance. Predictive reading means for outputting a read address match signal when the read address read from the data held in the read data holding means matches the read address output to the local bus; Transfer means for transferring the data held in the read data holding means to the local bus side when the read address match signal is output, when the write operation is performed immediately before the read operation. The prediction of the read address has the effect that the CPU can immediately read the data. And a third comparing means for outputting an address match signal when the read address stored in the address storage means matches the write address output to the local bus; and outputting the address match signal. Then, in the case where a configuration is provided that includes a held data management unit that invalidates data held in the read data holding unit, old data can be prevented from passing to the CPU. When the extension device is a video controller having a video memory, the effect of learning the correlation between the read operation and the write operation immediately before the read operation is increased, and the system efficiency can be further improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a computer device including a bus bridge circuit according to the present invention.

FIG. 2 is a block diagram illustrating a configuration example of a bus bridge circuit.

FIG. 3 is a block diagram showing an internal configuration of an address cache.

FIG. 4 is a block diagram showing an internal configuration of an address storage / comparison circuit.

FIG. 5 is a flowchart showing the operation of the bus bridge circuit.

FIG. 6 is a block diagram showing a schematic configuration of a computer device including a conventional bus bridge circuit.

FIG. 7 is a block diagram illustrating an example of a conventional bus bridge circuit.

[Explanation of symbols]

 Reference Signs List 1 bus bridge circuit 2 CPU 3 video controller 4 various memories / I / Os 11 address cache controller 12 address cache 13 bus controller 15 FIFO controller 16 write FIFO 17 read FIFO 12a address latch 12b address storage / comparison circuit 12c address selector 121 write address Latch 122 Read address latch 123 Write address comparison circuit 124 Read address comparison circuit 300 Local bus 400 General-purpose bus

Claims (6)

[Claims] 1. A bus bridge circuit provided between a local bus of a computer and a general-purpose bus and having read data holding means for holding data from the general-purpose bus, wherein a read cycle for an extension device connected to the general-purpose bus is provided. A bus bridge circuit comprising: a predictive read unit that predicts a read address in the read cycle before the start of the read operation, reads data from the extension device, and causes the read data holding unit to hold the data. 2. The predictive read means includes a plurality of address storage means for respectively storing a read address output to a local bus and a write address generated immediately before a read cycle in which the read address was output. Bus bridge circuit. 3. The predictive reading unit includes: a first comparing unit that outputs a write address match signal when a write address output to a local bus matches a write address stored in an address storage unit; 3. The bus bridge circuit according to claim 2, further comprising: general-purpose bus read control means for reading data from the read address stored in the address storage means when the address match signal is output, and causing the read data holding means to hold the data. 4. The predictive reading means outputs a read address match signal when the read address read from the data held in the read data holding means matches the read address output to the local bus. 4. The bus bridge circuit according to claim 3, further comprising: a comparing unit, and a transfer unit that transfers the data held in the read data holding unit to the local bus when the read address match signal is output. 5. A prediction reading means comprising: third comparison means for outputting an address match signal when a read address stored in an address storage means and a write address output to a local bus match; 5. The bus bridge circuit according to claim 4, further comprising: held data management means for invalidating data held in the read data holding means when a signal is output. 6. The bus bridge circuit according to claim 1, wherein the extension device is a video controller having a video memory.