JPH1114712A - Test pattern generating device of logical circuit and generating method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce consumed memory at generating a test pattern for inputting to the test device of a logical circuit by a computer, and make the generating speed high. SOLUTION: Necessary information is input by means of 101 inputting connection information of a logical circuit and trouble definition information, an initial test pattern is generated by an initial test pattern generating means due to ATG (automatic test pattern generation), the initial test pattern is converted to a compressed code by a compressed code test pattern conversion means 103, and hence consumed memory is reduced. Data construction for executing test pattern mergence process at high speed is generated by a comparison data construction generating means 104, a test pattern is compressed by a test pattern compression means 105, and the compressed test pattern is output by an after compression test pattern outputting means 106.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus and a method for generating a test pattern, and more particularly, to pattern compression in a test pattern generation apparatus for a logic circuit.

[0002]

2. Description of the Related Art In recent years, a test pattern sequence for detecting a group of faults defined for a logic circuit of an LSI has not been input to an LSI tester as it is, thereby reducing the fault detection rate in the test pattern sequence. LS through the process of pattern compression to reduce the total number of test patterns without
The form of input to an I tester is common. This is because the scale of the test pattern has been increased with the recent increase in the scale of the LSI.
This is because the data cannot be input to the testing machine.

When performing this test pattern compression on a computer, if the logic circuit becomes large-scale, the test pattern also becomes large-scale, and the amount of memory required for storing the test pattern also becomes large-scale. When performing this test pattern compression on a computer, there is a method in which the entire test pattern is recorded on a magnetic disk device or the like, expanded on a memory when necessary, and compression processing is performed. Disk access (ms or more), which takes much longer time than memory access time (μs), frequently occurs, and the time required for compression processing tends to be longer. Therefore, the key to shortening the compression processing time is to hold the entire test pattern in the memory.

Conventionally, in order to store a test pattern, which is a set of logic values of input / output terminals of a logic circuit, in a memory, it is common to hold a logic value of one input / output terminal in association with one byte. . However, with the increase in the scale of LSIs, the amount of test patterns to be handled has become enormous. For example, in a full scan circuit or the like, there are tens of thousands of input / output terminals and tens of thousands of test patterns due to the circuit configuration. A gigabyte memory capacity is required. However, there is a limit to the memory capacity that can be built in due to the configuration of the computer, and furthermore, since the memory itself is expensive, it is often impossible to provide a sufficient memory on the computer.

In the conventional merging process for compressing test patterns, in order to determine whether or not the test patterns can be merged, each test pattern is compared with brute force and the test patterns are compared. A method of comparing the logical values of the input / output terminals constituting the pattern one by one with respect to all the terminals, and merging the test patterns into one if the results can be merged. Was taken.
In this method, when the size of the test pattern becomes large, an enormous processing time is required.

Conventionally, when test pattern compression is performed on a computer, how the test pattern is stored in a memory,
Whether the test pattern compression has been performed will be described with reference to the drawings.

FIGS. 8 and 9 are diagrams showing a configuration of a conventional test pattern generation device and a merging process flow for test pattern compression. Here, FIG. 8 is a block diagram showing a configuration of a conventional test pattern generation device, and FIG. 9 is a flowchart showing a merging process flow for test pattern compression. FIG. 10 is an image diagram for holding a test pattern in a memory for compressing a test pattern in a conventional test pattern generation device. FIG. 11 is an image diagram illustrating the merging of test patterns. FIG. 12 is an image diagram showing a comparison method between test patterns for compressing test patterns in a conventional test pattern generation device.

First, FIG. 8 will be described. A conventional general test pattern generation apparatus includes a unit 501 for inputting connection information of a logic circuit and failure definition information, and an initial test pattern for detecting a failure defined from the connection information of the logic circuit and the failure definition information. 502 using an ATG (automatic test pattern generation) method or the like; a test pattern compression means 503 for reducing the number of test patterns and generating a compressed test pattern without reducing the failure detection capability of the initial test pattern; And a post-compression test pattern output unit 504 for outputting a post-test pattern.

In particular, the operation of the test pattern merging process in the test pattern compression means 503 for compressing the initial test pattern is as shown in FIG. Hereinafter, the operation of the merging process will be described. In step 511, the process is started, and in step 512, a list of patterns of the initial test is created. In step 513, it is determined whether there is a test pattern not selected as a comparison reference pattern in the test pattern list. As a result, if there is an unselected test pattern, the unselected test pattern is set as a comparison reference pattern in step 514, and the test pattern is deleted from the test pattern list. Then, in step 515, it is determined whether or not there is a test pattern not selected as a comparison target pattern in the test pattern list. As a result, if there is a test pattern that is not selected, a test pattern that is not selected is set as a comparison target pattern in step 516. Thereafter, in step 517, the comparison reference pattern and the comparison target pattern are compared for all terminals by one terminal. Based on the result of the comparison in step 517, it is determined in step 518 whether the comparison reference pattern and the comparison target pattern can be merged. If the result of determination in step 518 indicates that merging is possible, in step 519 the comparison target pattern is merged with the comparison reference pattern, and the comparison target pattern is deleted from the test pattern list. As a result of the determination in step 515, when there is no comparison target pattern for the comparison reference pattern set in step 514 in the test pattern list, the comparison reference pattern is extracted as a compressed test pattern in step 520. Then, as a result of the determination in step 513, when there is no test pattern that can be set as the comparison reference pattern in the test pattern list, the process ends in step 521.

Here, how the prior art holds a test pattern in a memory on a computer will be described with reference to FIG. FIG. 10 illustrates a logic circuit 609, an input terminal portion 608 of the logic circuit 609, and the input terminal portion 608.
Input terminals 610, 611, 612, 613,
614, 615 and these input terminals 610, 611, 6
A memory 601 holding the logical values of 12, 613, 614, 615 and memory elements 616, 617, 61 having a 1-byte capacity constituting the memory 6014
8, 619, 620, 621 and input terminals 610, 61
1, 612, 613, 614, and 615 are associated lines 602, 603, and 6 indicating which memory element corresponds to
04, 605, 606, and 607. FIG.
As shown in (1), the logical value of each conventional input terminal is held in a memory element having a one-byte capacity corresponding to each other on a one-to-one basis. As a result, the memory capacity used when there are 10,000 test patterns of a logic circuit having 10,000 input terminals is 100 Mbytes.

Next, merging of test patterns will be described. In general, the merge between test patterns is performed when the logical value between the input / output terminals constituting the test pattern is the same, or when the logical value of the terminal of one of the test patterns is an indeterminate value X
When the condition of (don't care) holds between all terminals, merging becomes possible. Here, the logical value of the terminal having the uncertain value X is the logical value of the terminal to be merged. According to FIG. 11, a test pattern 701 and a test pattern 702 have a logical value 706 of each terminal between two patterns,
When 707, 708, and 709 are compared, the logical value relationships among all terminals are in a mergeable relationship. Therefore, the test pattern 701 and the test pattern 702 are merged into a test pattern 703. On the other hand, since the test pattern 704 and the test pattern 705 do not satisfy the merging condition due to the logical value relationship 712, they cannot be merged.

A process for determining whether or not merging as shown in FIG. 11 can be performed will be described with reference to FIG. In FIG. 12, the three test pattern sequences are divided into a comparison reference side (comparison reference patterns 801, 802, 803) and a comparison target side (comparison target patterns 804, 805, 806), and a round robin between these test patterns is performed. In the comparison 807, whether or not merging is possible is determined at the test pattern level. In the example shown in FIG. 12, the number of round robin comparisons for three test pattern sequences is three. Incidentally, the number of round robin comparisons of the 10,000 pattern series is 49,995,000. Further, in one comparison process at the test pattern level, an inter-terminal level comparison 810 for the number of terminals between the test pattern 808 and the test pattern 809 is performed. This is 10,000
The test pattern of a circuit having 0 input / output terminals is 10,0
If there are 00 patterns and they cannot all be merged, it may be that tens of billions of terminal-to-terminal level comparisons are performed.

Next, the operation of the merging process shown in FIG. 9 will be described with reference to FIGS. This merging process includes an outer loop passing through Steps 513, 514, 515, and 520, and Steps 515, 516, 517, and
It is constituted by a double loop of an inner loop passing through 518 and 519. In the inner loop, merging determination as shown in FIG. 11 is performed by an inter-terminal level comparison 810 as shown in FIG. 12, and in the outer loop, a test pattern level brute force comparison 807 in FIG. 12 is performed. Such level comparison between terminals 8
10 and test pattern level brute force comparison 807 are:
This process is repeated until the test patterns cannot be merged.

The details of the inter-terminal level comparison 807 performed in step 517 of FIG. 9 will be described with reference to the example of FIG. In FIG. 13, a comparison reference pattern 902 and a comparison target pattern 901 exist. The inter-terminal level comparison between these patterns is performed from comparison 903 to comparison 910. In this last comparison 910, because it violates the merge condition,
These test patterns 901 and 902 cannot be combined. In order to reach this conclusion, it is necessary to perform the terminal-to-terminal level comparison eight times in the conventional method. Here, if the logical value 912 of the terminal 911 of the test pattern 901 is the logical value 1
If so, the test patterns 901 and 9
02 is determined to be mergeable, and merged in step 519 in FIG. 9 to form a test pattern 913.

Steps 513, 514, 515, FIG.
An example of the test pattern level brute force comparison performed in the outer loop composed of 520 will be described with reference to FIG. In step 512, the test patterns 901, 902, 9
21 is created. After steps 513, 514, and 515, the test pattern list 933 is divided into a comparison reference test pattern 923 and a comparison target test pattern list 926. Then, a test pattern 902 which is a comparison reference test pattern
And a test pattern 901, which is a test pattern to be compared.
Test pattern level comparisons 930 and 931 are performed between 921.

This test pattern level comparison 930, 93
The actual process 1 is the level comparison between terminals shown in FIG. In the first outer loop, the comparison reference pattern 923 cannot be merged with any comparison target pattern. As a result, the test pattern 90 which is the comparison reference pattern 923
2 is the first test pattern constituting the test pattern list 928 after compression. Subsequently, in the second outer loop processing, the remaining comparison target test pattern list 926 is set as a comparison reference test pattern 924 and a comparison target test pattern list 927. Here, the comparison reference test pattern 924 is the test pattern 901, and the comparison target pattern list 927 is the test pattern 92.
It is one. Then, the comparison 93 corresponding to step 517 is performed.
2 is performed. In this case, it is determined in step 518 that merging is possible. As in step 519, the test pattern 921 is merged with the test pattern 901 and is deleted from the comparison target test pattern list. As a result, a post-merge comparison reference test pattern 922 can be obtained. After other test patterns to be compared no longer exist, the merged comparison reference test pattern 922 becomes one of the compressed test pattern lists 929.
In the next outer loop process, the test pattern list itself does not exist, so the process ends, and the process proceeds to the end step 521, where the merging process itself ends.

[0017]

In this conventional logic circuit test pattern generation apparatus, when the scale of a logic circuit to be handled is large, it is not possible to hold all test patterns in a memory when performing test pattern compression. . The reason is that the input / output terminals constituting the test pattern are held in one byte, and a memory capacity of several gigabytes is required to hold tens of thousands of test patterns consisting of tens of thousands of terminals.

Further, in the conventional test pattern merging method,
The larger the circuit, the longer the merge time for test pattern compression. The reason is that, when performing the level comparison between all test patterns, the level comparison between all the terminals is performed one by one, so that the number of comparisons increases in a square order with respect to the circuit size, and the merging time becomes longer. It is.

An object of the present invention is to reduce the memory consumed when generating a test pattern computer for input to a test apparatus for a logic circuit and to increase the generation speed.

[0020]

In order to solve the above-mentioned problems, a logic circuit test pattern generating apparatus according to the present invention comprises a logic circuit connection information and failure definition information input means, and a logic circuit connection information and failure definition information input means. A logic circuit comprising: generating means for generating a test pattern for detecting a fault from the definition information; merging means for merging the test patterns without lowering the fault detection rate; and output means for the merged test pattern Means for converting the generated test pattern into a test pattern represented by a compressed code composed of a logical value description section and a repetition number description section, and holding the test pattern in a main memory on a computer; Applying the above, means for generating a comparison data structure used when merging the test patterns, and using the comparison data structure, And merging means for performing a merging process of Sutopatan, and a.

The method for generating a test pattern for a logic circuit according to the present invention includes the steps of inputting connection information and fault definition information of the logic circuit, and generating a test pattern for detecting a fault from the connection information and fault definition information. Converting the generated test pattern into a test pattern using a compressed code including a logical value description section and a repetition number description section; and generating a comparison data structure used when merging the test pattern from the compressed code. And combining the test patterns using the comparison data structure.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a functional configuration of a test pattern generation device according to the present invention. FIG. 2 is a flowchart of a merging process for test pattern compression using a compressed code and a comparison data structure which characterizes the present invention most. FIG. 3 is an explanatory diagram of a compressed code which is a key of the present invention. FIG. 4 is an image diagram showing an example of storing a test pattern on a memory when the compressed code of the present invention is used. FIG. 5 shows a relationship between a test pattern using a conventional normal code and a test pattern using a compressed code according to the present invention;
FIG. 10 is an image diagram showing a comparison data structure which is another key of the present invention.

Referring to FIG. 1, the configuration of the first embodiment of the test pattern generation device of the present invention will be described. As shown in FIG. 1, the test pattern generation device of the present invention includes a means 101 for inputting connection information of a logic circuit and failure definition information,
Means 102 for generating an initial test pattern for detecting a fault defined from the connection information of the logic circuit and the fault definition information by an ATG (automatic test pattern generation) method or the like;
Means 103 for converting an initial test pattern into a compressed code test pattern, and means 10 for generating a data structure for comparison used in the test pattern merging process using the compressed code
Test pattern compression means 105 for reducing the number of test patterns and generating a compressed test pattern without reducing the failure detection capability of the initial test pattern using the compressed code test pattern and the data structure for comparison; Test pattern output means 106 for outputting a test pattern after compression
It is composed of

Here, referring to FIGS. 3 and 4, means 1 for converting an initial test pattern into a compressed code test pattern
An example of the structure of a compressed code used in step 03 and a test pattern using the compressed code will be described. FIG. 3 shows an example of the structure of the compressed code. In this example, the compression code is 8
The one-byte area 201 composed of bits is divided into a logical value description part and a repetition number description part that describes how many terminals the logical value is repeated between adjacent terminals, and combines them into one byte. The structure is described as follows.

The logical value description unit 202 is a logical value description unit for expressing a logical value of a logical circuit in four values (1, 0, X, Z), and requires a 2-bit area. The repetition number description unit 205 is a repetition number description unit for the logical value description unit 202, and can describe continuous terminals having the logical value indicated by the logical value description unit 202 for up to 6 bits. In other words, the logical value of the logical circuit represented by the quaternary expression is such that, when this compression code is used, the logical value of 64 terminals where the same logical value continues can be expressed by 1 byte. In the conventional method, only the logical value of one terminal can be described by one byte. Therefore, the logical value of 64 terminals in which the same logical value is continuous requires a capacity of 64 bytes. As described above, by using the compression code for the logical value description (holding), the logical values for a plurality of terminals can be expressed by one byte. In general, input / output terminals constituting an initial test pattern generated by an ATG (automatic test pattern generation) method or the like for detecting a fault have no relation to the detection of a fault as the circuit scale handled increases. Since the number of input / output terminals increases, the logical values of those terminals can be set as the uncertain value X. That is, in the initial test pattern, the uncertain value X can exist in a very large number continuously. By using this compressed code, the length of one initial test pattern can be significantly reduced as compared with the conventional method. Become.

In FIG. 3, when the logic value of the logic circuit is an octal expression, a combination of the logic value description unit 203 and the repetition number description unit 206 is used. It becomes a combination of the number description unit 207.

In addition, the compression code is composed of a plurality of bytes, a hybrid such as "01", "1Z", or "0Z" is a logical value description section, and the repetition number description section is a repetition description of a variable bit area. It is also conceivable to adopt a configuration in which the unit is a unit.

FIG. 4 shows an example in which a test pattern is stored in a memory using a compressed code. The input terminal group 218 includes terminals 220, 221, 222, 223, and 2
24, 225. The test pattern indicated by these input terminals is “11XXX0”. When this is indicated by a compressed code, since the consecutive terminals 220 and 221 have the same logical value “1”, they can be represented by one byte and these are stored in the memory element 226 on the memory 211 as indicated by arrows 212 and 213. Can be stored. Similarly, the continuous terminals 222, 223, and 224 are indicated by arrows 214 and 21.
5, 216, can be stored in the memory element 227, and the last terminal 225 can be stored in the memory element 228, as indicated by the arrow 217. As described above, in this example, the test pattern length which conventionally required the capacity of 6 bytes is reduced to the capacity of 3 bytes, and the memory can be saved. As the general input and the circuit size increase, the ratio of the logical value occupied by the uncertain value X in one test pattern becomes very high (9
0% or more), the reduction rate of the memory usage by using the compression code increases.

Next, means 1 for generating a data structure for comparison
The data structure for comparison shown in FIG. First, the merging conditions indicating whether two test patterns can be merged are summarized as follows.

[Two test patterns are respectively TP
a , TPb, and an index indicating a terminal constituting the test pattern is i, the test pattern TPa The logical value of the i-th terminal of the test pattern TPb is LV (TPa (i)), and the logical value of the i-th terminal of the test pattern TPb is LV (TPa (i)).
b (i)). At this time, 1. LV (TPa (i)) and LV (TPb (i)) are equal.

2. LV (TPa (i)) is an uncertain value X
It is.

3. LV (TP _b (i)) is the uncertain value X. If any one of the conditions is satisfied between the terminals, the test patterns TPa and TPb can be merged. In other words, if all of the above conditions are not satisfied at any terminal, merging is impossible. Therefore, when the merging condition of whether or not merging is possible is changed to the condition of whether or not merging is possible, the following condition is obtained. LV (TPa (i)) and LV (TPb (i)) are not uncertain values X.

2. LV (TPa (i)) and LV (TP
b (i)) are not equal. Are satisfied, the test patterns TPa and TPa
Pb cannot be merged. ]. In other words, "To determine whether merging is possible, the test pattern TPa
Of the terminals having a logical value that is not an uncertain value, and another test pattern TPb corresponding to the terminal.
Only the combination with the terminal described above need be compared. ] * 1

The test patterns to be compared are divided into comparison reference patterns and comparison target patterns. The comparison reference pattern is compared with another test pattern in the test pattern list as a comparison target to determine whether or not merging is possible, and the comparison target patterns are merged as necessary. This is because if the number of merge processing increases, the number of uncertain values X in the comparison reference pattern decreases and the number of confirmed values increases, so it takes time to determine whether or not merging can be performed using a terminal having a confirmed value as a key. Will be applied. To solve this problem, in the present invention, * 1
Is used as a test pattern TPa in.

The data structure for comparison is used to determine at an early stage whether two test patterns cannot be merged based on the above grounds, and is required for every test pattern. In the data structure for comparison, only the terminal having a definite value among the terminals constituting the test pattern is represented by a compressed code, and the minimum index value in the terminal group indicated by the compressed code is represented by the compressed code. This is a data structure having a pair (combination) with. From this comparison data structure, it is possible to identify which terminal has all the definite values of the test pattern. Therefore, in FIG. 5, the combination of the compression code pattern for comparison 304 and the input / output terminal index array 305 is a comparison data structure. The compressed code test pattern 303 of FIG.
Is shown as a logical value. A, B, C, D, E, F
Is a convenient representation of the compressed code. Here, A indicates that the logical value X continues for four terminals,
B is a logical value 1 for two terminals, C is a logical value X for one terminal, D
Indicates that the logical value 1 corresponds to one terminal, E indicates that the logical value 0 corresponds to two terminals, and F indicates that the logical value X corresponds to two terminals. The comparison target pattern 306 only needs to perform the inter-terminal level comparison 308 six times with the comparison reference pattern 307. This can be performed at a speed that is less than half the number of comparisons as compared with the point where the conventional method has performed 15 comparisons, and can achieve high speed. Further, the comparison data structures 304 and 306
Because it is expressed in compressed code, it does not consume more memory than necessary.

Next, the operation of the embodiment of the present invention will be described with reference to FIGS. The logic circuit connection information and the fault definition information are input, an initial test pattern for detecting a fault defined using an ATG (automatic test pattern generation) method or the like is generated, and the process for merging the initial test patterns is started. The operation of the merging process for the initial test pattern which characterizes the present invention most will now be described.

First, the merging process is started from step 111, the initial test pattern is converted into a compressed code test pattern composed of compressed codes, and a compressed configuration test pattern list is created (step 112). Subsequently, a comparison data structure using a compression code is created for all the test patterns for comparing levels between terminals (step 113). Thereafter, it is determined whether or not a compressed code test pattern not selected as a comparison reference pattern exists in the compressed code test pattern list created in step 112 (step 114). At step 114,
If there is a compressed code test pattern that has not been selected as a comparison reference pattern, it is deleted from the compression code test pattern list and set as a comparison reference pattern (step 115). In step 115, the compressed code test pattern set as the comparison reference pattern is returned to the normal code test pattern (step 116). In the steps up to this point, the comparison reference pattern has been set.

Next, it is determined whether or not there is a compressed code test pattern that is not selected as a pattern to be compared from the compressed code test pattern list (step 11).
7). In step 117, if there is a compressed code test pattern that is not selected as a comparison target pattern,
The comparison data structure for the compressed code test pattern is set as a comparison target pattern (step 118).
Subsequently, between the comparison reference pattern set in step 116 and the comparison reference pattern set in step 119,
An inter-terminal level comparison such as the inter-terminal level comparison 308 shown in FIG. 5 is performed (step 119). As a result of the inter-terminal level comparison in step 119, it is determined whether the comparison target pattern can be merged with the comparison reference pattern (step 120). According to step 120, if the comparison target pattern can be merged with the comparison reference pattern, the compressed code test pattern corresponding to the comparison target pattern is deleted from the compression code test pattern list, and the comparison target pattern is merged with the comparison reference pattern ( Step 121). If it is determined in step 120 that the comparison target pattern cannot be merged with the comparison reference pattern, the process returns to step 117. Step 117 causes step 11
If there is no compressed code test pattern that is not selected as a comparison target pattern for comparison with the comparison reference pattern set in step 6, the comparison reference pattern is extracted as one of the post-compression test patterns (step 122). . From step 114, if there is no compressed code test pattern that can be set as a comparison reference pattern in the compressed code test pattern list, the merging process ends (step 12).
3).

Here, the reason why the test pattern described in the compressed code is converted into the test pattern described in the normal code and set as the comparison reference pattern in steps 115 and 116 will be described. The reason is that, during the inter-terminal level comparison, the comparison reference pattern needs to refer to the logical values of the terminals constituting the pattern many times, and this reference is made as easy as possible. At this time, the comparison reference pattern is extracted as a post-compression test pattern immediately after the end of the inter-terminal level comparison, so that the memory usage in the merging unit does not increase.

Next, an example of the first embodiment of the present invention will be described in detail. In the present embodiment, as in the conventional method, the comparison of the test patterns in the merge processing unit has two stages, that is, a test pattern level comparison and an inter-terminal level comparison. FIG. 15 shows an example in which the contents of the test pattern level comparison of the prior art shown in FIG. 14 are applied to the present invention. The normal code test pattern list 933 in the prior art is a compressed code test pattern list 1009.
To the comparison data structure list 1012. Then, the compressed code test pattern 1006 selected as the comparison reference pattern 1015 is developed into the normal code test pattern 1002 in the same manner as the comparison reference pattern 923 of the conventional normal code test pattern. The remaining compressed code test patterns 1007 and 1008 together with the comparison data structures 1005 and 1011 together with the comparison target pattern 1016
Becomes The test pattern level comparison between the comparison reference pattern and the comparison target pattern is performed by using the normal code test pattern 1002.
The test pattern level comparisons 1025 and 1026 are performed while decoding the comparison data structures 1010 and 1011. However, in this comparison, the comparison reference pattern 10
Since there is no comparison target pattern 1016 that can be merged with the reference pattern 15, the comparison reference pattern 1015 is output as it is to the external storage device such as a magnetic disk as the compressed pattern list 1022. After that, the compressed code test pattern 100
7 is selected as the comparison reference pattern 1017. At this time, the compressed code test pattern 1007 is returned to the normal code test pattern 1001. The remaining compressed code test pattern 1008 is set as a comparison target pattern 1018, and a test pattern level comparison is performed with the comparison data structure 1011. As a result, in order to satisfy the merging condition, the compressed code test pattern 1008 constituting the comparison target pattern 1018 is compared with the comparison reference pattern 1017.
Are decoded into a normal code test pattern 1019 and then merged. Then, the comparison reference pattern 1017 becomes the merged comparison reference pattern 1020. Since there is no other pattern to be compared, the comparison reference pattern 10
Reference numeral 20 is output to an external storage device such as a magnetic disk or the like as a normal code test pattern 1023 constituting the compressed pattern list 1024. The above is the operation of the comparison processing of the test pattern level in the embodiment.

Next, an example of level comparison between terminals will be described with reference to FIGS.
This will be described with reference to FIGS. In the conventional method, the test pattern 901 is treated as a comparison target pattern as shown in the example of the inter-terminal level comparison in FIG.
In the present invention, the comparison data structure 1005 in FIG. 15 is used as a comparison target pattern. This comparison data structure 10
05 is a pair (combination) of a compression code d indicating that one logical value 0 is continuous and a terminal index 1 indicating which first terminal has the logical value of the compression code.
, And a pair (combination) of a compression code b indicating that one logical value 1 is continuous and a terminal index 8 indicating which first terminal has the logical value of the compression code. ing. Conventionally, the level comparison between terminals is shown in FIG.
As described above, eight comparisons from terminal comparison 903 to 910 were performed. However, the comparison data structure 10 of FIG.
05, only the terminals that need to be compared are described.
004 only needs to be performed twice, and the number of comparisons can be greatly reduced as compared with the conventional method. Here, the compressed codes (a, b, c, d, e, f) used in FIGS. 15 and 16 are used for convenience, and are expressed as compressed codes having the following meanings, respectively. Only.

A: Code in which logical value X is repeated 5 times b: Code in which logical value 1 is repeated once c: Code in which logical value 0 is repeated twice d: Code in which logical value 0 is repeated once e: Logical A code in which the value X is repeated six times f: A code in which the logical value X is repeated once g: A code in which the logical value X is repeated twice Next, referring to FIG. 6, a second embodiment of the present invention will be described. The configuration will be described. The second embodiment shown in FIG.
The first embodiment shown in FIG. 1 is different from the first embodiment in that the comparison data structure generation means is a comparison data structure generation means with error terminal information, and the test pattern compression means is a test pattern with a preliminary judgment function. They differ in that they are compression means. Generally, in ATG (automatic test pattern generation), a plurality of test patterns generated for a plurality of faults defined in a certain part of a circuit have different input terminal values in a very limited part of the test pattern. In many cases, the mismatch location is biased. Therefore, this pre-determination function is to hold the terminal of the comparison target pattern and its logical value that caused the determination to be unmergeable when performing the inter-terminal level comparison in the data structure for comparison as error terminal information. This means that before performing the inter-terminal level comparison of the information with a different comparison reference pattern for the second time or later, it is determined in advance whether the comparison target pattern cannot be merged with the comparison reference pattern. By performing this preliminary judgment, the number of times of comparing the levels between terminals between patterns that cannot be merged is greatly reduced, and the processing speed is improved.

Next, the operation of the second embodiment of the present invention will be described with reference to FIG. The operation of the second embodiment shown in FIG. 7 is different from the operation of the first embodiment shown in FIG.
The point that step 413 is changed so that an error terminal information area is also created when the comparison data structure is created, the terminal that does not satisfy the merging condition after step 421 for determining the result of the inter-terminal level comparison, and its logic A step 423 of adding a value to the comparison data structure as an error terminal is added, and a step 42 of performing an inter-terminal level comparison based on the error terminal information generated in the step 423
Before 0, step 419 is added to determine whether an error terminal is set for the comparison target pattern and whether the logical value of the error terminal cannot be merged with the logical value of the corresponding terminal of the comparison reference pattern. Are different.

In the case of the first embodiment, when there is a test pattern that cannot be merged with any of the test patterns, the terminal-to-terminal level comparison between the comparison reference patterns is performed despite the fact that the test patterns cannot be merged. However, this is completely useless processing. In some cases, the number of terminals that are determined to be unmergeable are limited. This limited unmergeable terminal is extracted as an error terminal (step 423), and before comparing the test pattern with the inter-terminal level, only the error terminal is compared and the test pattern is compared with the comparison reference pattern. It is determined at an early stage whether or not merging is impossible between the terminals, so that the level comparison between the terminals does not have to be performed (step 419).

Next, an embodiment will be described. In FIG. 16, it is assumed that the logical value 1 of the terminal 1028 of the test pattern 1001 is the logical value 0 indicated by the logical value 1029.
At this time, the test patterns 1002, 1001, and 1013 cannot be combined. Test pattern level comparison 10
As a result of the inter-terminal level comparison of 26, the error terminal of the test pattern 1013, which is the pattern to be compared, becomes the terminal 1030 and is stored together with its logical value 1031 as error terminal information in the error terminal information area of the comparison data structure. Before performing the inter-terminal level comparison of the next test pattern level comparison 1027, if merging is determined based on the error terminal information (step 419), the test pattern 1013 is immediately executed.
Is determined to be incapable of being merged with the test pattern 1001 selected as the comparison reference pattern 1017, and there is no need to perform an inter-terminal level comparison.

Next, a modified example of the embodiment will be described. As described above, by using the error terminal information to determine the merging condition, the number of times of comparing the levels between terminals can be greatly reduced.
This error terminal information is used to find a pattern that cannot be merged at an early stage. In this embodiment, in addition to storing the information of one error terminal described in the above embodiment, a data structure for comparison is used. In some cases, information for arranging the terminal information in the table in the order of the error occurrence frequency of the key terminal determined to be unmergeable may be stored. In this way, the inter-terminal level comparison can be made at an early stage to determine whether or not merging is impossible by comparing from the terminal where an error is likely to occur. In the case of such an error terminal information form, in FIG. 16, the comparison data structure 1011 is a terminal-to-terminal level comparison 1026 at the first test pattern level 1032, where the terminal 1030 becomes an error terminal and the comparison reference pattern 1015
Cannot be merged with the test pattern 1002 constituting As a result, in step 420, the comparison data structure 101
The terminal arrangement information such that 1 becomes the comparison data structure 1034 is stored in the error terminal information area. Then, in the inter-terminal level comparison 1027 in the second test pattern level comparison 1033, the comparison data structure 1034 and
The test pattern 1001 whose terminal 1028 is set as the logical value 1029 is compared. In this comparison, the error terminal 1030 is compared first, and it can be determined that merging is not possible during the first terminal level comparison. Then, when adopting such a form of the error terminal information, step 419 becomes a form merged with step 420.

As described above, in the second embodiment, the number of comparisons can be reduced more than in the first embodiment, so that the merging processing time can be reduced.

[0048]

The first effect of the present invention is that the amount of memory used on the computer required for the merge processing of test patterns when generating test patterns can be reduced. The reason is that the test pattern is expressed using a compression code, held on a computer, and then merged.

For example, when a test pattern sequence of 50,000 patterns is generated for a circuit having 20,000 input / output terminals by a full scan circuit, in order to hold a collector in a memory on a computer by a conventional technique, 1GB of memory was required, but by using the present invention,
If the number of uncertain values X in one pattern is 90%, a memory amount of about 100 MB is required at worst.

The second effect of the present invention is that the processing speed of test pattern merging can be improved. The reason is that when performing test pattern merging processing, the number of level comparisons between terminals for merging processing can be reduced by using a comparison data structure that applies compressed code, This is because the information is stored as error terminal information, and from this information, the efficiency of determination of whether or not merging is possible in the next and subsequent times can be increased, and the number of comparisons of test patterns for judging merging can be reduced.

For example, when a full scan circuit generates a test pattern sequence of 50,000 patterns for a circuit having 20,000 input / output terminals, assuming that all these patterns cannot be merged, the conventional method The total number of comparisons between the terminals at which the merging process is performed is tens of billions or more, but in the present invention, the judgment between patterns that cannot be merged is performed with the number of comparisons of several or less, so that the The total number of comparisons can be reduced to millions.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a test pattern generation device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing the operation of the test pattern generation device of the present invention.

FIG. 3 is a diagram showing an example of the structure of a compressed code according to the present invention.

FIG. 4 is a diagram showing an example of using a compressed code in the present invention.

FIG. 5 is a diagram showing an example of a compressed code pattern and a comparison data structure according to the present invention.

FIG. 6 is a diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 7 is a diagram illustrating an operation of the second exemplary embodiment of the present invention.

FIG. 8 is a diagram showing a configuration of a conventional general test pattern generation device.

FIG. 9 is a diagram showing an operation of a conventional general test pattern generation device.

FIG. 10 is a diagram showing an example of conventional test pattern holding.

FIG. 11 is a diagram for explaining general test pattern merging.

FIG. 12 is a diagram illustrating a comparison method at the time of a conventional test pattern merging process.

FIG. 13 is a diagram for explaining an example of a conventional inter-terminal level comparison.

FIG. 14 is a diagram for explaining an example of a conventional test pattern level comparison.

FIG. 15 is a diagram for explaining an example of level comparison between terminals according to the embodiment of the present invention.

FIG. 16 is a diagram for explaining an example of test pattern level comparison in the example of the present invention.

[Explanation of symbols]

101-106 Functional means 111-123 Processing step 201 1-byte memory element 202-204 Logical value description section 205-206 Repetition number description section 211 Image of memory 212-217 Arrow indicating correspondence 218 Input terminal 219 Image of logic circuit 220 ２５225 Logical value of each input terminal 226〜228 Memory element for storing compressed code 301 Input / output terminal index 302 Test pattern based on normal code 303 Test pattern based on compressed code 304 Compressed code section 305 constituting data structure for comparison 305 Comparison data structure The input / output index unit 306 that constitutes the comparison data structure 307 as a comparison target pattern 307 Comparison reference patterns 401 to 406 that are normal codes Functional means 411 to 425 of the second embodiment Second Embodiment State processing steps 501-504 Conventional function means 511-521 Conventional processing steps 601 Image of memory 602-607 Arrow indicating correspondence 608 Input terminal 609 Image of logic circuit 610-615 Logic value of each input terminal 616-621 Normal Memory element for storing code 701-705 Test pattern 706-711, 713 Mergeable terminal 712 Non-mergeable terminal 801-806 Test pattern 807 Test pattern level comparison 808,809 Test pattern 810 Terminal level comparison 901 902 921 Normal code test pattern 903 to 910 Conventional inter-terminal level comparison 911 One terminal constituting test pattern 912 Assumed logical value 913 Test pattern when merging is possible with assumed logical value 922 Test pattern after merging 923-925 Comparison reference pattern 926,927 Comparison target pattern 928,929 Pattern list after compression 930-932 Test pattern level comparison 933 First test pattern level comparison 934 Second test pattern level comparison 1001,1002,1013 Normal code test pattern 1003, 1004 Inter-terminal level comparison of the present invention 1005, 1010, 1011 Comparison data structure 1006 to 1008 Compression code test pattern 1009 Compression code test pattern list 1012 Comparison data structure list 1014 Normal code test corresponding to compression code test pattern list Pattern list 1015, 1017 Comparative reference pattern 1016, 1018 Comparative target pattern 1019 Merged normal code test pattern 1020 Merged comparative reference pattern 021, 1023 Pattern after compression 1022, 1024 Pattern list after compression 1028 Assumed terminal 1029 Assumed terminal value 1030 Assumed error terminal 1031 Assumed error terminal value 1032 First test pattern level comparison 1033 Second test pattern level comparison 1034 Example of a data structure for comparison in which the arrangement of terminals is changed so that error terminals are compared first.

Claims (5)

[Claims] An input unit for inputting connection information and fault definition information of a logic circuit; a generating unit for generating a test pattern for detecting a fault from the connection information and the fault definition information; In a test pattern generation device for a logic circuit, comprising: a merging unit for merging without causing the test pattern to be merged; and a unit for outputting the merged test pattern, a compressed code comprising a logical value description unit and a repetition number description unit for the generated test pattern. Means for converting into a test pattern represented by: and holding it on a main memory on a computer; means for applying the compression code to generate a comparison data structure used when merging the test patterns; Merging means for merging test patterns using the data structure for comparison. Generator. 2. A means for inputting connection information of a logic circuit and fault definition information; means for generating an initial test pattern for detecting a fault defined from the connection information of the logic circuit and the fault definition information; Means for converting the initial test pattern into a compressed code test pattern; means for using the compressed code to generate a data structure for comparison used in the test pattern merging process; Test pattern compression means for reducing the number of test patterns without degrading the failure detection capability of the initial test pattern and generating a compressed test pattern; and outputting a post-compression test pattern for outputting the compressed test pattern. Means for generating a test pattern for a logic circuit. 3. The comparison data structure according to claim 1, wherein only the terminal having a definite value among the terminals constituting the initial test pattern is represented by a compression code, and a minimum of a terminal group indicated by the compression code is provided. 3. A data structure having an index value of (1) as a pair with the compression code.
An apparatus for generating a test pattern for a logic circuit according to the present invention. 4. A means for inputting connection information and fault definition information of a logic circuit; a means for generating an initial test pattern for detecting a fault defined from the connection information of the logic circuit and the fault definition information; A means for converting an initial test pattern into a compressed code test pattern, and for generating a comparison data structure to be used in the test pattern merging process using the compressed code, and for creating a comparison with an error terminal information area for error terminal information. A data structure generation unit, and reducing the number of test patterns without deteriorating the failure detection capability of the initial test pattern, while performing advance judgment using the compressed code test pattern and the comparison data structure with error terminal information. Test pattern compression means for generating a post-compression test pattern, and after compression for outputting the post-compression test pattern Test pattern generating apparatus of the logic circuit, characterized in that it comprises a Sutopatan output means. 5. A step of inputting connection information and fault definition information of a logic circuit; a step of generating a test pattern for detecting a fault from the connection information and the fault definition information; and describing the generated test pattern as a logical value Converting the test pattern into a test pattern based on a compressed code including a unit and a repetition number description unit; generating a comparison data structure used when merging the test pattern from the compressed code; Merging using a data structure. A method for generating a test pattern for a logic circuit, comprising: