JPH11146417A - Motion detection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a picture failure by detecting a still picture by a current frame and a video signal delayed for two frames, forcing a motion detection signal to be 0 at the time of the static picture, and making a 1 frame difference motion detection signal a motion signal at the time of a dynamic picture. SOLUTION: A difference between a video signal 2 and a 2 frame delay video signal is taken by a subtracter 9 and a difference signal 10 is inputted to an absolute value circuit 11. A difference absolute value signal 12 to which an absolute value processing is applied at the absolute value circuit 11 is compared with a set value 13 by a comparator 14 and '1' is outputted when it is bigger than the set value 13 and '0' is outputted when smaller. A comparison signal 15 is inputted to the third memory 16 and a terminal (b) of a motion signal synthesis circuit 18, delayed for one frame and inputted to a terminal (c) of the motion signal synthesis circuit 18. In the motion signal synthesis circuit 18, an arithmetic processing is performed that an output signal is forced to be 0 when input signals of the terminals (b) and (c) are both '0' and outputs an input signal of a terminal (a) otherwise, and it is outputted as a motion signal 19 from a terminal 20.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a motion detecting circuit, and more particularly to a motion detecting circuit for synthesizing a motion signal detected by two-frame difference, a two-frame differential motion signal delayed by one frame, and a motion signal detected by one frame differential. And a motion detection circuit for detecting motion.

[0002]

2. Description of the Related Art Generally, when a composite video signal is displayed on a color monitor, it is necessary to separate a frequency-interleaved luminance signal and a chrominance signal. In the NTSC standard television system, the phase of the chrominance subcarrier is inverted between frames. Focusing on this, in a static region of an image (hereinafter referred to as a still image), a luminance signal can be obtained by taking the sum between frames, and a chrominance signal can be obtained by taking the difference. In a moving region of an image (hereinafter referred to as a moving image), when a sum and a difference between frames are applied, a luminance signal and a chrominance signal leak into each other to cause an adverse effect such as dot interference. The luminance signal and the chrominance signal are obtained by using this. The method of separating the luminance (Y) / color (C) signal according to the motion of the image in this manner is called motion adaptive YC separation. In the motion adaptive YC separation, a moving image and a still image are used. The motion detection circuit that determines whether to switch between the two functions plays an important role. If this motion detection cannot be performed accurately and a moving image cannot be processed as a moving image and a still image cannot be processed as a still image, ideal YC separation cannot be performed, resulting in adverse effects such as cross color and dot interference on the image.

Hereinafter, a configuration of a conventional motion detection circuit will be described with reference to the drawings.

First, the configuration of a conventional two-frame differential motion detection circuit will be described with reference to FIG. FIG. 5 corresponds to FIG. 1 of Japanese Patent No. 2558087.

[0005] As shown in FIG. 5, a digital video signal 2 input from a terminal 1 is input to a two-frame memory 41 and a subtractor 9. The video signal 2 input to the two-frame memory 41 is delayed by two frames and input to the subtractor 9. The subtracter 9 calculates a difference between the video signal 2 and the video signal 8 delayed by two frames, and outputs the output difference signal 10 to the absolute value circuit 11. Absolute value circuit 11
Is input to the comparator 14 and compared with the set value 13. The comparison signal 15 is input to the frame memory 16 and the OR circuit 42. The comparison signal 15 input to the frame memory 16 is delayed by one frame and input to the OR circuit 42. OR circuit 4
In the step 2, the larger one of the input comparison signal 15 and the comparison signal 17 delayed by one frame is selected, and is output from the terminal 20 as the motion signal 43. When this output signal is "1", it is determined as a moving image, and when it is "0", it is determined as a still image. The reason for using the difference signal between two frames in this detection circuit is that, when the difference between one frame is used, the color signal is output as a difference in the case of a still image due to the above-described frame inversion of the color subcarrier.

In such a conventional two-frame differential motion detection circuit, as shown in FIG. 6, a certain object moves on a frame by frame as shown in FIGS. From the left to the right), the area determined as a moving image in the output signal 15 of the comparator 14 is the current frame:
The frame before the nth frame ((d) in the same figure) and two frames before:
The area is detected by the difference from the n-2 frame (FIG. 13B), which is the hatched area A in FIG. On the other hand, since the delay signal 17 output from the frame memory 16 is a motion signal of one frame before, it is detected from the difference between the n-1 frame (FIG. 10C) and the n-3 frame (FIG. 10A). Signal. Therefore, the delay signal 17 is shown in FIG.
Is determined to be a motion. In the OR circuit 42, the logical addition of the hatched portion A and the hatched portion B is performed, and all the hatched portions in FIG. This is a moving portion between frames, and is a region indicated by a hatched portion C in FIG. An area D surrounded by a broken line in FIG. 9F is an area to be determined to be stationary.

Next, the configuration of a conventional one-frame differential motion detection circuit will be described with reference to FIG.

As shown in FIG. 7, a digital video signal 2 input from a terminal 1 is input to a frame memory 3 and a comb filter 201 between lines. The input video signal 2 is converted into a luminance signal 1 by the interline comb filter 201.
07 and a color signal 108. On the other hand, the video signal 2 input to the frame memory 3 is delayed by one frame, input to the interline comb filter 202, and separated into the luminance signal 109 and the chrominance signal 110 delayed by one frame. Since the phase of the color signal 110 delayed by one frame is inverted as described above, the color signal 110 is input to the inverting circuit 111 to align the phases. Line-to-line comb filter 20
Luminance signals 107 and 10 separated by YC by reference numerals 202 and 202
9, the color signal 108, and the inverted color signal 112 obtained by inverting the color signal 110 delayed by one frame are input to subtracters 113 and 114, respectively. And difference color signal 116
Is output. The difference luminance signal 115 is output to the absolute value circuit 117.
, And the absolute value is taken and input to the comparison circuit 121. The comparison circuit 121 compares the luminance value with the set value 122 and outputs a luminance motion signal 125. Similarly, the absolute value circuit 118 calculates the absolute value of the difference color signal 116, compares the absolute value with the set value 124 by the comparison circuit 123, and obtains the color motion signal 126.
Is obtained. The luminance motion signal 125 and the color motion signal 126 are input to an OR circuit 127, which performs an OR operation on the OR circuit 127, and outputs a motion signal 128 from the terminal 20.

In such a conventional one-frame differential motion detection circuit, when a colored diagonal pattern is input as a still image as shown in FIG. 8A, the circuit shown in FIG. As described above, the signal level of the x-th pixel on the n-th line is set to (Yn + C
n) and the signal level of the x-th pixel in the (n-1) -th line is (Yn-1-Cn-1), (the color signal is 1
Paying attention to these two pixels because the phase is inverted for each line), the output of the adder 103 is (Yn + Cn) + (Yn-1-Cn-1), and the luminance signal 107 is (Yn + Yn-1) + (Cn-Cn-
1).

The output of the subtractor 104 is (Yn + Cn)
− (Yn−1−Cn−1), and the color signal 108 becomes (Yn−1−Cn−1).
n + Yn-1) + (Cn-Cn-1). On the other hand, the video signal 4 delayed by one frame by the frame memory 3
Since the phase of the color signal is inverted for each frame, the signal level of the x-th pixel of the n-th line of interest is (Yn-Cn), and the signal level of the x-th pixel of the n-1-th line is (Yn-1 + Cn-1).

Therefore, the output of the adder 105 is (Yn-C
n) + (Yn-1 + Cn-1), and the delayed luminance signal 1
09 is (Yn + Yn-1) + (-Cn + Cn-1). The output of the subtractor 106 is (Yn-Cn)-(Yn
−1 + Cn−1), and the delayed color signal 110 is (Yn−
Yn-1)-(Cn + Cn-1), but the inversion circuit 11
1 and − (Yn−Yn−1) + (Cn +
Cn-1).

The luminance signal 107 and the delayed luminance signal 109 are subtracted by a subtractor 113 into a Δluminance signal 107: (Yn + Y).
n-1) + (Cn-Cn-1)｝-｛delayed luminance signal 10
9: Yn + Yn-1) + (-Cn + Cn-1)}, and the difference luminance signal 115 becomes 2 (Cn-Cn-1). The same applies to the color signal 108:
(Yn-Yn-1) + (Cn + Cn-1)｝-｛delayed color signal 112:-(Yn-Yn-1) + (Cn + Cn-
1) The calculation of｝ is performed, and the differential color signal 116 is 2 (Yn−Y).
n-1).

The output of the subtractor is subjected to absolute value processing, compared with a set value by a comparator, combined by an OR circuit, and becomes a motion signal. In the above case, 2 (Cn− Cn-1) and 2 (Yn-
Yn-1) is determined to be a motion signal, and erroneous detection occurs.

[0014]

As described above, in the conventional example, in the case of two-frame differential motion detection, unnecessary motion occurs in a region surrounded by a broken line in FIG. 6 (f). In the case of one-frame differential motion detection, a color signal leaked into a luminance signal or a luminance signal leaked into a color signal is determined to be motion, and unnecessary motion occurs even though it is a still image. . Due to these unnecessary motion signals, ideal YC separation is not performed in the motion adaptive YC separation, and adverse effects such as cross color and dot disturbance occur.

An object of the present invention is to provide a motion detection circuit which does not generate unnecessary motion even when a signal such as a certain object moves at a high speed or an oblique line pattern is input.

[0016]

In order to achieve the above object, a motion detecting circuit according to the present invention comprises a first frame memory, a second frame memory, a one-frame differential motion detecting circuit, and a second frame memory. A differential motion detection circuit,
A motion detection circuit having a third frame memory and a motion signal synthesis circuit, wherein the first frame memory delays the input digital video signal by one frame and converts the one-frame delay signal into a second frame memory; A second frame memory for delaying the one-frame delayed video signal by one frame, and outputting a two-frame delayed signal to the two-frame differential motion detection circuit; The one-frame differential motion detection circuit detects a one-frame differential motion signal from an input digital video signal and a one-frame delayed video signal and outputs the motion signal to a motion signal synthesizing circuit. A motion signal is detected from the video signal and the two-frame delayed video signal, and the comparison signal is stored in the third frame memory and the motion signal synthesis circuit. The third frame memory delays the output signal of the two-frame differential motion detection circuit by one frame and outputs the signal delayed by one frame to the motion signal synthesis circuit. Are the output signals of the one-frame differential motion detection circuit and 2
The operation is performed by using the output signal of the frame difference motion detection circuit and the output signal of the third frame memory as inputs, and a motion signal is output.

Also, there are two types of motion signal synthesizing circuits, two types of third frame memories, and a motion MIX circuit.
The one-frame differential motion detection circuit separately outputs a luminance signal one-frame differential motion signal and a chrominance one-frame differential motion signal, and the two-frame differential motion detection circuit outputs a luminance-side comparison signal and a color-side comparison signal. Are output separately, and two types of third
The frame memory separately stores the luminance-side comparison signal and the chrominance-side comparison signal output from the two-frame differential motion detection circuit.
The two types of motion signal synthesizing circuits receive the output of the motion detecting circuit for one frame, the output of the motion detecting circuit for two frames and the output of the third frame memory, and separate the luminance signal and the chrominance signal separately. And the luminance-side motion signal and the color-side motion signal output to the other side
The motion MIX circuit mixes the two input signals and outputs a motion signal.

When both the output signal of the two-frame differential motion detection circuit and the output signal of the two-frame differential motion detection circuit delayed by one frame indicate "0", the motion is forcibly set to zero. In this case, the output signal of the one-frame difference motion detection circuit is used as a motion signal.

[0019]

(Embodiment 1) Hereinafter, Embodiment 1 of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a main configuration of a motion detection circuit according to an embodiment of the present invention. The same components as in the conventional example will be described with the same reference numerals.

In FIG. 1, a digital video signal 2 input from a terminal 1 is input to a one-frame differential motion detection circuit 6 and a first frame memory 3. The one-frame delayed video signal 4 delayed by one frame in the first frame memory 3 is input to the second frame memory 5 and the one-frame differential motion detection circuit 6, respectively. The second frame memory 5 is further delayed by one frame and outputs a two-frame delayed video signal 8. On the other hand, the video signal 2 and the one-frame delayed video signal 4 inputted to the one-frame differential motion detection circuit 6
01 and 202, the difference is calculated by subtractors 113 and 114, respectively, and compared with set values 122 and 124 by comparators 121 and 123, and OR circuit 127
, The luminance motion signal 125 and the color motion signal 126 are combined, and the one-frame differential motion signal 7 is output. The one-frame difference motion signal 7 is input to a terminal a of the motion signal synthesis circuit 18.

The difference between the video signal 2 and the two-frame delayed video signal is obtained by a subtractor 9 as in the conventional example, and the difference signal 10 is input to an absolute value circuit 11. The difference absolute value signal 12 subjected to the absolute value processing by the absolute value circuit 11 is input to a comparator 14, compared with a set value 13 by the comparator 14, and outputs “1” when the set value is larger than the set value 13. When it is smaller than 13, "0" is output. The comparison signal 15 is input to the third frame memory 16 and the terminal b of the motion signal synthesis circuit 18. The comparison signal 15 input to the frame memory 16 is delayed by one frame and input to the terminal c of the motion signal synthesis circuit 18. In the motion signal synthesis circuit 18, FIG.
As shown in (2), when both the input signals of the terminals b and c are "0", the output signal is forcibly set to 0, otherwise, the input signal of the terminal a is output, and the operation is performed. The signal is output from a terminal 20 as a signal 19.

By adopting such a configuration, FIG.
(A) to (c) in FIG.
If the motion shown in FIG. 6D is performed (the same motion as in FIG. 6) and the background includes a diagonal pattern, the output signal 15 of the comparator 14 and the output from the third frame memory 16 are output. The regions determined to be moving images based on the delayed signal 17 are, as in the conventional example, as shown in FIG. On the other hand, the detection signal 7 based on the one-frame difference in the current frame is determined to be a motion in the shaded area in FIG. In the motion signal synthesizing circuit 18, arithmetic processing is performed based on the detection results as shown in FIGS. 7E to 7G, and in the hatched area in FIG.
Is output, and in other areas, a one-frame difference motion detection signal as shown in FIG. 9G is output as the motion signal 19 in FIG. Accordingly, the area determined to be a moving image based on the motion signal 19 is as shown in FIG. 9I, and the erroneous moving image determination of the still image area which occurs in the related art can be improved. In addition, since there is no motion at the time of a still image, it is possible to improve the adverse effect caused by the erroneous detection that has occurred in the one-frame differential motion detection.

(Embodiment 2) FIG. 4 is a block diagram showing another embodiment of the present invention. In the example of FIG. 4, the outputs of one-frame differential motion detection are separately output on the Y and C sides, and two comparators are used in a two-frame differential detection circuit.
Motion detection is separately performed on the Y and C sides by using two set values on the Y and C sides, and two motion signal synthesis circuits are used to synthesize signals for the respective motions on the Y and C sides. The configuration is different from the previous embodiment in that the Y-side and C-side motion signals separately processed are mixed and output.

In FIG. 4, the input video signal 2 and the one-frame delayed video signal 4 delayed by the first frame memory 3 are input to a one-frame differential motion detecting circuit 6, and inter-line combing is performed as in the conventional example. YC separation is performed by the shape filters 201 and 202, the difference is calculated by subtractors 113 and 114, and set values 122 and 124 are calculated by comparators 121 and 123.
And a luminance signal one-frame differential motion signal 32 and a chrominance signal one-frame differential motion signal 33 are output. Also,
The one-frame delayed video signal 4 is further delayed by one frame by the second frame memory 5. The difference between the two-frame delayed video signal 8 and the video signal 2 is calculated by the subtractor 9 in the same manner as in the prior art, and the absolute value is processed by the absolute value circuit 11 in the comparator 2.
2 and the comparator 24 respectively.

The comparator 22 compares with the Y-side set value 23, and the comparator 24 compares with the C-side set value 25. When the set value is larger than the set value, "1" is set, and when the set value is smaller, "0" is set. Output. The Y-side and C-side comparison signals 26 and 27 are input to separate third frame memories 28 and 30 and terminals b of Y-side and C-side motion signal synthesis circuits 34 and 36, respectively.

The comparison signals 29 and 31 delayed by one frame by the third frame memories 28 and 30 are input to terminals c of the motion signal synthesizing circuits 34 and 36, respectively. The arithmetic operation shown in FIG. 2 is performed by the luminance signal 1-frame differential motion signal 32, the chrominance signal 1-frame differential motion signal 33, and the signals input from the terminals b and c, respectively.
The side motion signals 35 and 37 are output, respectively. The Y-side motion signal 35 and the C-side motion signal 37 are input to a motion MIX circuit 38, mixed, and output as a motion signal 39 from a terminal 20. By using two set values on the Y side and the C side in this way, it is possible to change the detection accuracy of the Y side and the C side motion signals.

[0028]

As is apparent from the above embodiment, according to the present invention, a still image is detected by the video signal of the current frame and the video signal delayed by two frames, and when the detection result is still, the still image is detected. The detection signal is forcibly set to 0, and in the case of a moving image, the one-frame difference motion detection signal is used as a motion signal, which is unnecessary even when a signal such as a certain object moves at a high speed or an oblique line pattern is input. No ideal movement occurs and ideal Y
This has the effect that image separation can be prevented by performing C separation.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a motion detection circuit according to one embodiment of the present invention.

FIG. 2 is a diagram illustrating a calculation result of a motion signal control circuit.

FIG. 3 is a schematic diagram for explaining the operation of the present invention. (A) to (d) Schematic diagrams including an object moving at high speed and a diagonal pattern in the background (e) Two-frame differential motion detection result in current frame (f) n-1 frame (one frame before (G) One frame differential motion detection result in the current frame. (H) Two-frame differential motion detection in the current frame and the (n-1) th frame indicates a region that is not determined to be motion by the two-frame differential motion detection.

FIG. 4 is a block diagram illustrating a configuration of a motion detection circuit according to another embodiment of the present invention.

FIG. 5 is a block diagram of a conventional two-frame differential motion detection circuit.

FIG. 6 is a schematic diagram for explaining the operation of a conventional two-frame differential motion detection circuit. (A)-(d) Schematic diagrams of an object moving at high speed. (E) Motion detection result in the conventional example. (F) Ideal detection result in the current frame.

FIG. 7 is a block diagram of a conventional one-frame differential motion detection circuit.

FIG. 8 is a model diagram for explaining an adverse effect of a conventional one-frame differential motion detection circuit. (A) An example of an oblique line pattern that causes a problem in the one-frame differential motion detection circuit. (B) It is a diagram in which (a) is enlarged for each line.

[Explanation of symbols]

 3, 5, 16, 28, 30 frame memory 6 1-frame differential motion detection circuit 9, 104, 106, 113, 114 subtractor 11, 117, 118 absolute value circuit 14, 22, 24, 121, 123 comparator 18, 34, 36 motion signal synthesizing circuit 38 motion MIX circuit 41 two-frame memory 42, 127 OR circuit 101, 102 line memory 103, 105 adder 111 inverting circuit 201, 202 inter-line comb filter 21, 40 two-frame motion detecting circuit

Claims (3)

[Claims] 1. A first frame memory, a second frame memory, a one-frame differential motion detection circuit, a second frame differential motion detection circuit, a third frame memory, and a motion signal synthesizing circuit. A motion detection circuit, wherein a first frame memory stores an input digital video signal
A frame-delayed one-frame delayed signal is output to a second frame memory and a one-frame differential motion detection circuit. The second frame memory further delays the one-frame delayed video signal by one frame, and The one-frame differential motion detecting circuit detects the one-frame differential motion signal from the input digital video signal and the one-frame delayed video signal, and outputs the one-frame differential motion signal to the motion signal synthesizing circuit. The two-frame differential motion detection circuit detects a motion signal from the input digital video signal and the two-frame delayed video signal, and outputs a comparison signal to the third frame memory and the motion signal synthesis circuit. The third frame memory delays the output signal of the two-frame differential motion detection circuit by one frame and delays the output signal by one frame. The motion signal synthesis circuit outputs the output signal of the one-frame difference motion detection circuit, the output signal of the two-frame difference motion detection circuit,
A motion detection circuit which calculates an output signal of a third frame memory as an input and outputs a motion signal. 2. A motion signal synthesizing circuit comprising two kinds of motion signal synthesizing circuits, two kinds of third frame memories, and a motion MIX circuit. The one-frame differential motion signal is output separately. The two-frame differential motion detection circuit separately outputs a luminance-side comparison signal and a chrominance-side comparison signal. The luminance-side comparison signal and the color-side comparison signal output from the detection circuit are separately output with a delay of one frame, and the two types of motion signal synthesis circuits are a motion detection circuit for one frame and a motion detection circuit for two frames. And the output of the third frame memory are input, and the luminance signal and the chrominance signal, which are separately processed and output to the other side, respectively, are input to the motion MIX circuit. In things Ri, motion MIX circuit, according to claim 1, characterized in that a mix of both signals input and outputs a motion signal
3. The motion detection circuit according to 1. 3. When both the output signal of the two-frame differential motion detection circuit and the output signal of the two-frame differential motion detection circuit delayed by one frame indicate “0”, the motion is forcibly set to 0; 3. The motion detection circuit according to claim 1, wherein in the case of (1), an output signal of the one-frame difference motion detection circuit is used as a motion signal.