JPH11145978A - Multiplexing controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multiplexing controller capable of guaranteeing a transmission cell number per unit time for respective incoming lines and realizing a large latitude for setting and highly accurate priority control for the respective incoming lines. SOLUTION: This multiplexing controller 100 is provided with incoming lines 101-103 (incoming lines 1-3), cell buffer memories 104-106, memory control parts 107-109, a guarantee band setting table part 112 for setting respective guarantee bands to the incoming lines 1-3 and a contention judgement circuit part 111 for deciding the incoming line for permitting transmission corresponding to the set contents of the guarantee band setting table part 112. The guarantee band setting table part 112 is constituted of a setting original table 201 capable of setting an output cell number at each unit time for the respective incoming lines, an operation table 202 for indicating transmission priority orders for the respective incoming lines and performing self-updating at each 1-cell time and a timer 203 and the contention judgement circuit part 111 controls contention based on the operation table 202.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ATM (Asynchro
Nous Transfer Mode: relates to a multiplexing control device for controlling the band allocation of a multiplexing device or a switching device in a communication system, and particularly guarantees a band specified for each input route or each input logical channel in a multiplexing unit. ,
The present invention relates to a multiplexing control device capable of performing priority control according to a specified priority in a band not guaranteed.

[0002]

2. Description of the Related Art As a means for realizing multimedia communication, ATMs are considered to be promising.
ea Network).

[0003] In the ATM communication system, data is transmitted and received by dividing a data string of information into fixed-length data blocks called cells. The ATM communication system is characterized in that a line is efficiently used by multiplexing cell data input from various routes.

Conventionally, this type of device has a certain type of scheduling configuration. For example, there is one disclosed in JP-A-8-51445.

[0005] The apparatus described in the above-mentioned document uses a guaranteed bandwidth fixed for each input logical channel by a guaranteed bandwidth scheduler that schedules transmission of a guaranteed bandwidth virtual channel identified in the scheduler by an identification level set as a virtual channel identifier. A band and several priorities are set, and transmission control is performed according to these settings.

[0006]

However, in such a conventional ATM device, the number of priority classes is fixed unless the priority is set from the outside, and the number of priority classes is limited.
There is a problem that the bandwidth allocation in the non-guaranteed bandwidth cannot be set freely.

An object of the present invention is to provide a multiplexing control device which guarantees the number of cells transmitted per unit time for each incoming line and realizes high-precision control with a high degree of freedom and accuracy for each incoming line. Aim.

[0008]

A multiplexing control device according to the present invention is a multiplexing control device having a plurality of incoming lines, comprising: a first table capable of setting the number of output cells per unit time for each incoming line; And a second table that indicates the transmission priority for each incoming line and that is updated independently on a cell-by-cell basis, and that contention is controlled based on the second table.

The multiplexing control device according to the present invention comprises a plurality of V
In a multiplexing control device to which an input line in which C is multiplexed is connected, a first table in which the number of output cells per unit time can be set for each VC, and a transmission priority order for each VC are shown.
A second table that is updated independently for each cell time,
It is characterized in that competition is controlled based on the second table.

The first table is a table of the number of cells guaranteed for transmission per unit time per input route and the input route, in which the setting information is written in descending order from the route with the highest priority. Further, the first table is a table of the number of cells guaranteed to be transmitted per unit time for each VC and the VC number, and the setting information may be written in descending order from the route with the highest priority. Good.

The above-mentioned second table is a table of input routes corresponding to the number of cells guaranteed to be transmitted, and performs update processing once in every valid cell transmitted so as to be in descending order of priority. The second table is a table of the number of cells guaranteed to be transmitted and the VC number corresponding thereto, and is updated once in every valid cell is transmitted so as to be in descending order of priority. Processing may be performed.

In the updating of the second table, the priority is lowered when a prescribed number of cells are output from the outgoing line for each VC, and the control is returned to the initial priority after a certain period of time. Good.

[0013] The cell may be an ATM cell.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A multiplexing control device according to the present invention comprises:
The present invention can be applied to a broadband large-capacity routing server having a bandwidth control function (VC shaping function) in VC (Virtual Channel) units.

First Embodiment FIG. 1 is a diagram showing an overall configuration of a multiplexing control device according to a first embodiment of the present invention. FIG. 1 shows an example of a configuration in which a plurality of incoming lines are multiplexed. Here, a case where the number of incoming lines is 3 is described as an example.

In FIG. 1, a multiplexing control device 100 comprises:
Signal lines for inputting data (hereinafter referred to as input lines) 101 to 101
103 (input lines 1-3), cell buffer memories 104-1
06, memory control units 107 to 109, a signal line (hereinafter referred to as an outgoing line) 110 for sending output data, a conflict determination circuit unit 111, and a guaranteed bandwidth setting table unit 112.

The cell buffer memory 104 is a memory for storing cells input from the input line 1. This memory is controlled by the memory control unit 107 so as to function as a FIFO (first-in first-out) memory. Similarly, the cell buffer memory 105 is a memory for storing cells input from the input line 2, and the cell buffer memory 106 is a memory for storing cells input from the input line 3. The memory control unit 10 is configured to function as a FIFO.
8, 109.

In this embodiment, in order to perform efficient multiplexing processing without losing or discarding cell data, a FIFO (first-first buffer) is used as a buffer for temporarily storing and sequentially outputting cell data. in first-out). Generally, in a FIFO, data is temporarily stored using a memory or the like in a data latch unit. However, in an ATM communication system, data is frequently written and read, so that a flip-flop or a flip-flop capable of high-speed operation is used. A D-latch or the like is used.

When valid cells are input to the cell buffer memories 104 to 106, the memory control units 107 to 109 transmit a cell transmission request signal to the outgoing line 110 to the conflict determination circuit unit 111.
Send to When one or more valid cells are stored in the memory, the memory control units 107 to 109 transmit a cell transmission request signal to the contention determination circuit unit 111 for one cell time. When all the stored cells are transmitted, the transmission of the cell transmission request signal is stopped.

The guaranteed bandwidth setting table section 112 is a table for setting each guaranteed bandwidth for the incoming line 1, the incoming line 2, and the incoming line 3.

The contention determination circuit unit 111 determines an incoming line for which transmission is permitted according to the setting contents of the guaranteed bandwidth setting table unit 112, and transmits a cell transmission permission signal to the memory control unit of the corresponding incoming line. A configuration example of the conflict determination circuit unit 111 will be described later with reference to FIG.

FIG. 2 is a block diagram showing a connection configuration between the contention determination circuit 111 and the guaranteed bandwidth setting table 112.

In FIG. 2, the guaranteed bandwidth setting table unit 1
Reference numeral 12 denotes a setting source table 201 (first table), an operation table 202 (second table), and a timer 203.
Consists of

As shown in FIG. 3, the setting source table 201 stores the number of guaranteed transmission cells RT per unit time for each input route,
It is a table of the input route RC. When there is an input route RC having the same number of guaranteed transmission cells RT per unit time, a route written to a smaller address in the setting source table 201 has higher priority. That is, the setting source table 201 writes the setting information in descending order from the route with the highest priority.

The timer 203 measures a unit time specified in cell time units, and transmits a pulse to the setting source table 201 for each unit time. Setting source table 20
1 receives the pulse from the timer 203 and transfers the contents of the setting source table 201 to the operation table 202.

As shown in FIG. 4, the operation table 202 is a table of the number of remaining cells ET for transmission guaranteed and the input route EC corresponding to the number of cells ET, and is constituted by registers capable of executing a shift in an arbitrary address section. The operation table 202 performs an updating process once every valid cell is transmitted so that the priority order becomes descending. FIG. 7 shows the process of updating the operation table 202.
Will be described later. In addition, the shift processing and the insertion processing of the update processing of the operation table 202 can be realized by, for example, the circuit illustrated in FIG.

FIG. 5 is a diagram showing a part of the operation table updating circuit, and shows an example of the configuration of the insertion destination address determining circuit of the operation table.

In FIG. 5, the insertion address determining circuit for the operation table includes a mask generation circuit 301 for generating a signal for masking up to the competition winning address, and an exclusive OR (the number of cells 602 between consecutive addresses in the operation table). EX
EXOR gate 302 which takes OR), mask generation circuit 3
It comprises an AND gate 303 for ANDing the mask data from 01 and the output of the EXOR gate 302, a priority decoder 304 for determining the priority of the input data, and an encoder 305 for encoding the priority decoder 304 and outputting an insertion address. .

FIG. 6 is a circuit diagram showing the configuration of the conflict determination circuit unit 111.

In FIG. 6, the conflict determination circuit unit 111
The decoder 401, an AND gate 402 for calculating the logical product of the output of the decoder 401 and the transmission request signal input, an OR gate 403 for calculating the logical sum of the AND gate 402, the priority decoder 404 for determining the priority of the input data, and the priority decoder 404 are encoded. And outputs the insertion address.

Hereinafter, the operation of the multiplexing control device 100 configured as described above will be described.

[Overall Operation] First, FIG. 3 and FIG.
, The number of cells guaranteed for transmission per unit time and the pulse generation cycle of the timer are set in the setting source table 201. After the setting, the pulse generated by the timer 203 changes the setting table 201 to the operation table 20.
2 is transferred to the setting parameter 204 (FIG. 2). Then, table information 205 is output from the operation table 202 to the conflict determination circuit unit 111.

Now, when a valid cell is input from incoming line 1,
The cell is a cell buffer memory 10 functioning as a FIFO.
4 to 106, and the transmission request signal 206 (FIG. 2) is sent from the memory control units 107 to 109 to the conflict determination circuit unit 111.
Sent to. Here, the memory control units 107 to 109
Sends a cell transmission request signal to the 206 contention determination circuit unit 111 for one cell time when one or more valid cells are stored in the memory.

When all the stored cells have been transmitted, transmission of the cell transmission request signal 206 is stopped.

The contention determination circuit unit 111 determines an incoming line for which transmission is permitted according to the setting contents of the guaranteed bandwidth setting table unit 112, and transmits a cell transmission permission signal 207 to the memory control unit of the corresponding incoming line. That is, the conflict determination circuit unit 1
11 refers to the operation table 202 and, if there is no cell transmission request from a route having a higher priority than the incoming line 1, sends a cell transmission permission signal 207 for the incoming line 1 to the memory control units 107 to
Send to 109.

When a cell is transmitted, the operation table 20
Update 2. An execution example of the update processing will be described later with reference to the flow of FIG.

As described above, the specified band is guaranteed for each input path or each input logical channel, and priority control according to the specified priority is executed for the band not guaranteed.

[Operation of Each Unit] Guaranteed Band Setting Table 11
2 includes a setting source table 201, an operation table 202, and a timer 203 as shown in FIG. 2, and each unit has the following functions.

As shown in FIG. 3, the setting source table 201 is a table of the number of cells guaranteed for transmission per unit time and the number of input routes for each input route. If the route exists, the setting source table 20
A route written to an address smaller than 1 has a higher priority. For this reason, the setting information is written into the setting source table 201 in descending order from the route having the higher priority.

The timer 203 measures a unit time specified in cell time units, and transmits a pulse to the setting source table 201 for each unit time.

When the setting source table 201 receives a pulse from the timer 203, the contents of the setting source table 201 are transferred to the operation table 202.

The operation table 202 is, as shown in FIG. 4, a table of input routes corresponding to the number of cells guaranteed to be transmitted, and is constituted by registers capable of executing a shift in an arbitrary address section. In the operation table 202, the update process is performed once every time a valid cell is transmitted so that the priority order becomes descending.

FIG. 7 is a flowchart showing the flow of the operation table updating process, and ST indicates each step of the flow.

First, in step ST1, the conflict determination circuit 1
11 to obtain a conflict determination result. Here, it is assumed that the winning address based on the conflict determination result is a.

Next, in step ST2, the operation table 2
It is determined whether the number of remaining cells at address a of 01 is 0 (the number of remaining cells in the route of the transmitted cell is positive) or whether address a is the last address of the table. If the number of remaining cells at the address a is 0 or the address a is the last address of the table, it is determined that all update processing has been completed, and this flow ends.

If the number of remaining cells at address a is 0 or the address a is not the last address of the table, the number of remaining cells at address a is decremented at step ST3.

Next, in step ST4, it is determined whether or not the number of remaining cells at address a is smaller than the number of remaining cells at address a + 1.

If the number of remaining cells at address a is equal to or greater than the number of remaining cells at address a + 1, it is determined that all update processing has been completed, and this flow is terminated. If smaller, the process proceeds to step ST5.

In step ST5, the smallest address larger than a which satisfies the condition of the remaining cell number (n) ≦ the remaining cell number (a) is stored in the register i. In step ST6, the address a is stored in the register n and the remaining cell number ( a) is a temporary register tempa
Then, the input route (b) is stored in the temporary register tempb.

Next, in step ST7, the remaining cell number (n + 1) obtained by adding one cell to the remaining cell number is set as the remaining cell number (n), and the input route (n + 1) obtained by adding 1 to the input route is input. Route (n). In step ST8, the register n
Is determined to be greater than or equal to the register i. If the register n is equal to or smaller than the register i, the process returns to step ST7 and repeats step ST7 until the register n is greater than the register i.

When the value of the register n becomes larger than the value of the register i, the value of the temporary register tempa is set to the number of remaining cells (i) in step ST9, and the value of the temporary register tempb is set to the input route (i) to end the operation table updating process. I do.

As described above, the operation table updating process decrements the remaining cell number if the number of remaining cells in the route of the transmitted cell is positive, and does not decrement the remaining cell number if it becomes smaller than zero. If the result of the decrement is smaller than the number of remaining cells at the next address, the maximum number of cells equal to the number of cells obtained by adding one cell to the number of remaining cells resulting from the decrement is calculated from the competition winning address a. The shift to the address and the insertion process are performed (steps ST5 to ST9 described above).

FIGS. 8A and 8B are diagrams showing an example of updating the operation table 202. FIG. 8A shows the operation before updating the table, FIG. 8B shows the operation at the time of update processing, and FIG. 8C shows the operation after the update result. Represents a table.

From the operation table of the input route EC corresponding to the transmission guarantee remaining cell number ET shown in FIG.
When one cell of C0 is transmitted, as shown in FIG. 8 (B), (1) first, the number of remaining cells ETA + 1 for guaranteed transmission corresponding to the input route EC0 is decremented to ETa.

(2) By decrementing, the guaranteed transmission remaining cell number ETa becomes smaller than the guaranteed transmission remaining cell number ETa + 1 of the next address 0001, so that the insertion process is performed. The insertion destination address is 0003. The operation table after the update result is shown in FIG.

The above-described shift processing and insertion processing can be realized by, for example, an operation table updating circuit shown in FIG.

That is, in FIG. 5, the competition winning address 306 is input to the mask generation circuit 301, and the mask data 307 is obtained. The mask generation circuit 301 generates a signal for masking from address 0 to the competition winning address.

On the other hand, the number of cells between consecutive addresses in the operation table (the number of remaining cells in the operation table) 308 is input to the EXOR gate 302, and the exclusive OR is calculated by the EXOR gate 302, so that addresses having different numbers of remaining cells are obtained. Is obtained.

The result is masked by the AND gate 303, and the output of the AND gate 303 is processed by the priority decoder 304 and the encoder 305, so that the insertion addresses sa1 and sa0 larger than the competition winning address and the number of remaining cells change. Can be requested.

The operation of the conflict determination circuit 111 will be described.

As shown in FIG. 2, the contention determination circuit 111
Indicates the table information 205 from the operation table 202 and the cell transmission request signal 20 from the memory control units 107 to 109.
6 and once per cell time, for the only route that has a cell transmission request among the input routes and has the largest number of cells remaining to be transmitted in the operation table and has the highest priority among them. A contention processing function for generating a cell transmission permission signal.
Operation table 2 based on the determination result of the conflict determination circuit 111
02, the output route is read out, and the cell transmission request permission signal 2
07 is generated.

Referring to the circuit diagram of FIG.
The specific operation of No. 11 will be described.

In FIG. 6, reference numerals 406 and 407 denote path numbers EC0 to EC2 input to the decoder 401 and cell transmission request signal inputs rq0 to rq2, respectively. The cell transmission request signal 407 is input to the AND gate 402,
AND operation is performed with one output.

Now, regarding the cell transmission request signal 407,
When there is a cell transmission request, it is defined as "H", and when there is no cell transmission request, it is defined as "L".
01, the route number E given from the operation table 202
C0 is decoded, and the AND gate 402 performs a logical AND with the cell transmission request signal input 407 from each route. And
Output result 4 of AND gate 402 by OR gate 403
By taking the logical sum of 08 to 410, a cell transmission request presence / absence signal from the route EC0 is obtained as the output 411.

The cell transmission request presence / absence signal 412 from the route EC1 and the cell transmission request presence / absence signal 413 from the route EC2 obtained as described above are input to the priority decoder 404. The one with the highest priority is selected. When this signal is encoded by the encoder 405, a competition winning address 414 is obtained. This competition winning address 414
Indicates the address of the operation table 202.

As described above, the multiplexing control device 100 according to the first embodiment includes input lines 101 to 103 (input lines 1 to 3), cell buffer memories 104 to 106, memory control units 107 to 109, input line 1 A guaranteed bandwidth setting table unit 112 for setting each guaranteed bandwidth for
A contention determination circuit unit 111 is provided for determining an incoming line for which transmission is permitted according to the setting contents of the guaranteed band setting table unit 112. The guaranteed band setting table unit 112 is capable of setting the number of output cells per unit time for each incoming line. Original table 20
1, indicating the transmission priority order for each incoming line, comprising an operation table 202 and a timer 203, which are independently updated every one cell time, and configured such that the contention determination circuit unit 111 controls the contention based on the operation table 202. Therefore, since the operation table 202 is rearranged in descending order of transmission priority based on the number of cells guaranteed to be transmitted per cell time, the number of cells transmitted per unit time for each incoming line is guaranteed, and the degree of freedom of setting for each incoming line is increased. And high-precision priority control can be realized.

Second Embodiment FIG. 9 is a diagram showing the overall configuration of a multiplexing control device according to a second embodiment of the present invention, and is an example in the case of three VCs.

In FIG. 9, the multiplexing control device 500
Incoming line 501 (incoming line 1), cell buffer memory 502, memory control unit 503, outgoing line 504, conflict determination circuit unit 505
And a guaranteed bandwidth setting table unit 506.

The cell buffer memory 502 is a memory for storing cells input from the input line 1. This memory is a memory control unit 50 that functions as an independent FIFO memory for each VC (Virtual Channel).
3 is controlled.

When a valid cell is input to the cell buffer memory 502, the memory control unit 503 transmits a cell transmission request signal to the output line 504 to the conflict determination circuit unit 505. When one or more valid cells are stored for each VC, the memory control unit 503 sends a cell transmission request signal to the contention determination circuit unit 5.
Continue transmission to 05. When all the stored cells are transmitted, the transmission of the cell transmission request signal is stopped.

The guaranteed bandwidth setting table section 506 is a table for setting each guaranteed bandwidth for an input VC.

The contention determination circuit unit 505 determines an incoming line for which transmission is permitted according to the setting contents of the guaranteed band setting table unit 506, and transmits a cell transmission permission signal to the memory control unit of the corresponding incoming line. The configuration example of the conflict determination circuit unit 505 can be realized by a circuit example similar to that of FIG.

FIG. 10 is a block diagram showing a connection configuration between the contention determination circuit unit 505 and the guaranteed bandwidth setting table unit 506.

In FIG. 10, the guaranteed bandwidth setting table unit 506 includes a setting source table 601 (first table),
Operation table 602 (second table) and timer 60
3

As shown in FIG. 11, the setting source table 601 stores the number of guaranteed transmission cells RT and V per unit time for each VC.
It is a table of C number RVC. If there are VCs having the same number of guaranteed transmission cells RT per unit time, the route written to a smaller address in the setting source table 601 has higher priority. That is, the setting source table 601 writes the setting information in descending order from the route having the higher priority.

The timer 603 measures a unit time specified in cell time units, and transmits a pulse to the setting source table 601 for each unit time. Setting source table 60
1 receives the pulse from the timer 603 and transfers the contents of the setting source table 601 to the operation table 602.

The operation table 602 is, as shown in FIG. 12, a table of the transmission guarantee remaining cell number ET and the corresponding VC number EVC, and is constituted by a register capable of executing a shift in an arbitrary address section. The operation table 602 performs an update process once each time a valid cell is sent out so that the priority order becomes descending. The process of updating the operation table 602 is the same as in the first embodiment. The operation table 60
The shift processing and the insertion processing in the update processing 2 can also be realized by the circuit shown in FIG.

Hereinafter, the operation of the multiplexing control device 500 configured as described above will be described.

First, externally, according to FIGS. 9 and 10,
The number of cells guaranteed for transmission per unit time and the pulse generation period of the timer are set in the setting source table 601. After the setting, the setting parameter 604 is transferred from the setting source table 601 to the operation table 602 by a pulse generated by the timer 603 (FIG. 10). Then, table information 605 is output from the operation table 602 to the conflict determination circuit unit 505.

When a valid cell whose VC is VC0 is input from the input line 1, the cell is saved in the cell buffer memory 502, and the VC of the cell input from the memory control unit 503 is input.
0, the transmission request signal 606 corresponding to the contention determination circuit 50
5 is sent.

The conflict determination circuit unit 505 refers to the operation table 602 and transmits to the memory control unit 503 a cell transmission permission signal 607 for the VC having the highest priority among the VCs that have requested cell transmission. When the cell transmission permission signal 607 is transmitted to VC0 and the cell of VC0 is transmitted, the operation table 602 is updated, and if the number of remaining cells of VC0 is not 0, it is decremented. As a result of the decrement, if the number of remaining cells becomes smaller than the number of remaining cells at the next address in the table, a shift process is performed.

Such shift processing and insertion processing are performed as follows.
As in the first embodiment, for example, it can be realized by the operation table updating circuit shown in FIG.

As described above, the multiplexing control device 500 according to the second embodiment includes the input line 501 (input line 1), the cell buffer memory 502, the memory control unit 503, and the input VC. Guaranteed bandwidth setting table section 506 for setting the guaranteed bandwidth, guaranteed bandwidth setting table section 5
06, the contention determination circuit unit 505 that determines an incoming line for which transmission is permitted according to the setting content of the setting unit 06. The guaranteed bandwidth setting table unit 506 includes a setting source table 601 that can set the number of output cells per unit time for each VC. An operation table 6 indicating transmission priority for each VC and independently updating every cell time
02 and a timer 603, and the operation table 60
2, the contention determination circuit unit 505 controls the contention, so that the operation table 602 is rearranged in descending order of transmission priority based on the number of cells guaranteed to be transmitted per cell time. , The number of cells transmitted per unit time can be guaranteed, and highly accurate priority control can be realized.

Note that the multiplexing control device according to each of the above embodiments can be applied to a wideband large-capacity routing server having a bandwidth control function for each VC as described above. Of course, it is needless to say that the present invention can be applied to all the multiplexing apparatuses having a plurality of input lines.

Further, as long as it has a first table and a second table and controls the conflict based on the second table, any method of controlling the conflict or updating the table may be used. .

In each of the above embodiments, the cell includes the AT.
Although the M cell is used, the packet is not limited to the ATM cell and may be any packet. For example, the cell header portion and the payload portion may have a byte length and format different from those of the ATM cell.

In each of the above embodiments, the function of storing data is described using a FIFO. However, data may be stored in a memory using pointer control.

Further, it goes without saying that the types, the number of connections, the connection forms, and the like of the memory, the memory control unit, the gate circuit, the decoders and the like constituting the multiplexing control device and various circuits are not limited to the above-described embodiments.

[0089]

In the multiplexing control device according to the present invention, a first table in which the number of output cells per unit time can be set for each incoming line, and a transmission priority order for each incoming line are indicated. And a second table for autonomous updating, and configured to control competition based on the second table.
The number of cells transmitted per unit time for each incoming line can be guaranteed, and a high degree of freedom in setting freedom and high-precision control can be realized for each incoming line.

In the multiplexing control device according to the present invention, each VC
A first table in which the number of output cells per unit time can be set for each cell, and a second table that indicates the transmission priority order for each VC and that is updated independently for each cell time. Since the contention is controlled on the basis of the contention, the number of cells transmitted per unit time for each input VC can be guaranteed, and highly accurate priority control can be realized.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of a multiplexing control device according to a first embodiment to which the present invention has been applied.

FIG. 2 is a block diagram illustrating a connection configuration between a contention determination circuit unit and a guaranteed bandwidth setting table unit of the multiplex control device.

FIG. 3 is a diagram showing a setting source table of the multiplexing control device.

FIG. 4 is a diagram showing an operation table of the multiplex control device.

FIG. 5 is a diagram showing a part of an operation table updating circuit of the multiplex control device.

FIG. 6 is a circuit diagram showing a configuration of a contention determination circuit unit of the multiplex control device.

FIG. 7 is a flowchart showing a flow of an operation table update process of the multiplex control device.

FIG. 8 is a diagram showing an example of updating the operation table of the multiplexing control device.

FIG. 9 is a diagram illustrating a configuration of a multiplexing control device according to a second embodiment to which the present invention has been applied.

FIG. 10 is a block diagram showing a connection configuration between a contention determination circuit unit and a guaranteed bandwidth setting table unit of the multiplex control device.

FIG. 11 is a diagram showing a setting source table of the multiplexing control device.

FIG. 12 is a diagram showing an operation table of the multiplex control device.

[Explanation of symbols]

100,500 multiplexing control device, 101-103,5
01 incoming line (input lines 1 to 3), 104 to 106,502
Cell buffer memory, 107-109, 503 memory control unit, 110 outgoing line, 111, 505 conflict determination circuit unit, 112, 506 Guaranteed bandwidth setting table unit, 20
1,601 setting source table (first table), 20
2,602 operation table (second table), 20
3,603 timer

Claims (8)

[Claims] A multiplexing control device having a plurality of incoming lines, wherein a first number of output cells per unit time can be set for each incoming line.
And a second table indicating transmission priority for each incoming line and updating independently on a cell-by-cell basis, wherein contention is controlled based on the second table. Control device. 2. A multiplexing control device to which an input line in which a plurality of VCs are multiplexed is connected, wherein a first number of output cells per unit time can be set for each VC.
And a second table indicating transmission priorities for each VC and updating independently on a cell-by-cell basis, wherein contention is controlled based on the second table. Control device. 3. The first table is a table of the number of cells guaranteed for transmission per unit time per input route and an input route.
2. The multiplexing control device according to claim 1, wherein the setting information is written in descending order from a route having a higher priority. 4. The first table is a table of the number of cells guaranteed for transmission and the number of VCs per unit time for each VC, wherein setting information is written in descending order from a route having a higher priority. The multiplexing control device according to claim 2. 5. The second table is a table of input routes corresponding to the number of cells guaranteed to be transmitted, and performs an update process once every valid cell is transmitted so as to be in descending order of priority. 2. The multiplexing control device according to claim 1, wherein the multiplexing control is performed. 6. The second table is a table of VC numbers corresponding to the number of remaining cells for which transmission is guaranteed, and performs an update process once every valid cell is transmitted so as to be in descending order of priority. 3. The multiplexing control device according to claim 2, wherein: 7. In the updating of the second table, when a prescribed number of cells are output from an outgoing line for each VC, the priority is lowered, and after a certain period of time, control is performed to return to the initial priority. 7. The multiplexing control device according to claim 2, wherein 8. The multiplexing control device according to claim 1, wherein said cells are ATM cells.