JPH11145973A - Atm communication controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform communication at an accurate transmission rate by providing a cell timer for absolute time generation and a read timer for transmission time retrieval and matching the absolute time and communication time by making the read timer follow up the cell timer when transmission time delay is generated by multiple hits. SOLUTION: The output tx- time 7 of the read timer 14 is inputted as the retrieval data of the transmission time registered in a CAM 4, and when it matches the transmission time registered in the CAM 4, the hit 9 of the CAM 4 becomes 1 and the address is outputted from the output address- out 8 of the CAM 4. A transmission part 5 performs ATM cell transmission of a channel allocated to the address. By the end, a scheduler 10 calculates the next transmission time from a transmission rate 12, outputs it to a next- time 11 and rewrites the channel transmission time of the CAM 4. Thus, it does not match the value of the read timer 14, the hit 9 becomes 0, the read timer 14 is counted up, and when a difference with the cell timer 13 is present, it is caught up.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ATM communication control device, and more particularly, to an ATM communication control device of a control device for setting transmission scheduling of a plurality of channels using a CAM.

[0002]

2. Description of the Related Art Conventionally, this kind of ATM communication control apparatus has
ATM (Asynchronous Transfer)
Mode) ABR which is one of the service classes of communication
When realizing (Available Bit Rate), the circuit is configured by a method of controlling transmission scheduling using CAM, and is used for the purpose of performing data transmission at an optimal transmission rate by feeding back the network congestion state. I have.

FIG. 7 shows a conventional circuit configuration. Transmission unit 5
Is the address output addresses of the ABR scheduler 1.
The ATM cell is transmitted by s_out8. The ABR scheduler 1 includes a timer 3 and a scheduler 10 that determines a transmission time of an ATM cell.

There are two operation modes of the CAM 4, a CAM mode and a RAM mode. In the RAM mode, cha is assigned to the address corresponding to the channel number.
Write nnel transmission time. In the CAM mode, a time tx_time7 serving as search data is input, and if the input data tx_time7 matches the transmission time of the channel registered in the CAM 4, the address corresponding to the channel is addressed.
_Out8, and hit9 becomes “1”. (Here, the case where hit9 becomes “1” is called “hit”.)

The timer 3 generated from the system clock 2 has data (time) t for searching for a transmission time.
x_time 7 is generated, and the count-up signal 6 from the transmitter 5 counts up at intervals at which the transmitter 5 can process one ATM cell for transmission.

The timer 3 is set to the "hit" state.
9 stops. The transmitting unit 5 receives the received address.
The channel ATM cell corresponding to the address of ss_out8 is transmitted. After transmission, the scheduler 10
The next transmission time is calculated from the transmission rate of the "hit" channel, and the CAM 4 is set in the RAM mode to rewrite data. "Hit" is released ("0") because the rewritten data and timer 3 no longer match.
Then, the timer 3 resumes its operation, and continues counting up until it coincides with the next transmission time.

If there are channels with the same transmission time, priority is given to the smaller CAM4 address value, and "hit" is not released until all channels at the same time are processed. Further, the timer 3 is stopped until this processing ends.

The operation of the above conventional example will be described with reference to the timing chart of FIG. 8 together with FIG.

[0009] Two channels (channel_
A. channel_B), each of which is scheduled at a transmission rate of １ ／ of the band, and the initial values of the transmission time are “1” and “1”, respectively, as shown in FIG.
"1" is registered in CAM4.

When the time of the timer 3 becomes "1", the CAM
4 is in a hit state (timing of T1). chan
The transmission of nel_A has been completed, and the scheduler 10 determines that the interval “3” obtained from the current time “1” and the transmission rate 12
Is output to next_time11, and is written to CAM4 at the timing of T2.
The process of “annel_A” ends.

Although the processing of channel_A has been completed, the transmission time of channel_B is also “1”, so that the hit state continues further, and the processing of channel_B is cha
This is performed in the same manner as nnel_A. (Here, a case where there are a plurality of channels scheduled at the same time and the “hit” state of the CAM 4 continues is called a multi-hit.)

The transmission of channel_B is completed, and the next transmission time is the next “4 (= 1 + 3)” of the current time “1” and the interval “3” obtained from the transmission rate 12 as next.
_Time11 and output to CAM4 at the timing of T3.
Write to. When the data registered in the CAM 4 is updated and the time input to the CAM 4 does not match, the hit is released and the timer 3 restarts counting up.

The value of the timer 3 keeps counting up until there is a channel as a candidate for the next transmission time.
It changes from “1 → 2 → 3 → 4”. When the timer 3 counts up, the channel is channeled at the next transmission time “4”.
el_A. The channel_B becomes the “hit” state again (timing of T4), and the channel_A. ch
When the transmission of the “annel_B” is completed, the transmission time “7 (= 4 + 3)” is written in the CAM4, and the process ends.

[0014]

The problem is that a plurality of channels
When the channel is registered in the CAM and there is a channel with the same transmission time, FIG.
As shown in (H), data is not transmitted at a correct transmission rate.

The reason is that, since the timer 3 stops counting up to generate a multi-hit, the actual time (G) at which the transmission data must be actually transmitted and the transmission time (H) generated by the timer 3 Gap with
This is because, by repeating this scheduling operation, the transmission gap increases, and the scheduled transmission time and the actual transmission time gradually move apart, so that the transmission rate cannot be maintained.

Conventionally, this kind of ATM communication control apparatus has a plurality of channels as shown in the flowchart of FIG. 9 shown in Japanese Patent Application Laid-Open No. 08-242238.
If l is scheduled at the same time, priority control is performed by the priority encoder, and c is assigned a higher priority.
Only the channel is transmitted, and the value of the timer is incremented. When the value of the timer is updated, the transmission time registered in the CAM does not match the search time of the CAM, so that a channel with a low priority is not transmitted, and as a result, the transmission rate cannot be maintained.

An object of the present invention is to provide a scheduling method for a conventional circuit as described above, wherein there are a plurality of channels scheduled at the same time.
An object of the present invention is to provide an ATM communication control device capable of performing data communication at an accurate transmission rate by adding another timer that is extended in function to a conventional timer.

[0018]

In order to achieve the above object, an ATM communication control device according to the present invention is an ATM communication control device having two timers, a cell timer and a read timer. The timer is generated from the system clock and counts up at a certain interval to represent the absolute time. The read timer refers to the cell timer and the variable length within the cell timer count-up interval. Count at intervals of
When the transmission time is later than the absolute time, it counts up at a faster rate than the cell timer count-up interval,
It operates to catch up with the time of the timer.

The delay of the hard timer caused by the multi-hit is counted up by an operation faster than the count-up of the cell timer after the hit is released.
The difference between the read timer and the cell timer is eliminated to maintain the transmission rate.

An ATM communication controller having a cell timer, a read timer, a CAM, and a scheduler, wherein the cell timer is generated from a system clock and counts up at a certain interval. ,
The count result is output to the read timer, and the read timer outputs the search data of the registered transmission time to the CAM by variably counting up within the interval of the cell timer. Yes, CAM is
The transmission time of each transmission channel is registered and the transmission time is searched. When the output of the read timer matches the transmission time registered in the CAM, an address for allocating an ATM channel to be transmitted is output. Determines the next transmission time from the transmission rate of each channel,
The transmission time of the AM channel is rewritten.

Further, when a plurality of channels are scheduled at the same time, there is further provided a circuit for shifting transmission times to eliminate multi-hit channels.

An ATM communication control device having a cell timer, a read timer, a holding circuit, a timing generation circuit, a comparison circuit, a scheduler, a CAM, and a write control circuit, wherein: The timer is generated from the system clock, counts up at a certain interval, and outputs the count and the read timer.The read timer is variable within the interval at which the cell timer counts up. And outputs the count result to a holding circuit, a comparison circuit, and a CAM. The latch circuit holds the count result of the read timer and outputs the data to the comparison circuit. The timing generator generates the timing held by the latch circuit, and the comparator generates the timing. A current transmission rate input from Yura, a new transmission rate, and inputs the outputs of the read timer latch circuit, and outputs a write data transmission time to the write control circuit,
The scheduler determines the transmission time from the transmission rate and outputs it to the write control circuit, and outputs the current transmission rate and the new transmission rate to the comparison circuit.
M receives the output of the read timer and the output of the write control circuit as inputs, and searches for the transmission time and transmission time of each transmission channel. The write control circuit compares the output of the scheduler and the output of the comparison circuit. As an input, the write data of the transmission time is controlled and output to the CAM.

[0023]

(First Embodiment of the Invention) Next, a first embodiment of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, in the present invention, A
The BR scheduler 1 includes a cell timer 13 which is generated from the system clock 2 and counts up at a certain interval, a read timer 14 which counts up at a variable length interval within the above-described timer interval, C for registering the transmission time of each channel
The block is composed of an AM 4 and a scheduler 10 that determines the next transmission time from the transmission rate 12 of each channel.

In response to the count-up signal 6 from the transmission unit 5, the cell timer 13 determines that the transmission unit 5 has one ATM.
It is always counted up at intervals required to spend the cell transmission process. Read timer 14 is CAM4
While hit9 of "1" is "1", counting up is stopped, but if hit9 is "0", counting up is performed in synchronization with the cell timer 13. However, when a difference occurs between the cell timer 13 and the read timer 14 as a result of the CAM 4 being continuously in the hit state, the cell timer 13 counts up at the speed of the system clock 12 and the cell timer 13 always keeps counting. Operate to follow. At this time, the read timer 14 does not overtake the cell timer 13.

Output tx_tim of read timer 14
e7 is input as search data of the transmission time registered in the CAM4. If the output tx_time7 of the read timer 14 input to the CAM4 matches the transmission time registered in the CAM4, the CAM4 hit
9 becomes “1”, and at the same time, the output addre of CAM4
An address is output from ss_out8. Transmission unit 5
Transmits the ATM cell of the channel allocated to this address.

When the process of the transmitting unit 5 is completed, the scheduler 10 calculates the next transmission time from the above-mentioned channel transmission rate 12 and outputs it to the next_time 11, and rewrites the channel transmission time of the CAM4. Since the transmission time of the CAM 4 has been rewritten, the value of the read timer 14 does not match, and the hit 9 becomes “0”. As a result, the read timer 14 restarts counting up. At this time, read timer 1
4 counts up to the same time as the cell timer 13 at the speed of the system clock 12 if there is a difference from the cell timer 13.

Next, the operation of FIG. 1 will be described with reference to the timing chart of FIG. 2 and the flowchart of FIG.

[0029] Two channels (channel_
A. channel_B), each of which is scheduled at a transmission rate of 1/3 of the band. CAM4
The address “0” corresponds to channel_A, the address “1” corresponds to channel_B, and the initial values of the transmission times are “1” and “1”, respectively, which are registered in the CAM 4 ((C)). , (D) T0). Other CAM4 addresses include chann.
el is not allocated.

Counting in synchronization with cell timer 13
When the read timer 14 is up, the time becomes “1” (T
1 timing), cha registered in CAM4
nnel_A coincides with the transmission time (S3 in FIG. 5), and CA
Hit9 of M4 becomes "1" (S4 in FIG. 5). At the same time, the address “0” is output from the output address_out 8 of the CAM 4 (S 5 in FIG. 5), and the transmitting unit 5
The nnel_A ATM cell is transmitted (S6 in FIG. 5).
When the transmission of channel_A is completed, the scheduler 10 sets the sum “4 (= 1 + 1) of the current time“ 1 ”and the interval“ 3 ”obtained from the transmission rate 12 of channel_A.
3) "is output to next_time11 (S in FIG. 5).
7), next_time is added to the address “0” of the CAM4.
The value of 11 is written (T2 timing in FIG. 2C, S8 in FIG. 5), and the process of channel_A ends.

The processing of channel_A has been completed, but the transmission time of channel_B is also “1”, so that the hit state continues. The process of channel_B is cha
After the transmission of the ATM cell by the transmission unit 5, the scheduler 10 transmits the next transmission time “4” to the address “1” of the CAM 4 by next_tim.
e11, and writes the value of next_time11 to CAM4 (T3 timing of (D)) channel
The processing of l_B ends.

When the process of channel_B is completed and the read timer 14 does not match the data registered in the CAM 4, "hit" is released (S9 in FIG. 5), and the read timer 14 counts up. Resume. At this time, the read timer 14 determines the timer value stopped by the multi-hit and the cell timer 13.
Therefore, the cell clock 13 follows the cell timer 13 at the speed of the system clock 12, and the next transmission time "4"
Catches up with cell timer 13 in the stage before (T3 and T
4).

At this time, in the flowchart, S9, S1
0, S11, S2, and S9 are repeated twice.

The above-described operation is repeated at the next transmission time "4" (timing of T4), but the delay of the read timer 14 is recovered.

As a result, as shown in FIG.
The transmission rate (1/3) of the channel is maintained, and the channel A and the channel_B are transmitted once every three times.
TM cells will be transmitted.

(Embodiment 2) Next, a second embodiment of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 3, ABR scheduler 1
Is a cell timer 13 generated from the system clock 12 and counting up at a certain interval, a read timer 14 counting up at a variable length interval at the above-mentioned timer interval, and transmission of each channel. CAM 4 for registering time, and scheduler 10 for determining transmission time from transmission rate 12 of each channel
And a latch circuit 16 for holding the read timer 14
A timing generation circuit 15 for generating a timing for holding the read timer 14, a comparison circuit 18 for comparing the data Q17 held by the latch circuit 16 with the count result of the read timer 14, and an output of the comparison circuit 18. The write control circuit 22 controls the write data at the transmission time from the COMP 19.

The cell timer 13 is always counted up by the count-up signal 6 from the transmitter 5 at intervals necessary for the transmitter 5 to spend one ATM cell transmitting process. On the other hand, the read timer 14
The count-up is stopped while hit9 of M4 is "1". If hit9 is "0", the count-up is performed in synchronization with the cell timer 13. However, if a difference occurs between the cell timer 13 and the read timer 14 as a result of the CAM 4 being continuously in the hit state, the count is incremented at the speed of the system clock 12 and the cell timer 13 is always maintained. 13 to follow. At this time,
The read timer 14 does not overtake the cell timer 13.

Output tx_tim of read timer 14
e7 is input as search data of the transmission time registered in the CAM4. If the input time tx_time7 of the read timer 14 matches the transmission time registered in the CAM4, the hit9 of the CAM4 becomes "1", and at the same time, the address is output from the output address out8 of the CAM4. The transmitting unit 5 transmits the ATM cell of the channel allocated to this address.

The latch circuit 16 includes a read timer 14
Each time changes, the output tx_time7 of the previous read timer 14 is always held. The comparison circuit 18 receives the current transmission rate old_rat from the scheduler 10.
e21 and a new transmission rate new_rate20 are input, and a COMP19 is generated from the output Q17 of the latch circuit 16 and the output tx_time7 of the read timer 14 and output to the write control circuit 22. Comparison circuit 18
The output COMP19 of the current transmission rate old_ra
When the value of the output Q17 of the latch circuit 16 matches the value of the output tx_time7 of the read timer 14, the value becomes "1" when te21 matches the new transmission rate new_rate20.

When the process of the transmitting unit 5 is completed, the scheduler 10 calculates the next transmission time from the channel transmission rate 12 and outputs the next transmission time next_time 11 to the write control circuit 22.

In the write control circuit 22, the comparison circuit 18
From COMP 19 and next from scheduler 10
_Time11 rewrites the transmission time of the channel. At this time, if COMP19 is "1", next
Write a value obtained by adding +1 to _time11 to CAM4,
If OMP19 is "0", next_time11 is written.

Since the transmission time of the CAM 4 has been rewritten, the value of the read timer 14 does not match, and
9 becomes "0". As a result, the read timer 14 restarts counting up.

Next, the circuit operation of FIG. 3 will be described with reference to the time chart of FIG. 4 and the flowchart of FIG.

The four channels (channel_
A, channel_B, channel_C, cha
nnel_D), each of which is scheduled at a transmission rate of １ ／ band. Each transmission rate 12 is always constant (= 1/4) (old_ra
te21 = new_rate20). CAM
4, channel_A for address “0”, channel_B for address “1”, and c for address “2”.
channel_C, channel "3" at address "3"
_D, and the initial values of the transmission time are “1”, “1”, “1”, and “2”, respectively, which are registered in the CAM 4. The other address is chann
el is not allocated. ((F), (G),
(Timing of T0 of (H) and (I))

Counting in synchronization with cell timer 13
When the time reaches “1” (timing of T1), the read timer 14 (S1 in FIG. 6) matches the transmission time of channel_A registered in CAM4 (S3 in FIG. 6), and hit9 of CAM4 is It becomes “1” (FIG. 6
S4). Addres output from CAM4 at the same time
Since the value of s_out8 is “0”, the transmitting unit 5
The ATM cell of nel_A is transmitted (S6 in FIG. 6). c
The transmission of the channel_A is completed, and the scheduler 10 determines that the current time “1” and the transmission rate 1 of the channel_A
Sum “5 (= 1 + 4)” with the interval “4” obtained from 2
Is output to the write control circuit 22 as next_time11 (S7 in FIG. 6). The write control circuit 22
Since the OMP 19 is “0” (S15 in FIG. 6), next_ti is set as the next transmission time at the address “0” of the CAM4.
"5" of me11 is written (timing of T2 in FIG. 4F, S8 in FIG. 6). Finally, the latch circuit 16 holds the value "1" of tx_time7 (12 in FIG. 6). Thus, the process of channel_A ends.

Although the process of channel_A has been completed, the transmission time of channel_B is also “1”, so that the hit state continues, and the process of channel_B starts. After the transmission of the ATM cell by the transmission unit 5 (S in FIG. 6)
6), the scheduler 10 determines that the current time "1"
Interval “4” calculated from transmission rate 12 of nel_B
The sum “5 (= 1 + 4)” is written to the write control circuit 22 by n.
It is output as ext_time11 (S7 in FIG. 6).
When the data Q17 held by the latch circuit 16 is "1",
The output tx_time7 of the read timer 11 is "1"
Since the old_rate21-new_rate220, the output COMP 19 of the comparison circuit 18 becomes "1" (timing of T2 in FIG. 4E, S14 in FIG. 6). Since the COMP 19 is “1”, the write control circuit 22
The transmission time “6 (= 5 + 1)” obtained by adding +1 to next_time 11 is written to the address “1” of AM4 (S16 in the figure), and the process of channel_B ends (timing of (G) T3).

The processing of channel_B ends,
Since the transmission time of channel_C is “1”, the hit state further continues, and like channel_B, channel is performed.
The transmission process of el_C is started. channel_C
As in channel_B, COMP 19 becomes “1”, and “6” is written to the address “2” of CAM 4 (timing of T4 in (H)).

The read time of the read timer 14 is "1".
Count is started when the channel corresponding to is lost (S2, S3, S9, S10, S10 in FIG. 6).
S11). The read timer 14 becomes "2" and the ch
The inside_D is in the hit state (S4 in FIG. 6). The transmitting unit 5 transmits the channel_D ATM cell (S6 in FIG. 6), and the scheduler 10 outputs the next transmission time “6 (= 2 + 4)” to the write control circuit 22 (S7 in FIG. 6). At this time, the output Q1 of the latch circuit 16 is output.
7 (= "1") and the output tx_t of the read timer 14
Since im7 (= "2") does not match, the comparison circuit 18
Becomes "0" (T4 in FIG. 4E).
Timing, S15 in FIG. 6). Write control circuit 22
Since the COMP 19 is “0”, the transmission time next_time 11 from the scheduler 10 is written to the address “3” of the CAM 4 as it is (S8 in FIG. 6), and tx_ti
me7 is held by the latch circuit 16 (S12 in FIG. 6),
The process of channel_D ends.

When the process of channel_D is completed and the read timer 14 does not match the data registered in the CAM 4, "hit" is released (S9 in FIG. 6), and the read timer 14 counts up. Resume. At this time, the read timer 14 follows the cell timer 13 at the speed of the system clock 12 because of the difference between the timer value tx_time7 stopped by the multi-hit and the cell timer 13. Is counted up to "5" ((B))
Between T5 and T6 in FIG. 6 (S11 in FIG. 6).

By repeating the above operation after T6, the channel having a multi-hit gradually disappears. Finally, the result is as shown in FIG. 4 (k) transmission data sequence, and all channels are transmitted at the correct transmission rate (1/4).

In the second embodiment of the present invention, in addition to the circuit of the first embodiment, when a plurality of channels are scheduled at the same time, a circuit for shifting the transmission time and avoiding a multi-hit is provided. Is added.

In the first embodiment, when the number of channels scheduled at the same time is large, the difference between the cell timer and the read timer due to multiple hits increases. Depending on the cycle of the system clock and the cycle of the cell timer, the read timer cannot follow the cell timer, and as a result, an accurate transmission rate may not be maintained. On the other hand, in the second embodiment, by eliminating channels scheduled at the same time, a multi-hit is avoided, so that the difference between the cell timer and the read timer does not widen.

In the second embodiment of the present invention, in addition to the first embodiment, a multi-hit channel
There is an effect that an accurate transmission rate is maintained without being affected by the number of l.

[0055]

The first effect is that the correct transmission rate is always maintained. The reason is that by providing a cell timer that generates an absolute time and a read timer that searches for the transmission time, when the transmission time is delayed due to a multi-hit, the read timer is activated.
This is because the timer follows the timer, and the absolute time always coincides with the transmission time.

The second effect is that the multi-hit chan
This is to eliminate nel. The reason is that channels of the same transmission time are continuously transmitted and the next transmission time is set to C
This is because, when writing to the AM, the transmission time calculated by the scheduler is incremented by “+1” and the transmission time is arbitrarily shifted.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a time chart illustrating the operation of the first exemplary embodiment of the present invention.

FIG. 3 is a block diagram of a second embodiment of the present invention.

FIG. 4 is a time chart illustrating the operation of the second exemplary embodiment of the present invention.

FIG. 5 is a flowchart for explaining the first embodiment.

FIG. 6 is a flowchart illustrating a second embodiment.

FIG. 7 is a block diagram of a conventional embodiment.

FIG. 8 is a time chart showing the operation of the conventional embodiment. The timing chart (a) shows the operation of the conventional embodiment. The timing chart (b) shows a gap in the transmission data sequence.

FIG. 9 is a flowchart described in Japanese Patent Application Laid-Open No. 8-242238 of the prior art.

[Explanation of symbols]

 1 ABR scheduler 2 System clock 3 Timer 4 CAM 5 Transmitter 6 Count up signal 7 tx_time 8 address_out 9 hit 10 Scheduler 11 next_time 12 Transmission rate 13 Cell timer (absolute time timer) 14 Read timer 15 Timing generation circuit 16 Latch circuit 17 Q 18 Comparison circuit 19 COMP 20 new_rate 21 old_rate 22 Write control circuit

Claims (5)

[Claims] An ATM communication controller having two timers, a cell timer and a read timer, wherein the cell timer is generated from a system clock,
The absolute time is counted up at certain intervals to indicate the absolute time. The read timer refers to the cell timer,
Counts up at variable length intervals within the timer count-up interval, checks the transmission time, and when the transmission time is later than the absolute time, the speed is faster than the cell timer count-up interval An ATM communication control device which counts up and operates so as to always catch up with the time of a cell timer. 2. A delay of a hard timer caused by a multi-hit is counted up by an operation faster than a count-up of a cell timer after a hit is released, and transmitted without a difference between a read timer and a cell timer. 2. The AT according to claim 1, wherein the rate is maintained.
M communication control device. 3. An ATM communication controller having a cell timer, a read timer, a CAM, and a scheduler, wherein the cell timer is generated from a system clock.
It counts up at a certain interval and outputs the count result to the read timer. The read timer variably counts up within the interval of the cell timer, and the transmission registered in the CAM is performed. The CAM outputs time search data. The CAM registers the transmission time of each transmission channel and searches for the transmission time, and when the output of the read timer matches the transmission time registered in the CAM. AT to send to
An ATM communication control device for outputting an address for allocating M channels, wherein the scheduler determines the next transmission time from the transmission rate of each channel and rewrites the transmission time of the CAM channel. 4. The ATM communication control device according to claim 3, further comprising a circuit for shifting transmission times and eliminating multi-hit channels when a plurality of channels are scheduled at the same time. 5. A cell timer, a read timer, a holding circuit, a timing generation circuit, a comparison circuit,
An ATM communication controller having a scheduler, a CAM, and a write control circuit, wherein the cell timer is generated from a system clock,
It counts up at a certain interval and outputs the count and the read timer.The read timer variably counts up within the cell timer count up interval and counts the count result. The latch circuit holds the count result of the read timer and outputs the data to the comparison circuit. The timing generation circuit includes a latch circuit. The comparison circuit receives the current transmission rate input from the scheduler, the new transmission rate, the output of the latch circuit and the output of the read timer, and writes the transmission time write data. Is output to the write control circuit, and the scheduler determines the transmission time from the transmission rate and The CAM outputs the current transmission rate and the new transmission rate to the comparison circuit. The CAM receives the output of the read timer and the output of the write control circuit as inputs, and transmits each transmission channel. The write control circuit receives the output of the scheduler and the output of the comparison circuit, controls the write data of the transmission time, and outputs the data to the CAM. ATM communication control device.