JPH11145621A - Multi-layer interconnection substrate and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To manufacture a multi-layer interconnection substrate, wherein it is possible to obtain higher wiring density, a cylindrical via comprising an integral land part at its upper part is stacked in a simple process, with no polishing process required. SOLUTION: An insulating resin layer 2 is formed on an insulating substrate 1 where a conductor pattern 4 and a land part 5 are formed, and a through hole having an aspect ratio 0.5-2 is so formed that the land part 5 is exposed above the resin layer 2. Here, after the upper surface of the resin layer and the inner surface of the through hole are coated with a copper tin-film 6 by electroless plating, a resist pattern 17 is formed over it, and the through hole is filled by electrolytic copper plating using a copper sulfate plating bath of weight ratio of copper sulfate/sulfuric acid 0.15-0.33 further, plating layers 7 and 8 whose upper surface is flat are so formed flush with the resist layer, then the resist 17 and a copper thin-film 16 below it are removed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin-film multilayer wiring board formed by a build-up method in which a metallic conductive wiring layer (conductive pattern) and a resinous insulating layer are sequentially formed on the surface of an insulating substrate. It relates to a manufacturing method. According to the present invention,
It is possible to manufacture a multilayer wiring board having a high wiring density in a process that has been simplified compared to the related art. The multilayer wiring board of the present invention is intended for a board for mounting a semiconductor element, but can also be applied to a printed wiring board.

[0002]

2. Description of the Related Art As a kind of wiring board on which a semiconductor element is mounted, a thin-film type multilayer wiring board (also referred to as a thin-film multilayer circuit board) having a multi-layered wiring layer formed on an insulating substrate with a thin insulating layer interposed between layers. ). The wiring layer is made of a metal layer formed by plating, sputtering, or the like, and is patterned using a resist or the like, or a metal layer is formed in a pattern from the beginning like pattern plating. The insulating layer is generally a resin layer. This type of thin film type multilayer wiring board is manufactured by a method called a build-up method in which wiring layers and resin layers are alternately stacked on an insulating substrate.

Although this multilayer wiring board is essentially a plastic substrate, a fine thin film wiring pattern is formed in multiple layers in the substrate, and high-speed signals can be propagated. The use of a ceramic multilayer wiring board, which is a general multilayer wiring board of the related art, is thinner than that of a conventional general multilayer wiring board.

FIG. 1 schematically shows an example of a typical cross-sectional structure of a conventional multilayer wiring board of this kind. In the drawing, 1, 2, and 3 are first, second, and third insulating layers, respectively, and the first insulating layer is usually an insulating substrate. Electrical connection between the conductor patterns 4 and 8 formed on the first and second insulating layers and the conductor pattern 12 formed on the third insulating layer is secured as follows.

[0005] The conductor pattern 4 formed on the first insulating layer 1 is connected to a land 5 on the same insulating layer, and the land 5 is formed at the bottom of a through hole (via hole) in the second insulating layer. And a land portion 9 on the second insulating layer 2 connected thereto through a metal layer 18 covering the wall surface and the periphery of the opening.
Connected to. The conductor pattern 8 is also connected to the land 9. The land portion 9 also has a third insulating layer 3 connected thereto through a metal layer 19 covering the bottom and the wall surface of the through hole of the third insulating layer 3 and the periphery of the opening. It is connected to the upper wiring pattern 12. The through-holes formed in the second and third insulating layers and covered with a metal layer at the bottom, the wall, and the periphery of the opening connect the wiring layers on both surfaces of the insulating layer across the insulating layer. Beer.

However, in the conventional multilayer wiring board having a general structure shown in FIG. 1, since there is no land portion above each through-hole, an upper-layer via can be formed immediately above a lower-layer via. Instead, as shown in the figure, the lands are drawn out beside the lower layer vias, and the upper layer vias are shifted in the horizontal direction. Therefore, there is a problem in that the space occupied by the via on the substrate plane is increased, the increase in the wiring density is restricted, the wiring length is increased, and the signal transmission loss is increased.

As the demand for higher speed and higher density of signals of a multilayer wiring board increases, a multilayer wiring board in which an upper via is formed immediately above a lower via has been desired. Some structures and manufacturing methods have been proposed so far.

FIG. 2 shows a typical structure of a multilayer wiring board in which lower and upper vias are directly connected to each other vertically. In the figure, 1,
Reference numerals 2 and 3 are first, second and third insulating layers. Conductive patterns 4 and 8 formed on first and second insulating layers
The vias 7, which are formed in a substantially cylindrical shape through the insulating layer on these land portions via adjacent land portions 5 and 9 formed on the same insulating layer as the conductor patterns,
It is electrically connected to the conductor pattern 12 formed on the third insulating layer via the land 10 and the land portions 9 and 13 thereon. Since the lands 9 and 13 are formed on the vias 7 and 10, respectively, the vias 10 can be vertically aligned and formed in a row just above the vias 7, and the space occupied by the vias on the substrate plane is small. Since the land is not drawn out next to the via, the wiring length can be reduced.

As a method of manufacturing the multilayer wiring board shown in FIG. 2, two methods shown in FIGS. 3 and 4 are known. In the method shown in FIG. 3, a first insulating layer (substrate) 1 having a conductor pattern 4 and a land portion 5 formed on the surface is prepared, and a layer having a thickness corresponding to a via is provided on the first insulating layer. A resist layer 15 is formed, and a through hole for a via reaching the land is formed on the land 5 by exposure and development [FIG.
(a)]. A metal (usually copper) is filled in the through hole by electroless plating or electrolytic plating so as to have a height equal to or higher than the height of the resist layer 15, and a metal pillar 7 'for a via is formed on the first insulating layer.
[FIG. 3 (b)]. Next, when the resist layer 15 is removed, the first
The via metal pillar 7 'remains on the land 5 on the insulating layer 1 of FIG. 3 (FIG. 3 (c)).

Thereafter, a resin is applied on the first insulating layer 1 to form a second insulating layer 2 having a thickness completely covering the via metal pillar 7 '[FIG. 3 (d)]. Next, the metal column is polished or the like.
The upper end surface of 7 ′ is exposed, and the upper surfaces of the metal pillar and the second insulating layer 2 are flattened [FIG. 3 (e)]. Flattened metal pillars (vias) 7
A metal layer is formed on the exposed surface of
[FIG. 3 (f)], and then a resist layer 17 is formed by a conventional method.
Is formed and patterned by exposure and development [Fig. 3 (g)],
The conductor layer 8 and the land 9 are formed on the second insulating layer 2 by removing the portion of the metal layer that is not covered with the resist layer and further removing the resist layer [FIG. 3 (h)].

FIG. 4H is formed on the second insulating layer 2 shown in FIG.
By repeating the steps (a) to (h), the third
The multilayer wiring board shown in FIG. 2 in which the via 10 penetrating through the insulating layer 3 is located, and the land portion 13 and the conductor pattern 12 are formed thereon, is manufactured.

In the second method shown in FIG. 4, a second insulating layer 2 is formed on a first insulating layer 1 having a conductor pattern 4 and a land portion 5 formed on the surface thereof. A substantially cylindrical through hole reaching the land is formed [FIG. 4 (a)]. Next, electrolytic plating is performed on the through-hole while supplying power from the land portion 5 to fill a metal to the same height as the second insulating layer, thereby forming the via 7 [FIG. 4 (b)]. In addition, FIG.
As in (h), the entire surface of the metal layer 16 is covered by sputtering or the like.
[FIG. 4 (c)] and formation of a resist pattern 18 [FIG.
(d)], the metal layer and the resist layer not covered with the resist layer are removed to form a conductor pattern 8 and a land portion 9 on the second insulating layer 2 [FIG. )].

Also in this case, the steps shown in FIGS. 4A to 4E are further repeated on the second insulating layer, and the third insulating layer, the via penetrating therethrough, and the conductor pattern and land thereabove. Is formed, the multilayer wiring board shown in FIG. 2 is manufactured.

The method shown in FIGS. 3 and 4 can produce a multilayer wiring board in which multilayered conductor patterns are connected by vias connected in a row in a vertical direction. However, in the method of manufacturing the multilayer wiring board shown in FIG. 3, the number of steps required to form one insulating layer, a via penetrating therethrough, a conductor pattern and a land thereon is different from those shown in FIGS. As shown in FIG. 2, a resist that requires a very large amount and requires complicated processing is used twice, and a polishing step is also essential. Usually, this process is repeated several to ten and several times to form a multilayer,
Since the production of the multilayer wiring board is very complicated and takes a long time, the cost becomes extremely high.

Further, since a metal pillar for a via is first formed and then a resin is applied around the pillar to form an insulating layer, the adhesion between the via and the surrounding insulating layer is inferior. Or the metal constituting the via may diffuse into the surrounding insulating layer, and the insulating function of the insulating layer may be greatly reduced.

In the second method shown in FIG. 4, a through-hole is formed in the second insulating layer without using a resist layer for forming a via, as compared with the first method, and this through-hole is formed. Since the via is formed by filling with metal by electrolytic plating, the process is somewhat simplified. Even so, since the formation of the via and the formation of the conductor pattern and the land are performed in separate steps, the number of steps is still large. Further, in this method, a step is easily formed near the boundary between the upper surface of the metal filled in the through hole and the adjacent insulating layer as shown in FIG. It has been pointed out that adhesion between the metal filled in the through hole and the insulating layer is poor.

Japanese Patent Application Laid-Open No. 7-79078 discloses a method for manufacturing a multilayer wiring board free from the above-mentioned disadvantages. The method described in this publication will be described with reference to FIG. FIG.
In the method described in JP-A-7-79078, a second insulating layer 2 is provided on a first insulating layer (insulating substrate) 1 having a conductor pattern 4 and a land 5 formed on the surface. Is formed, and through holes are formed in the insulating layer 2 so that the lands 5 are exposed [FIG. 5 (a)]. As shown, the through hole is tapered so that the diameter decreases from the upper surface of the insulating layer 2 to the land portion 5.

Next, a thin metal layer 6 is formed on the surface of the insulating layer 2 including the through holes by sputtering [FIG. 5 (b)]. Thereafter, a resist layer 17 having a pattern corresponding to the wiring pattern is formed by forming a resist layer and patterning by exposure and development. This resist layer is patterned so that the through hole of the first insulating layer and the periphery thereof are exposed [FIG. 5 (c)].

Thereafter, power is supplied from the metal layer 6 to perform electroplating, and the exposed portions of the metal layer 6 (that is, the cavities of the resist pattern and the insides of the through holes) are filled with metals 7 'and 8'. Electroplating is performed until the lowest part of the formed metal layer is equal to or higher than the upper surface of the resist layer 17 [FIG. 5 (d)]. Next, the filled metal is flattened by polishing or the like, and its film thickness is adjusted [FIG. 5 (e)]. Finally, when the resist layer 17 is removed, and the metal layer 6 exposed by removing the resist layer is also removed, a via 7 penetrating through the second insulating layer 2 and having a land portion integrally formed thereon is formed. The conductor pattern 8 is the second insulating layer 2
[FIG. 5 (f)].

On this second insulating layer 2, FIG.
When the third insulating layer is formed by repeating the step (f), the via penetrating through the third insulating layer is placed on the land of the via 7 of the second insulating layer, and the vias vertically overlap. Figure 2
A multilayer wiring board similar to that shown in FIG. However, the via is not a columnar shape as shown in FIG. 2, but an inverted truncated conical shape having a tapered upper spread.

According to this method, since the via, the land portion thereon, and the conductor pattern of the same layer are formed simultaneously by one panel plating, the steps are simplified as compared with the method shown in FIGS. However, the method described in Japanese Patent Application Laid-Open No. 7-79078 is considered to be incapable of coping with a higher density required in the future for the following reasons.

First, the through-holes (and thus vias) formed in the insulating layer 2 are formed such that the diameter of the upper surface, which is the opening, is larger than that of the lower surface in order to completely fill the via with metal by electrolytic plating. It has a taper. Since a land portion having a larger diameter than the diameter of the large upper surface is formed on the via, the diameter of the land portion becomes extremely large, and there is a limit in increasing the density. If an attempt is made to reduce the diameter of the land, the diameter of the lower surface of the via becomes small, making it difficult to establish electrical connection with the land below, and lowering the reliability.

As shown in FIG. 4 (d), in the electrolytic plating step, a long plating time is required because a metal layer having a thickness much larger than a required film thickness is formed so as to rise above the upper surface of the resist layer. Further, after this, an unnecessary metal portion is removed by polishing or the like, and a step of flattening the metal layer and the resist layer is required, and the manufacturing process is still complicated. As the wiring density increases and the through-holes become finer, unnecessary metal parts become extremely fine, and it becomes difficult to remove and flatten unnecessary metal by polishing or the like. Difficult. Therefore, it is desirable that at least the wiring polishing step be unnecessary.

JP-A-9-116266 also discloses JP-A-7-116266.
A method for manufacturing a multilayer wiring board having tapered vias similar to the method described in 79078 is disclosed. However, a thin metal layer is formed only on the surface of the through-hole and its surroundings, and then the power is supplied and electrolytic plating is performed, so that the through-hole is filled with copper without using a resist pattern. This method is disclosed in Japanese Patent Application Laid-Open No. 7-7907 described above.
There is the same problem as the method described in Japanese Patent Publication No.

[0025]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a multi-layer wiring board which enables high-density wiring, has good adhesion between wiring and vias and an insulating layer, and is unlikely to cause a decrease in insulating properties of the insulating layer. And a manufacturing method with the simplified process.

More specifically, a cylindrical via, rather than a tapered via having a large upper surface, is formed by a method in which a flattening step such as polishing is not required at all, or at least a polishing step after forming a wiring is unnecessary. It is an object of the present invention to achieve the above object by forming.

[0027]

SUMMARY OF THE INVENTION The present inventor has proposed that, when electroless copper plating is performed on a through-hole for a via formed in an insulating layer and then electrolytic copper panel plating is performed using a copper sulfate plating bath of a specific composition, the through-hole is reduced. It has been found that even when the hole has a cylindrical shape without a taper, the through hole can be uniformly filled with copper, and a copper layer having a substantially flat and uniform thickness is formed on the insulating layer. By filling the vias with copper in this way, it is possible to manufacture a multilayer wiring board capable of increasing the density of wirings by a simplified process without requiring at least a wiring polishing step. The present invention is based on this finding, and includes various aspects as described below.

(1) A multilayer in which wiring layers are formed in multiple layers on an insulating substrate via an insulating resin layer between layers, and wiring layers of different layers are electrically connected by vias penetrating the insulating layer therebetween. In the wiring board, vias penetrating at least two adjacent insulating layers are vertically arranged in a line, each via has a cylindrical shape having no taper, and a land portion is provided on an upper portion thereof. A multilayer wiring board, wherein an upper land portion is integrally formed by plating.

In a preferred embodiment of the multilayer wiring board (1), the cylindrical via has an aspect ratio (height / diameter ratio) of 0.5.
2 and / or a diameter of 80 μm or less, the via, the land portion, and the wiring layer are formed by electroless copper plating and subsequent electrolytic copper plating, and the plating surface is flattened after electrolytic copper plating. I have not received it.

(2) A method for manufacturing a multilayer wiring board including the following steps.

Forming a first wiring layer including a land on the surface of the first insulating layer; forming a second insulating layer on the first insulating layer so as to cover the first wiring layer on the surface; Forming a layer from a resin; forming a non-tapered cylindrical through hole on the land of the second insulating layer so that the land of the first wiring layer is exposed; A step of coating the upper surface of the layer and the inner surface of the through hole with a metal thin film by electroless plating, and forming a resist layer on the upper surface of the metal thin film, exposing and developing a resist pattern in which at least the through hole and its periphery are exposed. Forming a resist pattern, filling the cavity of the resist pattern and the through hole of the second insulating layer with metal until the surface is flush with the plane of the resist layer without performing a planarization process only by electrolytic plating; The process of removing Removing the metal thin film exposed by removing the dist layer;

(3) A method for manufacturing a multilayer wiring board including the following steps.

Forming a first wiring layer including a land on the surface of the first insulating layer; forming a second insulating layer on the first insulating layer so as to cover the first wiring layer on the surface; Forming a layer, forming a cylindrical through-hole having no taper on the land of the second insulating layer so that the land of the first wiring layer is exposed, A step of coating the upper surface and the inner surface of the through hole with a metal thin film by electroless plating, and filling the through hole with a metal by electrolytic plating, and forming a metal layer having a substantially flat upper surface on the surface of the metal thin film. Forming a resist pattern on the metal layer by forming, exposing and developing a resist layer, forming a resist pattern covering the through hole and the periphery thereof; Removing the metal thin film thereunder; and Removing the resist layer.

[0034] (4) After the step, the method further includes a step of uniformly reducing the thickness of the metal layer formed in the step. (3)
The described method.

In a preferred embodiment of the method described in (2) to (4) above, the cylindrical through-hole formed in the step has an aspect ratio (depth / diameter ratio) of 0.5 to 2, and / or a diameter of 0.5 to 2.
80 μm or less. After the step, the method may further include a step of performing a roughening treatment on a surface of a portion including the through hole of the second insulating layer. Further, the electroless plating is an electroless copper plating, and the weight ratio of copper sulfate / sulfuric acid is 0.
It is preferable to use a copper sulfate plating bath of 33 or less.

(5) A multilayer wiring board in which wiring layers are formed in multiple layers on an insulating substrate via an insulating resin layer between layers, and wiring layers of different layers are electrically connected by vias penetrating the insulating layer. Wherein the via is formed by electrolytic plating using a copper sulfate plating bath having a weight ratio of copper sulfate / sulfuric acid of 0.33 or less, without performing a flattening process on a plating surface of a plating layer. , A method of manufacturing a multilayer wiring board.

In the present invention, "up" means a direction far from the substrate, and "down" means a direction close to the substrate. For example, the “upper surface” of a layer means the surface of the layer remote from the substrate, and the “lower surface” means the surface of the layer closer to the substrate.

In the present invention, “cylindrical shape without taper” or simply “cylindrical shape” means a cylindrical shape having the same diameter on the upper surface and the lower surface. A maximum deviation of about 10% is allowed.

[0039]

FIG. 6 shows the structure of a multilayer wiring board according to the present invention. In the drawing, 1, 2, and 3 are first, second, and third insulating layers, respectively, and the first insulating layer 1 may be an insulating substrate. Reference numerals 4, 8, and 12 are conductor patterns (wiring patterns), and reference numeral 5 is a land portion formed on the first insulating layer, which is connected to the conductor pattern 4. Reference numerals 7 and 10 denote vias penetrating the second and third insulating layers 2 and 3, respectively.
In each case, a land portion having a diameter larger than that of the via is formed integrally with the via. The conductor pattern 4 and the land 5 form a first wiring layer, the conductor pattern 8 and the land above the via 7 form a second wiring layer, and the conductor pattern 12 and the land above the via 10 form a land. A third wiring layer is formed. The vias 7 and the vias 10 are vertically arranged in one row. Although it is not clear from FIG. 6, the vias 7 and 10 are both formed by metal plating (that is, by panel plating) together with the land portions above them.

The multilayer wiring board according to the present invention shown in FIG.
Compared with the conventional structure shown in FIG. 2, the basic structure is the same, but the land portions above the vias 7 and 10 are
However, they are not formed separately from the vias but are formed integrally with the vias at the same time. Further, it differs from the multilayer wiring board described in JP-A-7-79078 shown in FIG. 5 in that the via has a cylindrical shape having no taper.

It is preferable that the cylindrical vias 7 and 10 have an aspect ratio (height / diameter ratio) of 0.5 to 2 and / or a diameter of 80 μm or less. Here, the height of the via means the height of the cylindrical body excluding the upper land portion (the larger-diameter portion formed on the upper insulating layer). When this requirement is satisfied, as will be described in detail later, even when the via has a cylindrical shape without taper, there is no internal cavity, the depression on the upper surface is minimized, and the upper surface is substantially flat. Vias can be formed by electrolytic panel plating using a specific copper sulfate plating bath. More preferably, the diameter of the via is not more than 60 μm,
The aspect ratio ranges from 0.67 to 2.

The electrolytic panel copper plating is performed after the electroless copper plating, as described later. Therefore, the via, the land on the via, and the conductor pattern located on the same layer as the land can be formed by electroless copper plating and subsequent electrolytic copper plating. Further, in the electrolytic copper plating, a plating layer having a substantially flat upper surface can be formed, and therefore, unlike the methods shown in FIGS. 3 and 5, the electrolytic copper plating surface does not need to be subjected to a flattening treatment such as polishing. .

Hereinafter, a method for manufacturing a multilayer wiring board according to the present invention will be described in detail. First, a first method shown in FIG. 7 will be described. A first wiring layer including a land portion is formed on the surface of the first insulating layer 1 [FIG. 7 (a)]. In the illustrated example, the first wiring layer includes a conductor pattern 4 and a land portion 5.

The first insulating layer 1 may be an insulating substrate, but may be another insulating layer (resin layer) formed on the insulating substrate. The insulating substrate may be a rigid type (glass reinforced type) such as glass-epoxy or glass-polyimide, a flexible type such as polyimide, or may be made of ceramic or metal. When the insulating layer 1 is a resin layer, it is preferable to form the insulating layer from a resin having good insulation properties (low relative dielectric constant) and good heat resistance. A typical example of a preferable resin is polyimide, but is not limited thereto.

The conductor pattern 4 and the land 5 on the first insulating layer may be formed by a conventional method. For example, when the first insulating layer 1 is an insulating substrate, if the insulating substrate is a copper-clad laminate in which copper foil has been previously adhered, the copper foil on the substrate surface is formed by a conventional photolithography technique using a resist. Thus, the conductor pattern 4 and the land portion 5 can be formed. Photolithography technology generally involves coating a resist layer → patterning the resist layer by exposure and development via a photomask →
The method includes a step of removing the exposed portion of the copper foil by removing the resist layer by etching and then removing the resist layer.

When a metal layer such as a copper foil is not formed on the surface of the insulating layer 1 in advance, a land portion or a conductor pattern is formed by a vapor phase method such as sputtering or CVD, or a wet method such as electrolytic plating. To form This wiring layer may be formed by forming a continuous metal layer and then patterning it in the same manner as described above, or by forming a metal layer in a predetermined pattern from the beginning, such as pattern plating. May be. The thickness of the first wiring layer (land portion and conductor pattern) is usually about 20 to 25 μm.

On the first insulating layer 1, the first wiring layer (that is, the conductor pattern 4 and the land 5) formed on the surface thereof
The second insulating layer 2 is formed of a resin so as to cover the first wiring layer, and a through-hole is formed on the land 5 of the second insulating layer so that the land 5 of the first wiring layer is exposed [FIG. (b)]. The thickness of this resin layer may be sufficient to insulate the lower and upper conductor patterns, and is usually in the range of about 30 to 50 μm.

The resin layer constituting the second insulating layer 2 can be formed by applying a resin liquid and drying or curing by heating. The application of the resin liquid can be performed by, for example, a roll coating method or a spin coating method. This resin layer 2 is also preferably a resin having good insulation and heat resistance. However, as described below, depending on the method of forming the through-hole, the resin needs to be photosensitive. What is necessary is just to select a resin kind according to a method.

A preferred resin when photosensitivity is not required is polyimide. When photosensitivity is required, for example, a photosensitive resin used as a photoresist, which has excellent insulating properties and is inert to an etching solution for removing metal, can be used. As such a photosensitive resin, a composition containing a compound having a functional group (e.g., an acryl group or a methacryl group) in a molecule that induces a polymerization (curing) reaction by an active energy ray such as light or an electron beam is used. Suitable are, for example, urethane acrylate, epoxy acrylate and aliphatic acrylate. Also, to improve adhesion, strength and elongation,
A mixture of a thermosetting resin, a thermoplastic resin, and an organic or inorganic filler can also be used.

The through hole formed in the second insulating layer 2 has a cylindrical shape without a taper. This through-hole, which will later become a via, preferably has a diameter of 80 μm or less and / or an aspect ratio of 0.5 to 2. This through-hole may be formed by photolithography when the second insulating layer is made of a photosensitive resin. When the resin constituting the second insulating layer has no photosensitivity, a through hole can be formed in the insulating layer by, for example, laser processing.

Next, a thin metal layer (metal thin film) 6 is formed on the entire upper surface of the second insulating layer 2 and the inner surface of the through hole by electroless plating [FIG. 7 (c)]. This metal thin film 6 is not only necessary for the power supply of the subsequent electrolytic panel plating, but also improves the adhesion between the electrolytic plating layer and the insulating layer, and prevents the metal from diffusing into the insulating layer during the electrolytic plating. It also serves as a barrier to prevent

Before the electroless plating, the surface of the insulating layer 2 may be roughened by an appropriate method in order to improve the adhesion between the metal thin film 6 and the insulating layer 2. The surface roughening of the insulating layer 2 can be achieved by, for example, treating with an aqueous solution of chromic acid and / or permanganic acid. This surface roughening is preferably performed so that the peel strength of the copper layer deposited thereon becomes 1 kg / cm ² or more.

The electroless plating for forming the metal thin film is preferably electroless copper plating, but other plating such as Ni plating is also possible. The electroless copper plating may be performed in the same manner as a method which has been frequently used for through-hole plating and the like. The thickness of the metal thin film 6 is generally 3 μm or less, but is preferably larger because the resistance in the next electrolytic plating becomes smaller and metal deposition becomes easier. For example
A thickness of about 0.5 to 2 μm is sufficient.

Next, a resist pattern 17 is formed on the flat surface of the metal thin film 6 according to a photolithography technique of forming a resist layer, exposing and developing [FIG.
(d)]. This resist pattern has a cavity corresponding to a predetermined wiring pattern. For example, the through hole of the insulating layer 2 and its surroundings are exposed as hollow portions of the resist pattern. That is, on the through hole of the insulating layer of the resist layer,
Since the land is also formed at the same time, a cavity having a diameter larger than that of the through hole is required. In addition, as shown in the illustrated example, a cavity for forming a conductor pattern for connection with a via formed in the through hole is formed in the resist layer near the through hole.

The type of resist used is not particularly limited, and may be a negative type or a positive type. Since there is a through hole below, it is preferable to form the resist layer by attaching a dry film type resist onto the metal thin film 6 by thermocompression bonding or adhesion. It is not impossible to apply liquid resist, but then the through hole is filled with resist, and it is necessary to remove this part of the resist during development,
If the development time is prolonged and the resist in this portion is not completely removed, it may cause disconnection and corrosion of the wiring. Since the thickness of the resist layer is the thickness of the land portion and the wiring pattern portion, the thickness is preferably, for example, 15 to 20 μm.

Thereafter, power is supplied to the metal thin film 6 to perform electrolytic plating, and the metal is filled into the cavity of the resist layer and the through-hole of the second insulating layer 2. According to the present invention, this electrolytic plating is performed only by electrolytic plating without flattening the plating surface, until the metal is filled on the same plane as the upper surface of the resist layer [FIG. 7 (e)]. That is, the energization of the electrolytic plating is continued until the through holes are filled with the plating metal and the upper surface of the plating layer is flush with the upper surface of the resist layer.

According to the conventional method, panel plating in which metal is filled in the via-hole is not substantially flat on the plating surface, and a recess is formed in the center of the via.
As shown in FIG. 5D, the recess was formed so as to be raised from the resist layer so that the lowest portion of the recess was at least the same height as the upper surface of the resist layer. Thereafter, the raised portions are removed by a flattening process such as polishing to flatten the upper surfaces of the resist layer and the plating layer as shown in FIG. 5E, so that an extra polishing step is required. In the method shown in FIG. 4, there is no swelling, but as shown in FIG.
A step is easily formed at the boundary between the insulating layer and the metal layer, and there is a danger of disconnection.

In the present invention, a copper sulfate plating bath is used for electrolytic plating, the composition of the solution is adjusted to improve the uniformity of copper deposition, and the diameter and / or aspect ratio of the through-hole (via) is controlled. As a result, as in the conventional method shown in FIG. 5, even if the through-hole formed in the insulating layer 2 is not tapered, the upper surface is substantially flat and the through-hole is formed without forming a cavity inside. Metal (copper) by panel plating
It becomes possible to fill with. Thereby, the metal is filled evenly into the through hole of the insulating layer 2 and the cavity of the resist pattern to the same height as the upper surface of the resist layer without the need for a flattening process such as polishing.

Table 1 below shows the composition of the copper sulfate plating bath suitable for use in the present invention, together with the plating conditions.

[0060]

[Table 1]

The copper sulfate plating bath which has been generally used for the through-hole plating of the substrate and the electrolytic copper plating for filling the vias has a low copper concentration and a high sulfuric acid concentration in order to improve the uniform electrodeposition property. What is called a high throw bath. In the present invention, electrolytic plating is performed by using a copper sulfate plating bath in which the copper concentration is further reduced and the sulfuric acid concentration is increased in comparison with the conventional high throw bath, and the cathode current density is lowered.
The copper sulfate plating bath used has a copper sulfate / sulfuric acid weight ratio of 0.
33 or less. The lower limit of the weight ratio of copper sulfate / sulfuric acid is not particularly limited, but if it is lower than 0.15, the electroplating time required for filling the through holes becomes extremely long, and the copper concentration is too low, so that the management of the plating bath becomes difficult. Therefore, as shown in Table 1, it is preferable to be 0.15 or more. A more preferred copper sulfate / sulfuric acid weight ratio is in the range of 0.20 to 0.30.

The copper sulfate plating bath, in addition to the components shown,
It is common to generally include three additives: brighteners, carriers, and leveling agents. It is preferable that these additives are also contained in the copper sulfate plating bath used in the present invention. Examples of brighteners are sulfur-containing organic compounds such as thiourea and thiocarbamate. Examples of carriers are polyoxyalkylene glycols and the like. An example of a leveling agent is a polyamine. The amounts of these additives may be the same as in the conventional case.

By performing electrolytic copper plating under the above-described copper sulfate plating bath composition and plating conditions, the metal (copper) can be completely filled in the through-hole formed in the insulating layer as described below.

The conventional general copper sulfate plating bath can be used at a high current density, and the copper deposition rate is high, so that the energization time is short. However, when this plating bath is used for filling a metal in a through hole (forming a via), a cavity 20 is formed inside the through hole as shown in FIG. This is because the current during electrolytic plating concentrates on the upper edge 21 of the through hole,
This is because the copper deposition in this portion is greater than in the other portions, and the opening of the through hole is sealed with metal before the bottom of the through hole is filled with metal.

Since the plating solution is confined in the cavity 20, the solution gradually erodes the copper in the through-holes, thereby greatly impairing the reliability of the multilayer wiring board. Conventionally, as shown in FIG. 5, such a cavity is not formed by providing a taper having a diameter decreasing toward the lower side of the through hole and widening the opening of the through hole.

The copper sulfate plating bath suitable for use in the present invention has a low copper sulfate / sulfuric acid weight ratio, so that the uniformity of copper deposition is good. When this plating bath is used and the cathode current density is set lower as shown in Table 1 and electrolytic copper plating is performed at a relatively low temperature, the deposition rate of copper decreases, but the uniformity of deposition increases. Even if the shape of the through-hole is a cylindrical shape without a taper, it is possible to cleanly fill the through-hole with copper without forming a cavity.

However, when the aspect ratio (height / diameter ratio) of the through hole is reduced (that is, when the height is constant, the diameter is increased), although the cavity cannot be formed, as shown in FIG. A recess is formed at the center of the upper surface of the formed metal layer 7. If this dent is small (e.g.,
10% or less, especially 5% or less). When filling the through hole at the same position in the upper insulating layer with metal in the same manner, the metal is also filled in the recess, so the reliability of via connection is greatly reduced. I will not do it. Therefore, no flattening process is required.

On the other hand, if the depression becomes large, it becomes difficult to fill the depression at the time of filling the next upper metal layer.
As in the method shown in FIG. 5, it is necessary to deposit a metal to a thickness larger than a required thickness and to flatten the plated surface later by polishing or the like. Therefore, the number of steps increases and the plating time increases.

Therefore, as a result of examining this point, it was found that the aspect ratio of the through-hole (therefore, via) formed in the insulating layer was 0.5 or more and / or the diameter was 80 μm.
If it is below, a plating layer having a substantially flat upper surface is formed by electroplating using the above-mentioned copper sulfate plating bath without generating a large dent that requires a flattening treatment such as polishing. It has been found. Here, “substantially flat” means that the size of the dent is the depth of the through hole (= the height of the via).
It means less than 10%.

The upper limit of the aspect ratio of the through hole (via) is 2
It is. If the diameter is smaller than this, the opening of the through hole is too small, and it is difficult to uniformly fill the metal by electrolytic plating. A more preferable shape of the through hole (via) has an aspect ratio of 0.67 to 2 and / or a diameter of 60 μm or less.
According to the invention, the diameter is thus less than 80 μm, especially 60 μm.
It is possible to reliably form a cylindrical via having a very small diameter of less than μm and having no taper, which is very advantageous for increasing the density of the multilayer wiring board.

Even if a step as shown in FIG. 4 (f) is formed at the edge of the metal layer (the boundary between the metal layer and the resist layer) when the through hole is filled with metal, the method of the present invention does not require a via. This step is formed only at the edge of the land because the land and the land above it are simultaneously filled and integrated. Therefore, this step does not cause disconnection, and the reliability of the connection is not impaired.

As described above, the metal is substantially flatly filled by electrolytic plating in the through-hole of the second insulating layer 2 and the cavity of the resist pattern 17 on the insulating layer, and then the resist layer is removed. Then, the metal thin film 6 formed by the electroless plating below appears, and the land portion of the via 7 and the conductor pattern 8 remain as a protruding portion [FIG. 7 (f)]. When the resist layer is a dry film type, the removal of the resist layer can be performed simply by mechanical peeling. When peeling is difficult, a chemical method using a chemical solution for dissolving the resist may be employed.

After that, it is exposed on the surface of the insulating layer 2.
When the metal thin film 6 formed by the electroless plating is removed, the via 7 penetrating the insulating layer 2 with the land 5 under the insulating layer 2 penetrates, and a land integrated with the via 7 is formed on the insulating layer 2. An intended wiring structure having the conductor pattern 8 formed thereon is obtained [FIG. 7 (g)]. The removal of the metal thin film can be performed by etching using an etching solution that dissolves copper (eg, an aqueous ferric chloride solution).

When the upper via is formed on the via 7 by repeating the steps of FIGS. 7B to 7G, the multilayer wiring board shown in FIG. 6 is obtained. Note that the filling of the through holes provided in the insulating layer can be performed by electroless plating instead of by electrolytic plating. In this case, the step of forming the metal thin film 6 by electroless plating shown in FIG. 7C is omitted, and the conditions of the electroless plating are changed to the conditions for the thick film plating, and the through hole of the insulating layer is removed. The metal is filled in the cavity of the resist pattern. However, it is quite difficult to form a plating layer having a substantially flat upper plating surface, and the plating adhesion is also inferior to the above method.

A second method for manufacturing a multilayer wiring board according to the present invention will be described with reference to FIG. As in the first method shown in FIG. 7, after forming a first wiring layer including a conductor pattern 4 and a land portion 5 on the surface of the first insulating layer 1, an insulating layer 2 is formed thereon, A cylindrical through hole is formed so that the land portion 5 is exposed [FIG. 10 (a)]. Next, the upper surface of the insulating layer 2 and the inner surface of the through hole are covered with a metal thin film 6 by electroless copper plating [FIG. 10 (b)]. So far, the first
Method is the same.

Thereafter, power is supplied to the metal thin film 6 to perform electrolytic copper plating. As a result, the metal (copper) is filled in the through holes formed in the insulating layer 2 and covered with the metal thin film, and the metal (copper) layer 16 is formed on the metal thin film on the upper surface of the insulating layer [ FIG. 10 (c)]. Electrolytic copper plating is performed by forming a metal layer having an appropriate thickness as a wiring layer on the metal thin film 6 on the surface of the insulating layer 2.
Repeat until 16 is formed.

This electrolytic copper plating is preferably performed at a relatively low temperature and a low cathode current density using a copper sulfate plating bath having a specific composition, as described in detail for the first method. For the shape of the through hole, the aspect ratio is preferably 0.5 to 2 and / or the diameter is 80 μm or less, more preferably the aspect ratio is 0.67 to
2. The diameter is 60 μm or less. Thereby, as described in connection with the first method, the metal can be filled neatly without forming a cavity in the through hole of the insulating layer 2 and the metal layer 16 having a substantially flat plating upper surface can be replaced with the insulating layer 2. Can be formed on the metal thin film 6 covering the metal.

Thereafter, in order to pattern the metal thin film 6 and the metal layer, a resist pattern is formed on the metal layer 16 by forming a resist layer and patterning by exposure and development.
17 is formed [FIG. 10 (d)]. This resist pattern 17
In contrast to the pattern shown in FIG. 7 (d) having a cavity corresponding to the wiring pattern, it has the same pattern as the wiring pattern.
Therefore, a resist pattern 17 having a larger diameter than the through hole is formed on the through hole of the insulating layer 2 so as to form a land.

Then, the unnecessary portion of the metal layer 16 not covered with the resist pattern and the metal thin film 6 thereunder are removed together by etching [FIG. 10 (e)]. Finally, the resist pattern 17 is removed. The via 7 and the land portion integrated with the via and the conductor pattern 8 filled with the above are completed on the insulating layer 2 [FIG. 10 (f)]. If the steps of FIGS. 10A to 10F are repeated to form a via just above the land of the via 7, the multilayer wiring board shown in FIG. 6 can be manufactured.

In the method shown in FIG. 10, the aspect ratio of the through hole formed in insulating layer 2 for forming a via is small.
In this case, when the electrolytic plating is performed until the through holes are completely filled with the metal, the thickness of the metal layer 16 formed on the surface of the insulating layer 2 becomes equal to the thickness desired for the wiring layer 8. May be too thick. In that case, as shown in FIG. 11, after the electrolytic plating, the thickness of the metal layer 16 is reduced by polishing or the like.

FIG. 11 (a) shows the state after electrolytic plating corresponding to FIG. 10 (c), but the thickness of the metal layer 16 formed by electrolytic plating is unnecessarily thick. . However,
Using the copper sulfate plating bath and plating conditions of the preferred composition described above, the plating upper surface is substantially flat. Therefore, after the electrolytic plating process, the entire plating surface is reduced by shaving the entire plating surface by an appropriate method such as mechanical polishing or chemical etching, and the thickness is reduced by an appropriate plating thickness as a land (for example, 15 to 20).
μm). This is not only the case where the fine wiring is thinned as in the conventional method shown in FIG. 5, but also the entire surface is thinned and the upper surface is flat, so that even when the thickness is reduced by polishing, it is easy. An etching method can also be adopted.

After adjusting the thickness of the metal layer 16 in this manner,
In the same manner as described for 10 (d) to (f), the metal layer 16 and the metal thin film 6 thereunder are patterned using a resist pattern [FIGS. 11 (b) to (d)]. A via 7 having a land on the top and a wiring pattern 8 are formed in the insulating layer 2.

[0083]

(Embodiment 1) In this embodiment, a via filling step in the method of manufacturing a multilayer wiring board according to the present invention shown in FIG. 7 (that is, the through hole of the insulating layer 2 shown in FIG. In the step of supplying the metal by electrolytic plating by supplying power to the cavity of the resist pattern 17 from the metal thin film 6 previously formed by electroless plating, the influence of various parameters on the metal filling property of electrolytic plating is examined.

A copper foil layer (18 μm thick) (insulating layer 1) of a 0.8 mm thick copper-clad glass cloth-polyimide insulating substrate was patterned by photolithography to form a wiring pattern 4 and a land shown in FIG. A wiring layer including the portion 5 was formed. The diameter of the land 5 was set to twice the predetermined via diameter.

A cresol novolak photosensitive resin was applied on the wiring layer of the substrate and baked at 140 ° C. to form an insulating layer 2 having a thickness of 60 μm from the substrate. Next, the substrate is exposed to ultraviolet light using a glass mask and developed using a predetermined developing solution, so that the land portion 5 is exposed to the insulating layer 2 so as to have a predetermined diameter within a range of 40 to 110 μm. A cylindrical through-hole was formed [FIG. 7 (b)]. After that, the surface including the through-hole portion of the insulating layer is first treated with an aqueous solution of permanganic acid to roughen the surface, and then subjected to electroless plating copper plating. Was coated with a copper thin film 6 having a thickness of 0.5 μm [FIG. 7 (c)].
Therefore, the via height h (FIG. 8) was 40 μm.

Next, a 20 μm-thick layer was placed on the copper thin film layer of the substrate.
m, and a resist pattern 17 having a cavity corresponding to the conductor pattern 4 and the land 5 on the substrate was formed by exposing and developing [FIG. 7 (d)]. )]. The cavity (depth: 20 μm) of this resist pattern and the through-hole (depth: 40 μm) of the insulating layer 2
m) was filled with copper by electrolytic plating using a copper sulfate plating bath [FIG. 7 (e)].

The copper sulfate plating bath used was a plating bath having the composition shown in the present invention in Table 1, wherein the weight ratio of copper sulfate / sulfuric acid was changed within the range of 0.1 to 0.5, and the chlorine ion was 50 mg / kg. L and contained brighteners, carriers and leveling agents as additives. The bath temperature was 20 ° C., and the cathode current density was 0.4 A / dm ² . The electrolytic plating was continued until the plating upper surface reached the height of the upper surface of the resist pattern 17. After the plating was completed, the depth of the recess (via recess) formed in the center of the plating upper surface was measured by cross-sectional observation (embedding and polishing the sample). The measurement results and the electrolytic plating time (via hole filling time) are shown in FIGS.

FIG. 12 is a graph showing the relationship between the via hole filling time (the plating time required for filling up to the upper surface of the resist pattern) and the weight ratio of copper sulfate / sulfuric acid when the diameter of the through hole is 80 μm. As can be seen, the larger the weight ratio of copper sulfate / sulfuric acid, the shorter the via hole filling time, which is advantageous. When the weight ratio is 0.15 or less, the plating time required for filling the via hole becomes extremely long, and the copper concentration is extremely low. Therefore, it is necessary to frequently supply copper, and it becomes difficult to control the plating bath. Therefore, this weight ratio is preferably set to 0.15 or more.

FIG. 13 is a graph showing the relationship between the weight ratio of copper sulfate / sulfuric acid and the recess of the via when the diameter of the through hole is 80 μm. As can be seen from this graph, contrary to FIG. 12, the smaller the weight ratio of copper sulfate / sulfuric acid is, the smaller the depression of the via is, which is advantageous. If this weight ratio exceeds 0.33, the depression of the via is 10% of the via height (40 μm).
μm, and the upper surface of the via (land portion) cannot be said to be substantially flat. When the dent is large like this,
A cavity as shown in FIG. 8 may be formed inside the via. Therefore, in order to perform a substantially flat filling that does not require polishing by electrolytic plating, the weight ratio of copper sulfate / sulfuric acid needs to be 0.33 or less.

FIG. 14 is a graph showing the relationship between via hole diameter and via dent when the weight ratio of copper sulfate / sulfuric acid in the copper sulfate plating bath was fixed at 0.25 and the diameter of the through hole (via hole) was varied. It is. As can be seen from this graph, when the diameter of the through-hole exceeds 80 μm and the aspect ratio becomes smaller than 0.5, the dent of the via increases rapidly and the height of the via increases.
Since the thickness exceeds 10% (= 4 μm) of (the thickness of the insulating layer), it is preferable that the diameter or the aspect ratio of the through-hole is not more than this. More preferably, the diameter of the through hole is
It is 60 μm or less (aspect ratio is 0.67 or less), so that the depression of the via becomes 5% or less (= 2 μm) of the via height. In addition, it is difficult to uniformly fill a deep through-hole having an aspect ratio exceeding 2 (that is, having a depth larger than the diameter) by the electrolytic plating method.

After filling the through hole of the insulating layer 2 and the cavity of the resist pattern with metal by electrolytic plating, the resist pattern was peeled off (FIG. 7 (f)).
When a 5 μm-thick copper thin film formed by electroless plating is removed by etching with an aqueous cupric chloride solution, a wiring pattern 8 and a land portion having a thickness of approximately 20 μm remain on the insulating layer 2 and polishing after plating is performed. Instead, a wiring layer including a target cylindrical via and a land integrally formed on the via was able to be formed [FIG. 7 (g)].

Example 2 In this example, an insulating layer and a wiring layer were formed on an insulating substrate in the order shown in FIGS.
The substrate used was the same as in Example 1. A conductor pattern 4 and a land portion 5 were formed on the surface of the substrate in the same manner as in Example 1, and then an insulating layer 2 was formed. A through hole having a diameter of 80 μm was formed so as to be exposed.

Next, a 2 μm-thick copper thin film was formed on the surface of the insulating layer 2 and the through-hole by electroless plating copper plating, and the through-hole was made of copper using a copper sulfate plating bath in the same manner as in Example 1. Filled. Copper sulfate of the used copper sulfate plating bath /
The weight ratio of sulfuric acid is 0.25 and the cathode current density is 1.0 A / d
m ² , bath temperature was 20 ° C. Under these electrolytic plating conditions,
About 5 hours of plating time was required to completely fill a through hole having a diameter of 80 μm and a depth of 40 μm. The plating upper surface after the electrolytic plating was substantially flat, and the dent of the plating surface at the upper part of the through hole was 10% or less of the depth of the through hole. Is about 60 μm, which is much thicker than the desired thickness of 20 μm
[FIG. 11 (a)].

Therefore, the thickness of the plating layer 16 was adjusted to 20 μm by mechanical polishing by buffing. Thereafter, using the same resist as in Example 1, the plating layer 16 and the copper thin film 6 thereunder are patterned to form a via 7 shown in FIG. 11 (f) and a land integrally formed on the via. A wiring layer including the same was formed.

[0095]

The multilayer wiring board of the present invention has a structure in which the upper layer via overlaps directly with the lower layer via, and the via has a cylindrical shape without taper, so that the area occupied by the wiring pattern on the substrate surface is small. The number of wirings can be reduced, and wiring can be formed with high density. In addition, vias and wiring layers are roughened on the surface of the insulating layer, if necessary, and then a metal thin film is formed by electroless plating and then formed by electrolytic plating. In addition, since the electroless plating layer serves as a barrier, the metal does not diffuse into the insulating layer during the electroplating, so that the insulating property of the insulating layer does not decrease.

According to the present invention, a via, a land portion above the via, and a conductor pattern of the same layer as the land portion are formed at one time. In addition, by appropriately selecting the copper sulfate plating bath composition and via shape used for electrolytic plating, even if the through-hole of the insulating layer for forming a via has a cylindrical shape without a taper, a cavity is formed in this through-hole. The metal can be filled uniformly without causing cracks, the plated top surface after plating is substantially flat, and the recess at the center of the via is 10% of the via height.
It can be suppressed below. Since such a fine dent can be filled when a via is formed thereon, it is not necessary to flatten the plating of the wiring portion above the via by polishing after electrolytic plating as in the related art. Therefore, the manufacturing process of the multilayer wiring board is greatly simplified, and the manufacturing cost can be reduced.

In the above-described second method, as shown in FIG. 11, depending on the shape of the through-hole, if electrolytic plating is performed until the through-hole is filled, the thickness of the plating layer becomes too large, and polishing is performed. However, unlike conventional polishing of only the wiring part, this is solid polishing of the entire surface of the substrate, so even fine wiring can be easily polished, and chemical etching must be performed. Therefore, the polishing step is facilitated.

[Brief description of the drawings]

FIG. 1 is a partial cross-sectional view schematically showing a conventional multilayer wiring board.

FIG. 2 is a partial cross-sectional view schematically showing another conventional multilayer wiring board.

FIG. 3 is a process chart schematically illustrating a method for manufacturing the conventional multilayer wiring board shown in FIG.

4 is a process chart schematically illustrating another method for manufacturing the conventional multilayer wiring board shown in FIG.

FIG. 5 is a process diagram schematically illustrating a conventional method for manufacturing a multilayer wiring board described in Japanese Patent Application Laid-Open No. 7-79078.

FIG. 6 is a partial cross-sectional view schematically showing a multilayer wiring board of the present invention.

FIG. 7 is a process chart schematically showing a method for manufacturing a multilayer wiring board of the present invention.

FIG. 8 is an explanatory diagram showing a situation in which a cavity is generated in a via.

FIG. 9 is an explanatory view showing a depression formed on a plating upper surface corresponding to a via central portion.

FIG. 10 is a process chart schematically showing another method for manufacturing a multilayer wiring board of the present invention.

11 is a process chart schematically showing a modification of the manufacturing method shown in FIG.

FIG. 12 is a graph showing a relationship between a via hole filling time in electrolytic plating using a copper sulfate plating bath and a copper sulfate / sulfuric acid weight ratio of the bath.

FIG. 13 is a graph showing the relationship between the recess depth of a via and the weight ratio of copper sulfate / sulfuric acid in the bath in electrolytic plating using a copper sulfate plating bath.

FIG. 14: Depression depth of via and diameter (aspect ratio) of via (through hole) in electrolytic plating using copper sulfate plating bath
6 is a graph showing a relationship with the graph.

[Explanation of symbols]

 1, 2, 3: Insulating layer; 4, 8, 12: Conductor pattern 5, 9, 13: Land portion; 6: Metal thin film 7, 10: Via 15, 17: Resist pattern 16: Metal layer 18, 19: Plating Layer 20: Hollow

Claims (12)

[Claims] 1. A multilayer wiring in which wiring layers are formed in multiple layers on an insulating substrate via an insulating resin layer between layers, and wiring layers of different layers are electrically connected by vias penetrating the insulating layer therebetween. In the substrate, vias penetrating at least two adjacent insulating layers are vertically arranged in a row, each via has a cylindrical shape having no taper, and a land portion is provided on an upper portion thereof. Wherein the land portion is integrally formed by plating. 2. An aspect ratio (height / height) of the cylindrical via.
2. The multilayer wiring board according to claim 1, wherein the diameter ratio is 0.5 to 2. 3. 3. The multilayer wiring board according to claim 1, wherein said cylindrical via has a diameter of 80 μm or less. 4. The method according to claim 1, wherein the via, the land, and the wiring layer are formed by electroless copper plating and subsequent electrolytic copper plating, and the plating surface has not been subjected to a flattening process after the electrolytic copper plating. 4. The multilayer wiring board according to any one of 3. 5. A method for manufacturing a multilayer wiring board, comprising the following steps. Forming a first wiring layer including a land on the surface of the first insulating layer; forming a resin on the first insulating layer so as to cover the first wiring layer on the surface; Forming a cylindrical through hole having no taper on the land portion of the second insulating layer so that the land portion of the first wiring layer is exposed; and an upper surface of the second insulating layer. And a step of coating the inner surface of the through hole with a metal thin film by electroless plating. On the upper surface of the metal thin film, forming a resist layer, exposing and developing a resist pattern exposing at least the through hole and its periphery. A step of filling the cavity of the resist pattern and the through-hole of the second insulating layer with a metal until it is flush with the plane of the resist layer without performing a planarization treatment only by electrolytic plating, and removing the resist layer Process and removal of resist layer Removing the exposed metal thin film. 6. A method for manufacturing a multilayer wiring board, comprising the following steps. Forming a first wiring layer including a land on the surface of the first insulating layer; forming a second insulating layer on the first insulating layer so as to cover the first wiring layer on the surface; Forming a cylindrical through hole having no taper on the land portion of the second insulating layer so that the land portion of the first wiring layer is exposed; A step of coating the inner surface of the hole with a metal thin film by electroless plating; a step of filling the through hole with a metal by electrolytic plating and forming a metal layer having a substantially flat upper surface on the surface of the metal thin film. Forming a resist pattern on the metal layer by forming a resist layer, exposing and developing, and forming a resist pattern covering the through-hole and the periphery thereof; Step of removing metal thin film and resist layer Removing. 7. The method of claim 6, further comprising, after the step, uniformly reducing the thickness of the metal layer formed in the step. 8. The method according to claim 5, wherein the cylindrical through hole formed in the step has an aspect ratio (depth / diameter ratio) of 0.5 to 2. 9. The method according to claim 5, wherein the diameter of the cylindrical through hole is 80 μm or less. 10. The method further comprises, after the step, a step of roughening the surface of a portion including the through hole of the second insulating layer.
The method according to any one of claims 5 to 9. 11. The method according to claim 5, wherein the electroless plating is electroless copper plating, and the electrolytic plating is performed using a copper sulfate plating bath having a weight ratio of copper sulfate / sulfuric acid of 0.33 or less. The method described in the section. 12. A multilayer wiring board in which wiring layers are formed in multiple layers on an insulating substrate via an insulating resin layer between layers, and wiring layers of different layers are electrically connected by vias penetrating the insulating layer. In the production, the via is formed by electrolytic plating using a copper sulfate plating bath having a weight ratio of copper sulfate / sulfuric acid of 0.33 or less, without performing a flattening process on a plating surface of a plating layer, A method for manufacturing a multilayer wiring board.