JPH11145403A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a non-defective one chip by a method, wherein a circuit in a chip is divided into a plurality of circuits for blocks, signal terminals of adjacent blocks are connected electrically on a semiconductor wafer, each block is detachably arranged, and the one chip is made capable of being constituted at an arbitrary place. SOLUTION: A circuit in a one chip is divided into two consisting of a function A block and a function B block. Signal terminals 2-1 to 2-6 are connected to pads 1-1 to 1-6 respectively, and the pads 1-1 to 1-6 are connected to pads 1-1' to 1-6', respectively. When the function A block malfunctions in a chip X, the function B block of the chip X and the function A block of another chip, which is located on the right side of the function B block, are used as a new chip Y. The content and the pad arrangement of the functional blocks of the chip Y and the chip X are all identical. Accordingly, a non-defective one chip can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit suitable as a large-scale semiconductor integrated circuit used for an information processing device and the like, and more particularly to a semiconductor integrated circuit having improved production yield improving means. .

[0002]

2. Description of the Related Art Japanese Unexamined Patent Publication No. Hei 5-136331 discloses a conventional semiconductor integrated circuit of this type. The semiconductor integrated circuit disclosed in this publication is configured as shown in FIGS.

FIG. 2 is a partial cross-sectional view showing a part of the semiconductor chip, and FIGS. 3A and 3B are schematic plan views of the semiconductor chip having the structure shown in FIG. 2 and 3, 3 and 8 are chips, 4, 9, and 17 are pads, 5 and 10 are insulating protective films, 6 is an ultrasonic bonding portion, 11 is a metal wire cutting portion, and 12 is a bump connection portion. . 13 to 16 are functional blocks, and 18 and 19 are metal wires.

As shown in FIGS. 2 and 3, this semiconductor integrated circuit is mainly composed of a plurality of functional blocks 13 to 16, and all input / outputs of each functional block are provided around a semiconductor chip. A pad 17 for electrically connecting to the outside of the chip is provided so that signals can be transmitted and received to and from the outside of the chip.

In this semiconductor integrated circuit, when a defect is found in a certain functional block in a test stage of a semiconductor chip,
The treatment is as follows. That is, a single chip 8 (non-defective product) of a functional block as shown in FIG. 3B, which is mirror-symmetric with the defective functional block, is prepared. The defective functional block is electrically cut inside the pad group, and the pad surface of the functional block unit chip 8 and the pad surface of the defective functional block are overlapped by utilizing the mirror symmetry of the functional block. Make an electrical connection.

Thus, in this semiconductor integrated circuit,
Since the defective functional block is complemented by the newly connected non-defective functional block unit chip, the production yield is improved.

[0007]

The above-mentioned conventional semiconductor integrated circuit has the following disadvantages. (A) A mirror-symmetric functional block unit chip is required. (B) A step of electrically cutting defective functional blocks in the semiconductor chip is required. (C) A step of electrically connecting non-defective mirror-symmetric functional block unit chips is required.

An object of the present invention is to significantly improve the production yield as compared with the case of a one-chip configuration, and eliminate the need for specially preparing a mirror-symmetrical functional block unit chip, and perform a good product without performing complicated operations. It is an object of the present invention to provide a semiconductor integrated circuit that can be implemented.

[0009]

In order to solve the above-mentioned problems, the present invention employs the following characteristic configuration. (1) In a semiconductor integrated circuit according to the present invention, a circuit in a chip is divided into a plurality of blocks to form blocks, signal terminals of adjacent blocks on a semiconductor wafer are electrically connected to each other, and a signal Are arranged in a detachable state, and it is possible to configure one chip at an arbitrary position.

(2) In the circuit described in the above (1), when one chip is formed at an arbitrary position, all pads used are the same as those before forming the one chip.

(3) In the circuit described in the above (1), when a defective block is present among a plurality of divided blocks on a semiconductor wafer, the circuit is shifted by the amount of the defective block. There is provided means for forming a new one chip.

(4) In the circuit described in (1), the circuit in the chip is divided into two parts on the semiconductor wafer and divided into blocks on the right and left sides.

(5) In the circuit described in the above (1), on a semiconductor wafer, a circuit in a chip is divided into upper, lower, left, and right and divided into four blocks.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIG. 1 is a plan view showing a main part of a semiconductor integrated circuit according to a first embodiment of the present invention. In FIG. 1, 1-1 to 1-6 and 1
-1 'to 1-6' are pads, and 2-1 to 2
-6 is a signal terminal.

As shown in FIG. 1, in a semiconductor chip of this embodiment, a circuit in one chip is composed of a block having a function A and a circuit having a function B.
Is divided into two blocks. For example, focusing on the function A block and the function B block of the chip X, the signal terminals 2-1 to 2-6 are connected to the pads 1-1 to 1-6, respectively. The pads 1-1 to 1-6 correspond to the pads 1-1 'to 1-
6 '. The terminal 2-7 in the function A block and the terminal 2-8 in the function B block are internally connected.

If the block of the function A in the chip X is defective, the block of the function B of the chip X and the block of the function A of another chip located on the right side thereof are used, and the new chip Y and the block of the function A are used. I do. Since the contents of the functional blocks and the arrangement of the pads to be used for the chips Y and X are all the same, one non-defective chip can be obtained.

Thus, in this embodiment, even if it is detected in one inspection step or the like that a defect exists in one functional block, if the adjacent functional blocks are non-defective, it may be recognized as a non-defective chip. As a result, the yield is much improved as compared with the normal one-chip configuration.

(Modifications) The semiconductor integrated circuit shown in the embodiment includes the following modifications. For example, a circuit in one chip can be divided into three or more to have a circuit configuration similar to that of the above embodiment, and a defective block exists in a plurality of divided blocks on a semiconductor wafer. In such a case, it is possible to provide a means for forming a new one chip by shifting by the defective block.

[0019]

According to the present invention, even if there is a defect in one functional block, if the adjacent functional blocks are non-defective, they can be handled as non-defective chips. Yield can be significantly improved, and there is no need to specially prepare a mirror-symmetrical function block unit chip, and electrical disconnection of defective function blocks in a semiconductor chip and electrical connection processing of non-defective function block unit chips can be performed. It is possible to provide a semiconductor integrated circuit that can be made non-defective without special treatment.

[Brief description of the drawings]

FIG. 1 is a diagram showing a main configuration of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a semiconductor integrated circuit according to a conventional example, and is a partial cross-sectional view showing a part of a semiconductor chip.

FIG. 3 is a diagram showing a configuration of a semiconductor integrated circuit according to a conventional example, and is a schematic plan view of a semiconductor chip having a structure shown in FIG. 2;

[Explanation of symbols]

 1-1 to 1-6, 1-1 'to 1-6' Pad 2-1 to 2-6 Signal Terminal 3.8 Chip 4, 9, 17 Pad 5, 10 Insulation Protective Film 6 Ultrasonic Bonding Location 11 Metal Line cutting part 12 Bump connection part 13-16 Function block 18, 19 Metal wire

Claims (5)

[Claims] A circuit in a semiconductor chip is divided into a plurality of blocks to form blocks, signal terminals of adjacent blocks on a semiconductor wafer are electrically connected to each other, and the blocks can be separated from each other. A semiconductor integrated circuit, wherein one chip can be configured at an arbitrary position. 2. The semiconductor integrated circuit according to claim 1, wherein when one chip is formed at an arbitrary position, all pads used are the same as those before forming said one chip. . 3. When a defective block is present among a plurality of divided blocks on a semiconductor wafer, a means for forming a new chip by shifting by the defective block is provided. Claim 1.
3. The semiconductor integrated circuit according to claim 1. 4. The semiconductor integrated circuit according to claim 1, wherein the circuit in the chip is divided into two parts on the semiconductor wafer and divided into left and right parts. 5. The semiconductor integrated circuit according to claim 1, wherein the circuit in the chip is divided into four parts vertically and horizontally on a semiconductor wafer to form a block.