JPH11143680A - Image display system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To update the image of another image display device even when one image display device fails. SOLUTION: Branching connectors 18, 20 and 22 are connected through connection cables 24, 26 and 28 to the output of a host computer 10 and FLCDs(ferroelectric liquid crystal display devices) 12, 14 and 16 are connected through the connection cables 30, 32 and 34 to the respective branching connectors 18, 20 and 22. The branching connectors 18, 20 and 22 output the AND of data reception preparation completion signals from a poststage and the data reception preparation completion signals from the connected FLCDs 12, 14 and 16 to a preceding stage. When the data reception preparation completion signals are not received for a fixed time, the host computer 10 supplies time-out signals to the branching connectors 18, 20 and 22. The branching connectors 18, 20 and 22 interrupt data supply to the poststage and fix signals to be ANDed with the data reception preparation completion signals from the connected FLCDs as 'H' when the data reception preparation completion signals from the poststage are 'L'.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an image display system, and more particularly, to an image display system using a plurality of display devices capable of self-holding a display state, such as a ferroelectric liquid crystal display device. .

[0002]

2. Description of the Related Art Generally, a display device such as a CRT and a liquid crystal display panel is used in a computer and other information processing systems to display information so as to be visually recognizable. Although the CRT has the advantages of easily obtaining high resolution and a large number of colors, it is large and requires a considerable size in the thickness direction, so it is difficult to reduce the size.
In addition, there is a problem that power consumption is extremely large. On the other hand,
The liquid crystal display panel has advantages that it can be basically manufactured thinly, is easily reduced in size and weight, and consumes less power.

A liquid crystal display panel includes a ferroelectric liquid crystal (FL).
C: Ferroe1tricLiquid Cry
display device (FLCD: F) using the liquid crystal cell of sta1)
LC-Dispay), and one of its features is that the liquid crystal cell has a display state preserving property against an applied electric field. That is, in the FLCD, the elongated FLC molecules in a sufficiently thin liquid crystal cell are oriented in a first stable state or a second stable state according to the direction of application of the electric field, and the respective alignment states are removed even when the applied electric field is removed. maintain. Due to such bistability of FLC molecules, FLCDs have memory properties. FLC
For details of the FLCD, see, for example, Japanese Patent Application No. 76/1987.
No. 357.

In driving an FLCD, unlike a CRT or another liquid crystal display device, apart from refresh driving of the entire display screen, partial rewriting driving for updating a display state of only a changed portion on the display screen is performed. Becomes effective.

In order to detect a changed portion on the display screen, for example, a write operation to a storage means for storing pixel information to be displayed is monitored, and rewriting is performed at an address where the write operation is performed. Flag may be set. This flag may be a pixel unit or a horizontal or vertical line unit.

Further, if an FLCD is used, it is easy to display different images on a plurality of FLCDs from one host computer. FIG. 6 shows a configuration example. In FIG. 6, reference numeral 110 denotes a host computer serving as an image source;
8, 120, 122 are branch connectors, 124, 126, 1
28, 130, 132 and 134 are connection cables.

[0007] The host computer 110 has an FLCD 1
One F for updating the display from 12, 114, 116
Along with ID numbers indicating LCDs 112, 114, and 116,
A horizontal line address to be updated on the FLCDs 112, 114, and 116 and image data for one line to be updated are output to the connection cable 124. Branch connector 1
18, 120 and 122 are ID numbers received from the previous stage,
The line address and the image data are output to the subsequent stage as they are, and when the ID number uniquely assigned to the received ID number matches the received line number, the input line address and the image data are transferred to the connection cables 130 and 13.
FLCDs 112, 114, and 116 connected by 2, 134
Output to The FLCDs 112, 114, and 116 display the image of the received image data on the corresponding line on the display area indicated by the line address in accordance with the line address and the image data of one line sent from the branch connectors 118, 120, and 122. Is displayed.

FIG. 7 is a timing chart for updating the line images of the FLDCs 114 and 116. Fig. 7 (1)
Is a signal on the connection cable 130, (2) is a signal on the connection cable 130, (3) is a signal on the connection cable 132, and (4) is a signal on the connection cable 13
4 show the respective signals. For example, the ID number of the FLCD 112 is “1” and the ID number of the FLCD 114 is “
2 ', the ID number of the FLCD 116 is'3'. FIG.
, The first data (ID1, LINE ADDRESS1, DATA) output by the host computer 110.
1) is for the FLCD 114, and the second data (ID2, LINE ADDRESS2, DATA)
2) is for the FLCD 116. That is, ID
1 indicates the ID number '2', and ID2 indicates the ID number '3'. In FIG. 7, the time delay in the branch connectors 118, 120 and 122 is ignored.

[0009] Each of the FLCDs 112, 114, 116 is sent to the host computer 110 by the FLCDs 112, 11
4, 116, a data reception preparation completion signal indicating whether preparation for reception of image data has been completed is transmitted. FIG.
FIG. 4 is a schematic block diagram of a part of the branching connectors 118, 120, and 122 for transmitting a data reception preparation completion signal to the host computer 110. Reference numeral 136 denotes a connector to which a connection cable on the front side (host computer 110 side) is connected, 138 denotes a connector to which a connection cable on the rear side is connected, and 140 denotes a connector to which the FLCD is connected. A data reception preparation completion signal from the FLCD connected to the connector 140 and a data reception preparation completion signal from the FLCD connected to the subsequent stage are signal lines 142 and 14, respectively.
4 to the AND circuit 146. The data reception ready signal indicates that data reception preparation is completed when it is "H", and indicates that data cannot be received when it is "L". The AND circuit 146 outputs the logical product of the two data reception preparation completion signals to the connector 136 via the signal line 148.
To supply. The signal line 144 is normally pulled up,
The signal line 144 of the last branch connector 130 is always “H”.
It has become.

In this manner, all the connected Fs
A signal indicating whether or not all of the LCDs 112, 114, and 116 have completed data reception is sent to the host computer 110.
Is transmitted to When receiving the data reception preparation completion signal from the nearest branch connector 118, the host computer 110 starts outputting image data. That is, the host computer 110 outputs the ID number, the line address, and the image data, and outputs the desired FLCDs 112, 114, 11
6 to display individual images. As described above, a plurality of FLCDs 112 and 11 are transmitted from one host computer 10.
4, 116 can display different images.

[0011]

In the conventional example, any one of the FLCDs 112, 114, 116 or the branch connector 11 is used.
If any of the FCLDs 112, 114, and 116 is broken or the power supply is turned off, or the connection cables 124 to 134 are disconnected or short-circuited, image display becomes impossible in all the FCLDs 112, 114, and 116.

In order to easily solve this problem, each F
Regardless of whether the LCDs 112, 114, and 116 are ready to receive data, the host computer 110
However, an ID number, a line address, and image data may be output periodically. At this time, the host computer 11
The time interval of the data output of 0 is determined by the FLCDs 112 and 11.
It is important that 4,116 be longer than the time required for data reception preparation. Generally, since the amount of image data becomes enormous, all the FLCDs 112, 114,
The fact that the host computer 110 does not output data even though 116 is ready to receive data is as follows.
The frequency of updating the display of the FLCDs 112, 114, and 116 is significantly reduced, resulting in a large negative display system.

The signal lines 142, 144, 14
In order to solve the problem that the cable 8 is fixed at "L", the connected branch-type connectors 118, 120, 1
22, the branch connector 118,
Although it is necessary to specify 120 and 122, the specification involves a work such as removing the branch connectors 118, 120 and 122 in order, and requires a large amount of labor.

An object of the present invention is to solve such a problem and to provide an image display system capable of displaying different images on each of a plurality of display devices with a simple configuration.

[0015]

An image display system according to the present invention comprises one image output device serving as an image source, a plurality of image display means having a display image holding function, and one image of the image output device. An image display system comprising: one or more branch connection units connected in series to an output port and branching and supplying image information to the plurality of image display units;
A time measuring means for measuring a time for which the image output device waits for a data reception preparation completion signal from a connected image display means; and a series of the branch connection when the time measured by the time measuring means exceeds a predetermined time. Control means for outputting a predetermined control signal to the means, each of the branch connection means includes a gate means for selectively supplying data from the preceding stage to the subsequent stage, and a data reception preparation completion signal from the subsequent stage. When the predetermined control signal is received in a state not indicating completion of data reception preparation, the gate means is closed to shut off data supply to the subsequent branch connection means, and a data reception preparation completion signal to the preceding stage is received. And a data changing / storing means for changing the data into a reception completed state.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a schematic block diagram of an embodiment of the present invention. 10 is a host computer serving as an image source, 12, 14, 16 are FLCDs, 18, 20, 22
Is a branch connector, and 24, 26, 28, 30, 32, and 34 are connection cables. The outer shape is the same as that of FIG. 6 showing the conventional example, but the functions of the host computer 10 and the branch connectors 18, 20, 22 are the same as those of the host computer 1 of FIG.
10 and the branch connectors 118, 120, 122 are completely different.

The host computer 10 includes a time measuring means and a time setting means, and branches a time-out signal indicating that the time measured by the time measuring means has become larger than the value set by the time setting means via the connection cable 24. It can be output to the connector 118 and thereafter. Obviously, the time measuring means and the time setting means can be realized by a known technique such as a timer function of the CPU of the host computer 10 and software.

FIG. 2 is a schematic block diagram of the branch connectors 18, 20, and 22. Reference numeral 36 denotes a connector to which a connection cable on the front stage (host computer 10 side) is connected.
Reference numeral 8 denotes a connector to which a connection cable on the subsequent stage is connected, and reference numeral 40 denotes a connector to which an FLCD is connected. A data reception preparation completion signal from the FLCD connected to the connector 40 flows on the signal line 42, and a data reception preparation completion signal from the FLCD connected to the subsequent stage flows on the signal line 44. Here, it is also assumed that the data reception preparation completion signal indicates completion of data reception preparation when it is “H”, and indicates that data cannot be received when it is “L”.

Reference numeral 46 denotes a data bus for carrying data (ID number, line address, and image data) from the preceding stage (host computer 10 or preceding branch connector 18, 20). It is assumed that Numeral 48 is a 1-bit signal line, and when "H", FL on which data on the data bus 46 is displayed and updated is updated.
Indicates that the address is a line address on CDs 12, 14, and 16. Numeral 50 is a 1-bit signal line, which when "H" indicates that the data on the data bus 46 is an ID number. Reference numeral 52 denotes a timeout signal line for transmitting a timeout signal from the host computer 10. Data bus 46 and signal lines 48-52 connect from connector 36 to connector 38 via gate circuit 54.

Reference numeral 56 denotes an ID set by an ID setting means (not shown) when the signal on the signal line 50 is "H".
This is an ID comparison circuit that compares the value (IDi) with the ID number on the data bus 46, and outputs "H" if they are equal, and outputs "L" if they are not equal. The comparison circuit 56 holds the output value until the next comparison.

Reference numeral 58 denotes a gate circuit which is controlled to be opened and closed by the output of the ID comparison circuit 56. When the output of the ID comparison circuit 56 is "H", a signal on the data bus 46 and a signal on the signal line 48 are transmitted. It is supplied to the connector 40.

Reference numeral 60 denotes a state change / storage circuit for storing the signal on the signal line 44, changing the storage value in accordance with the signal on the signal line 52, and outputting the changed value. The signal line 52 is at "H", and When the signal line 44 is "L", the signal to the AND circuit 62 is fixed to "H" and the gate circuit 54 is closed, otherwise, the signal on the signal line 44 is supplied to the AND circuit 62 as it is. Then, the gate circuit 54 is set in a passable state. The AND circuit 62 supplies the logical product of the output of the state change / storage circuit 60 and the signal line 42 (data reception preparation completion signal) from the connector 40 to the connector 36 via the signal line 64.

The operation of this embodiment will be described. FIG. 3 shows a timing chart of the present embodiment. Host computer 10
Determines the signal from the signal line 64, and starts outputting image data when it is 'H'. After the start, first the signal line 50
Is set to "H", and an ID number to be updated on the data bus 46 is output. Branch connector 18, 20, 2
The second ID comparison circuit 56 compares the ID number on the data bus 46 with the ID number set for itself. If the comparisons match, the data on data bus 46 and the signal on signal line 48 pass through gate circuit 58 until the next comparison and are provided to connector 40 (the FLCD connected to).

Next, the host computer 10 sets the signal line 50 to "L" and the signal line 48 to "H",
A line address to be updated is output on the data bus 46. This line address is stored in each branch connector 1
Of the 8, 20, and 22, the signals are supplied only to the FLCDs 12, 14, and 16 connected to the branch connectors 18, 20, and 22 determined to be equal in the previous comparison in the ID comparison circuit 56.

The FLCDs 12, 14, and 16 that have detected that the signal line 48 has become "H" take in the data on the data bus 46 as a line address, and are ready to receive the corresponding image data. The line 42 is set to "L" to indicate that a new line address cannot be obtained. In this state, the signal line 64 at each branch connector 18, 20, 22 becomes "L", and the host computer 10
Will be notified.

Subsequently, the host computer 10 sets the signal line 48 to "L" and outputs one line of image data on the data bus 46 as a data string. The FLCDs 12, 14, and 16 that have become able to receive the data take in the image data on the data bus 46, and
Display an image on the address line. After outputting the image data for one line, the host computer 10 waits for the signal line 64 to become “H”. On the other hand, the FLCDs 12, 14, and 16 during the display operation change the signal line 42 to 'H' after completion of display and after completion of preparation for receiving a new line address. This state is transmitted to the host computer 10 through each of the branch type connectors 18, 20, and 22. When all the FLCDs 12, 14, 16 are ready to receive,
The signal line 64 connected to the host computer 10
H 'is reached, and the host computer 10 restarts the above-described series of operations.

While the host computer 10 is waiting for the signal line 64 to go to the "H" level, any of the connected branch connectors 18, 20, and 22 is set to the "L" state even if one of the signal lines 42 is "L".
In this state, the signal line 64 connected to the host computer 10 remains at “L”, and the host computer 1
0 means that the next display update operation cannot be started.

Therefore, in the present embodiment, the host computer 10 starts time measurement by the time measuring means when the signal line 64 becomes "H" to start the display update operation and after the reset. That is, the time measuring means is the signal line 6
4 is reset to “H”, and time measurement is started from zero. When the time measured by the time measuring means is larger than the set value by the time setting means,
The host computer 10 outputs the signal “H” on the signal line 52.
Is output. In the branch connectors 18, 20, and 22, the signal on the signal line 52 is applied to the gate 54 and the state change storage circuit 60. In the state change / memory circuit 60, the signal line 52
H 'and the signal line 44 is'L', the signal to the AND circuit 62 is fixed to 'H' and the gate circuit 54 is closed, otherwise the signal on the signal line 44 is The signal is supplied to the AND circuit 62 as it is, so that the gate circuit 54 can be passed. Such a function can be realized by a circuit configuration as shown in FIG.

When any of the branch connectors 18, 20, 22, for example, the signal line 64 of the branch connector 22 is "L", the branch connector connected to the preceding stage of the branch connector 22 is connected. At 20, the signal on the signal line 52 is "H" and the signal on the signal line 44 is "L". As a result, in the branch connector 20, the state change / storage circuit 60 closes the gate circuit 54, interrupts the signal supply to the branch connector 22, and fixes the signal to the AND circuit 62 at “H”. . As a result, logically, the branch connector 22 (and the FLCD 1)
6) is removed. Since the branch connector 20 sets the signal line 64 to the branch connector 18 to “H” and is transmitted to the host computer 10 via the branch connector 18, the host computer 10 can start a new display update operation. And the display update of the FLCDs 12 and 14 can be continued.

FIG. 5 is a schematic block diagram showing another example of the structure of the branch connectors 18, 20, and 22. Two FCLCDs can be connected to the branch connector shown in FIG.
In response, two IDs are set by ID setting means (not shown).
Can be set.

Reference numeral 70 denotes a front stage (host computer 10
Side), a connector 72 is connected to the subsequent connection cable, and 74a and 74b are connectors connected to the FLCD. Signal line 7
6a and 76b have connectors 74a and 74b, respectively.
, A data reception preparation completion signal from the FLCD connected thereto flows on the signal line 78, and a data reception preparation completion signal flows from the FLCD connected to the subsequent stage. Here, it is also assumed that the data reception preparation completion signal indicates completion of data reception preparation when it is “H”, and indicates that data cannot be received when it is “L”.

Numeral 80 denotes a data bus for carrying data (ID number, line address and image data) from the preceding stage (host computer 10 or preceding branch connector 18, 20). ing.
Reference numeral 82 denotes a 1-bit signal line. When the signal line is at "H", the data on the data bus 80 is displayed and updated.
Indicates that the line address is on lines 14 and 16. 84
Is a 1-bit signal line.
Indicates that the data on the bus 80 is an ID number. The data bus 80 and the signal lines 82 and 84 are connected from the connector 70 to the connector 72 via the gate circuit 86.

When the signal on the signal line 84 is "H", 88a and 88b compare the ID values (IDa, IDb) set by the ID setting means (not shown) with the ID numbers on the data bus 80. The ID comparison circuit outputs 'H' when they are equal and outputs 'L' when they are not equal. I
The D comparison circuits 88a and 88b hold the output values until the next comparison.

90a and 90b are AND circuits 92a and 92
2b is a gate circuit that is controlled to be opened and closed by the outputs of the ID comparison circuits 88a and 88b. When the outputs of the AND circuits 92a and 92b are "H", the data bus 8
The signal on 0 and the signal on signal line 82 are supplied to connectors 74a and 74b, respectively.

Reference numeral 94 indicates that the signal on the signal line 84 is "H" and the data on the data bus 80 is "FFFFh".
(Hexadecimal number). In the configuration shown in FIG. 5, the ID number of the FLCD is' FFF
Fh 'is unavailable. Although the details will be described later, the output of the determination circuit 94 corresponds to the signal on the signal line 52 having the configuration shown in FIG.

96a, 96b and 96c store the signals of the signal lines 76a, 76b and 78, respectively.
Is a state change / storage circuit that changes and outputs a storage value in accordance with the output of the determination circuit 94. When the output of the determination circuit 94 is "H" and the signal lines 76a, 76b, and 78 are "L", The signal to the AND circuit 98 is fixed at "H" and a signal for closing the gate circuits 90a, 90b, 86 is output. Otherwise, the signal on the signal line 44 is supplied to the AND circuit 98 as it is. Gate circuits 90a, 90b,
86 is output. The control output to the gate circuits 90a and 90b is
a and 92b are applied to the gate circuits 90a and 90b.

The AND circuit 98 includes a state change / storage circuit 9
The logical product of the outputs of 6a, 96b and 96c is supplied to the connector 70 via the signal line 100.

After the signal line 100 connected to the host computer 10 has transitioned from "H" to "L" and remains at "L" for longer than the value set by the time setting means, the host computer 1- , The signal line 84 is set to “H”, and the data “FFFFh” is output on the data bus 80. The determination circuit 94 detects this and notifies the state change / storage circuits 96a, 96b and 96c. Status change /
The storage circuits 96a, 96b, 96c are connected to the signal lines 76a, 7
If 6b and 78 are "L", the output to the AND circuit 98 is fixed at "H" and "L" is output to the AND circuits 92a and 92b and the gate circuit 86. As a result, the gate circuit 86 is closed, and the subsequent-stage branch connector and the FLCD connected thereto are logically disconnected. When “L” is applied to the AND circuits 92a and 92b from the ID comparison circuits 88a and 88b, the gate circuit 90
a and 90b are closed to shut off signal supply to the FLCD connected to the connectors 74a and 74b.

By such an operation, the signal on the signal line 100 is forcibly switched from "L" to "H" after a certain period of time, and the host computer 10 can start a new display update operation. The FLCD 1 before the branch connectors 18, 20, and 22 in which the signal line 100 could not be set to “H”.
2, 14 can continue the display update. Further, signal line 1
000 could not be set to 'H'
22 is a FL connected to the branch connectors 18, 20, 22
If the data reception ready signals (signal lines 76a, 76b) from the CDs 12, 14, 16 do not become "H", the display updates of the FLCDs 12, 14, 16 except for the corresponding FLCDs 12, 14, 16 are also made. It can be continued.

[0041]

As can be easily understood from the above description, according to the present invention, when the reception preparation completion signal from any one of the plurality of image display means does not indicate the completion of preparation, However, it is possible to update and display the image display means at an earlier stage, and it is possible to easily specify a portion where the preparation for reception has not been completed.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of an embodiment of the present invention.

FIG. 2 is a schematic configuration block diagram of branch connectors 18, 20, and 22 of the present embodiment.

FIG. 3 is a timing chart of the present embodiment.

FIG. 4 is a schematic configuration block diagram of a state change / storage circuit 60.

FIG. 5 is a schematic block diagram of a modified example of the branch connectors 18, 20, and 22;

FIG. 6 is a schematic block diagram of a conventional example.

FIG. 7 is a timing chart of a conventional example.

FIG. 8 shows a conventional branch connector 118, 120, 122.
FIG. 2 is a schematic configuration block diagram of FIG.

[Explanation of symbols]

10: Host computer 12, 14, 16: FLCD 18, 20, 22: Branch connector 24, 26, 28, 30, 32, 34: Connection cable 36, 38, 40: Connector 42, 44: Signal line (data reception) (Preparation completion signal) 46: data bus 48, 50: signal line 52: timeout signal line 54: gate circuit 56: ID comparison circuit 58: gate circuit 60: state change / storage circuit 62: AND circuit 64: signal line (data reception) 70, 72, 74a, 74b: connectors 76a, 76b, 78: signal line (data reception ready signal) 80: data bus 82, 84: signal line 86: gate circuit 88a, 88b: ID comparison circuit 90a , 90b: Gate circuit 92a, 92b: AND circuit 94: Judgment circuit 96a, 96b, 96: State change / notation Circuit 98: AND circuit 100: Signal line (data reception preparation completion signal) 110: Host computer 112, 114, 116: FLCD 118, 120, 122: Branch connector 124, 126, 128, 130, 132, 134: Connection cable 136, 138, 140: connectors 142, 144: signal line 146: AND circuit 148: signal line

Claims (1)

[Claims] 1. An image output device serving as an image source, a plurality of image display units having a display image holding function,
An image display system comprising one or more branch connection units connected in series to one image output port of the image output device and branching and supplying image information to the plurality of image display units, wherein the image output device is A time measuring means for measuring a time for waiting for a data reception preparation completion signal from the image display means to be connected; and a predetermined control for a series of the branch connecting means when the time measured by the time measuring means exceeds a predetermined time. Control signal output means for outputting a signal, wherein each branch connection means selectively supplies data from the preceding stage to the subsequent stage, and a data reception preparation completion signal from the subsequent stage indicates completion of data reception preparation. In the state not shown,
Receiving the predetermined control signal, the gate means is closed to shut off data supply to the subsequent branch connection means, and to change the data reception preparation completion signal to the preceding stage to the reception completed state. And an image display system.