JPH11138417A - Dresser for semiconductor substrate abrasive cloth and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a dresser, capable of removing the blinding of an abrasive cloth, stabilizing a polishing speed and manufacturing a semiconductor with high quality and yield. SOLUTION: A dresser for an abrasive cloth used in the polishing process of a semiconductor substrate into a plane shape comprises one type of hard abrasive grain selected out of cubic system boron nitride, boron carbide, silicon nitride or aluminum oxide, is brazed in a single layer on a supporting member formed of metal and/or alloy by using alloy with a melting point of 600 degrees C to 1400 degrees C containing 1-30 wt.% one type selected out of titanium, chrome or zirconium. Preferably, the hard abrasive grain is 30 μm or more and 300 μm or less in diameter. The supporting member is formed of ferrite based stanless steel with the hard abrasive grain brazed only on the single side.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dresser used to remove clogging of a polishing pad and foreign matter in a polishing process for planarizing a semiconductor substrate.

[0002]

2. Description of the Related Art In polishing a wafer, a polishing method is required which ensures a polishing rate and does not cause defects such as mechanical distortion. In the conventional mechanical polishing method, it is possible to secure the polishing rate by increasing the particle size of the abrasive grains and the polishing load. However, various defects are caused by the polishing, and it has been impossible to secure both the polishing rate and the material to be polished without defects. Therefore, chemical and mechanical planarization (CMP: Chemical Mechanical Pl
A polishing method called anarization was devised. In this method, a chemical polishing action is superimposed on a mechanical polishing action so that a polishing speed can be ensured and a material to be polished has no defect. CMP is widely used in the finish polishing process of silicon wafers, which requires both the securing of the polishing rate and the fact that the material to be polished is defect-free. In recent years, it has become necessary to polish the surface of a wafer or a semiconductor substrate having a conductor / dielectric layer formed on the surface of the wafer at a predetermined stage of manufacturing an integrated circuit in accordance with high integration of devices. Was. Typically, this step is performed during the formation of various devices and integrated circuits on the wafer. In this polishing step, as in the case of the finish polishing step of the silicon wafer, it is necessary to ensure both the polishing rate and the defect-free state. By introducing the chemical slurry, CMP is performed on the semiconductor surface to provide a higher polishing removal rate and defect-freeness. In general, a CMP process involves holding and rotating a thin, planar semiconductor material against a wet polishing surface under controlled pressure and temperature.

As an example of the CMP process, for example, 5 to 3
Caustic soda, silica particles having a particle size of about
A polishing slurry made of a chemical slurry suspended in an alkaline solution such as ammonia or an amine to a pH of about 9 to 12 and a polyurethane resin is used. At the time of polishing, the semiconductor substrate is brought into contact with the polishing cloth and rotated relatively while the chemical slurry is being spread, thereby performing the polishing. As a dressing method of the polishing cloth, clogging and foreign substances inside the polishing cloth are removed by brushing using a diamond electrodeposition grindstone or a brush while flowing water or a chemical slurry on the polishing cloth.

[0004] The dresser used in the CMP process is essentially different from conventional tools used in cutting and grinding in the following points. Even if a small amount of abrasive particles fall off with a cutting tool,
If other abrasive grains remain on the new surface after the abrasive grains fall off, the cutting performance will not decrease, whereas with a CMP dresser, the dropped abrasive grains will damage the surface of the polishing pad or semiconductor substrate. It is a point that even a small amount is not allowed. Also,
Since it is a wet type and used at a low rotation speed, the heat resistance and extreme wear resistance required for a cutting tool are not required. As a conventional tool in which the removal of abrasive grains is a problem, there is a cutting tool in which relatively large single abrasive grains (generally, a diameter of about 1 mm or more) are joined to a metal holding material. However, it differs from the dresser used in the CMP process in the following points. In a conventional cutting tool, a relatively large abrasive grain (generally, a diameter of about 1 mm or more) is joined by a single grain, whereas C
The dresser used in the MP process has relatively small (30 to 300 μm in diameter) abrasive grains bonded in a single layer in a planar manner. In addition, the dresser used in the CMP process is wet and used at a low rotation speed, so that the heat resistance and extreme abrasion resistance required for the cutting tool are not required.

[0005]

In a conventional dressing method for a polishing cloth, dressing is performed using a grindstone in which diamond particles are nickel-electrodeposited. Nickel electrodeposition has been widely used because it can be relatively easily applied to metal support members. However, the bonding strength with diamond is not sufficient, and diamond particles are often dropped or lost, causing scratches on the polishing pad or semiconductor substrate. For this reason, there has been a demand for a dresser in which diamond grains do not fall off.

Accordingly, an object of the present invention is to provide a dresser capable of minimizing scratches in dressing a polishing pad, having a high yield, and obtaining a stable polishing rate. Further, it aims at cost reduction by using other less expensive hard abrasive grains without using diamond as abrasive grains.

[0007]

According to the present invention, at least one selected from the group consisting of titanium, chromium and zirconium is used in an amount of 0.1 to 0.1.
One type of hard abrasive selected from cubic boron nitride, boron carbide, silicon carbide or aluminum oxide is used as a support member made of a metal and / or an alloy by using an alloy having a melting point of 600 ° C. to 1400 ° C. containing 30 wt%. , A single-layer brazed dresser for semiconductor substrate polishing cloths.

Preferably, the hard abrasive grains of the cubic boron nitride, boron carbide, silicon carbide or aluminum oxide have a diameter of 30 μm or more and 300 μm or less. Alternatively, there is provided a dresser for a polishing pad for a semiconductor substrate, wherein the support member is a ferritic stainless steel and hard abrasive grains are brazed only on one surface of the support member.

[0009] Further, a melting point of 0.1 to 30 wt% containing at least one selected from titanium, chromium and zirconium.
One type of hard abrasive grains selected from cubic boron nitride, boron carbide, silicon carbide or aluminum oxide is applied to a supporting member made of a metal and / or an alloy by using an alloy of 00 ° C to 1400 ° C in a single layer, vacuum. By brazing in the inside, a dresser for a polishing cloth used in the step of flattening and polishing a semiconductor substrate can be manufactured.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION A dresser for a polishing pad for a semiconductor substrate manufactured according to the present invention can minimize scratches caused by falling off of hard abrasive grains. as a result,
It is possible to manufacture a semiconductor substrate and a semiconductor with high processing accuracy and high yield. The joining between the hard abrasive grains and the brazing alloy significantly increases the bonding strength by forming a segregation layer of at least one metal selected from titanium, chromium or zirconium at the interface between the hard abrasive grains and the brazing alloy. Rise. The inventors of the present invention used brazing alloy with hard abrasive grains by using an alloy having a melting point of 600 ° C. to 1400 ° C. containing 0.1 to 30% by weight of at least one selected from titanium, chromium and zirconium as a brazing material. It was confirmed that a segregation layer of the metal was formed at the interface with the alloy. The formation of the segregation layer was confirmed by observing abrasive grains present on the cross section of the dresser with a scanning electron microscope and performing elemental analysis by energy dispersive X-ray spectroscopy attached to the scanning electron microscope.

[0011] The brazing material of the present invention comprises at least one selected from titanium, chromium and zirconium in an amount of 0.1 to 30 wt%.
Including. If the content is less than 0.1% by weight, no segregation layer of the metal is formed at the interface between the hard abrasive grains of cubic boron nitride, boron carbide, silicon carbide or aluminum oxide and the brazing alloy. Further, a content exceeding 30 wt% is not required.

The brazing alloy has a melting point of 600 ° C. to 1400 ° C.
Alloy at a brazing temperature below 600 ° C.
This is because the bonding strength cannot be obtained and the brazing temperature exceeding 1400 ° C. is not preferable because the hard abrasive grains or the supporting member are deteriorated. The thickness of the brazing alloy is suitably 0.2 to 1.5 times the grain size of the hard abrasive grains. If it is too thin, the bonding strength between the hard abrasive grains and the brazing alloy will be low, and if it is too thick, the brazing material and the support member will be easily separated.

The diameter of the hard abrasive grains is 30 μm or more and 300 μm
It is preferable to set the following. Sufficient polishing rate cannot be obtained with hard abrasive grains of less than 30 μm.
Within this range, a sufficient polishing rate can be obtained. Also, 3
Hard abrasive grains of less than 0 μm tend to agglomerate and tend to fall off when aggregated to form clusters,
This can cause scratches. With hard abrasive grains having a coarse grain size of more than 300 μm, stress concentration during polishing is large, and the hard abrasive grains are likely to fall off.

The support member is a ferritic stainless steel,
It is preferable that hard abrasive grains are brazed on only one side of the support member. Ferritic stainless steel is easy to process. Furthermore, by making one surface a surface on which hard abrasive grains are not brazed, for example, attachment and detachment by a magnet becomes possible, which can greatly contribute to improvement of work efficiency. The reason why the brazing condition is set to vacuum is to prevent oxidation of the coating made of titanium, zirconium, chromium, etc.
The reason why the temperature is set to 400 ° C. is that at a brazing temperature lower than 600 ° C., the brazing alloy does not melt and cannot be brazed. At a brazing temperature higher than 1400 ° C., the abrasive grains or the support member are deteriorated. This is because it is not preferable.

[0015]

[Embodiment 1] The dresser of the present invention has the dresser No. shown in Table 1 shown in FIGS. Hard abrasive grains such as cubic boron nitride, boron carbide, silicon carbide, and aluminum oxide having particle diameters as shown in Tables 2 to 10 were coated on a ferritic stainless steel substrate using ^-Five
A single layer was prepared by brazing at a brazing temperature shown in Table 1 for 30 minutes in a vacuum of Torr. Polishing experiments were performed on 400 semiconductor wafers using the obtained dresser. Dressing is 2 per polishing
Dressing for minutes. After polishing 400 wafers, the number of wafers on which scratches were generated due to the dropped diamond grains was examined. In addition, using the used polishing cloth, the wafer polishing rate after polishing for 2 hours and 20 hours was examined. Polishing of 400 wafers required about 20 hours. Table 1 shows the results. The wafer surface scratches and the grain size of the abrasive grains were observed with an electron microscope.

In the dresser according to the present invention, the occurrence of scratches on the wafer surface was significantly reduced as compared with the conventional dresser (comparative example), and the polishing rate was not reduced. As a result, semiconductor substrates with high throughput and high yield can be manufactured.

[0017]

Embodiment 2 The dresser of the present invention is shown in Table 2 shown in FIG. Hard abrasive grains such as cubic boron nitride, boron carbide, silicon carbide, and aluminum oxide having particle diameters as shown in Tables 2 to 5 were applied to a ferritic stainless steel substrate using ^A single layer was prepared by brazing at a brazing temperature shown in Table 2 for 30 minutes in a vacuum of ^-5 Torr. Using the dresser thus obtained, a polishing experiment was performed on 400 silicon wafers. The dressing was performed for 2 minutes every 10 times of polishing. After polishing 400 wafers, the number of wafers on which scratches were generated due to the dropped diamond grains was examined. Further, the wafer polishing rates after polishing for 3 hours and 30 hours were examined using the used polishing cloth. 40
Polishing of zero wafers required about 30 hours. Table 2 shows the results. The wafer surface scratches and the grain size of the abrasive grains were observed with an electron microscope.

In the dresser according to the present invention, the occurrence of scratches on the wafer surface was significantly reduced as compared with the conventional dresser (comparative example), and the polishing rate was not reduced. As a result, a high-throughput and high-yield silicon wafer can be manufactured.

[0019]

According to the present invention, it has become possible to minimize the scratches on the semiconductor substrate due to the removal of the abrasive grains. In addition, since the clogging of the polishing cloth can be removed and the surface of the polishing cloth can be maintained as it is when the polishing cloth is new, the polishing rate does not decrease with the use time of the polishing cloth, and semiconductor substrates with high processing accuracy can be manufactured with high yield. did it.

[Brief description of the drawings]

FIG. 1 is a table showing test results of Example 1.

FIG. 2 is a table showing test results of Example 1.

FIG. 3 is a table showing test results of Example 2.

Claims (4)

[Claims] 1. A melting point 600 containing 0.1 to 30% by weight of at least one selected from titanium, chromium and zirconium.
One type of hard abrasive selected from cubic boron nitride, boron carbide, silicon carbide, or aluminum oxide is formed on a support member made of a metal and / or an alloy by using an alloy having a temperature of 1 ° C to 1400 ° C. A dresser for a polishing pad for a semiconductor substrate, which is provided. 2. A hard abrasive made of cubic boron nitride, boron carbide, silicon carbide or aluminum oxide having a diameter of 30
The dresser of claim 1, wherein the dresser has a thickness of not less than μm and not more than 300 μm. 3. The support member is made of ferritic stainless steel, and one type of hard abrasive selected from cubic boron nitride, boron carbide, silicon carbide or aluminum oxide is brazed only on one surface of the support member. The dresser for a polishing pad for a semiconductor substrate according to claim 1. 4. A melting point 600 containing 0.1 to 30 wt% of at least one selected from titanium, chromium and zirconium.
One type of hard abrasive grains selected from cubic boron nitride, boron carbide, silicon carbide or aluminum oxide is applied to a support member made of a metal and / or an alloy, using a single-layer vacuum A method for producing a dresser for a polishing pad for a semiconductor substrate, comprising brazing at 600 to 1400 ° C.