JPH11136258A - Cell read synchronization control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To synchronize cell reading from both ATM switch systems quickly regardless of a band of an arrived cell group and its band change with respect to a cell read synchronization control method in the duplexed ATM switches. SOLUTION: In duplexed ATM switches 1 each provided with a common buffer memory 2 in which one of the buffer memories is made to an active system and the the is made to a standby system, cells arrived from an input highway 5 are stored to the common buffer memories of both the systems in parallel and then, extracted and only the cell extracted from the common buffer memory of the active system is sent to an output highway 6, after each ATM switch sets a pseudo cell as if the cells of a same amt. are stored respectively to the buffer memories of both the systems in the case of revising the system configuration (e.g. arranging storage area sections or the like), the cells and the pseudo cells during being stored in the common buffer memories of both the systems are synchronized and extracted and at the stage of ending the extraction of the cells and the pseudo cells of the same amt., the reading of cells from both the systems is synchronized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a duplicated ATM
The present invention relates to a cell read synchronization control method in a switch.

[0002]

FIG. 9 is a diagram illustrating a conventional ATM switch device, and FIG. 10 is a diagram illustrating a conventional cell readout synchronization control method.

The ATM switch device shown in FIG. 9 comprises a duplicated ATM switch (1) [each ATM switch (1) is a 0-system ATM switch (1 ₀ ) and a 1-system AT switch.
M switch (1 ₁ ), the same applies hereinafter). One of the switches (for example, the 0-system ATM switch (1 ₀ )) is operated as the active system, and the other (for example, the 1-system ATM switch (1 ₁ )) is operated. Stand by as a standby system.

Each ATM switch (1) is a common buffer type self-routing type switch, and has a common buffer memory (CBM) (2) and a write control unit (W
C) (3) and a read control unit (RC) (4).

[0005] The common buffer memory (CBM) (2)
IFO (First In First Out) storage device,
ATM cell (C) arriving from input highway (5)
Is stored under the control of the write control unit (WC) (3), extracted under the control of the read control unit (RC) (4), and sent to the output highway (6).

When an ATM cell (C) arrives from each input highway (5), a device (hereinafter referred to as a preceding device (X) (7)) provided in a preceding stage of the ATM switch becomes:
Path information (rt) necessary for causing the ATM switch (1) to execute a self-routing operation, and a quality control indicating a service quality class received by the ATM cell (C).
QCP class information (qcp) for identifying an lpath class [hereinafter referred to as a QCP class] and a cell header part (HD)
After that, cell validity information (ei _C ) indicating whether or not the cell is a valid cell, output highway (6), and cell information (i _C ) including QCP class information (qcp) are created, and ATM is generated.
Cell (C) is a common buffer memory (CBM) (2
₀ ) and (2 ₁ ), and the cell information (i _C ) is sent to the write control units (WC) (3 ₀ ) and (3 ₁ ) in both ATM switches (1 ₀ ) and (1 ₁ ). introduce.

The write control units (WC) (3 ₀ ) and (3)
_1), the preceding apparatus (X) (cell information transmitted from 7) (i _C) cells validity information in the (ei _C) were analyzed respectively, cell information (i _C) is extracted ATM cells ( C)
To the corresponding common buffer memory (CBM)
It is determined whether or not to write to (2 ₀ ) or (2 ₁ ), and if it is determined to write, the write address (wa)
To the corresponding common buffer memory (CBM)
(2 ₀ ) or (2 ₁ ) and the corresponding read control unit (RC) (4 ₀ ) or (4 ₁ ), and the issued write address (wa) is closed.
The issuing of the ATM cell (C) arriving thereafter is prevented.

Each common buffer memory (CBM) (2 ₀ )
And (2 ₁ ) write the ATM cell (C) transmitted from the preceding-stage device (X) (7) to the write control unit (WC) (3 ₀ ) or (3 ₁ ). At the address (wa).

Each of the read control units (RC) (4 ₀ ) and (4 ₁ ) has a corresponding write control unit (WC) (3).
₀₎ or (3: ₁₎ issued the write address from the (w
Based on a), each read address (ra) is issued to the corresponding common buffer memory (CBM) (2 ₀ ) or (2 ₁ ).

Each common buffer memory (CBM) (2 ₀ )
And (2 ₁ ) correspond to the corresponding read control units (R
C) The ATM cell (C) stored at the read address (ra) issued from (4 ₀ ) or (4 ₁ ) is extracted, respectively, and the active common buffer memory (CBM) is extracted.
(2 ₀ ) sends the extracted ATM cell (C) to the corresponding output highway (6).

Each of the read control units (RC) (4 ₀ ) and (4 ₁ ) has a corresponding common buffer memory (C
BM) After the ATM cells (C) have been extracted from (2 ₀ ) or (2 ₁ ), respectively, the read addresses (r
Each write address (wa) used to issue a) is returned to the corresponding write control unit (WC) (3 ₀ ) or (3 ₁ ).

Each of the write control units (WC) (3 ₀ ) and (3)
₁ ) is the corresponding read control unit (RC) (4 ₀ )
Alternatively, when the write address (wa) is returned from (4 ₁ ), the blockade of the returned write address (wa) is released, and the write address (wa) can be issued to the subsequently arriving ATM cell (C).

[0013] The ATM switch device is operating as described above.
The current ATM switch (1₀) Has failed
If the operation cannot be continued, the standby 1-system ATM switch is
Chi (1 ₁) Newly started operation as the active system,
ATM switch (1₀) Is disconnected from the ATM switch device
And undergo inspection and repair processing.

At the time of the system switching, the ATM cells (C) being stored in the 0-system common buffer memory (CBM) (2 ₀ ) and the 1-system common buffer memory (CBM)
If the group of ATM cells (C) stored in (2 ₁ ) completely matches, that is, if the reading of the ATM cells (C) from both systems is not synchronized, the output highway () is output before and after the system switching time. Discontinuities occur in the group of ATM cells (C) transmitted to 6).

However, the ATM switches (1 ₀ ) and (1 ₁ ) of both systems are connected to the AT switch arriving from the input highway (5).
The M cells (C) are independently stored in the common buffer memory (CBM) (2 ₀ ) or (2 ₁ ), and are independently stored in the common buffer memory (CBM) (2 ₀ ) or (2 ₁ ). The cells (C) being stored in both common buffer memories (CBM) (2 ₀ ) and (2 ₁ ) and the 1-system common buffer memory (CBM)
There is no guarantee that the ATM cell (C) group stored in (2 ₁ ) always matches.

In a conventional ATM switch device,
In consideration of the above points, as shown in FIG.
After the occurrence of the error, the ATM switches (1₀)and
(1 ₁ATM cell arriving from input highway (5)
(C) write operation and stored ATM cell (C)
Read operation is continued and both common buffer memories (CBM)
(2₀) And (2)₁ATM cell (C) stored in
Arriving at the time when there is nothing left, that is, from the input highway (5)
And both common buffer memories (CBM) (2₀)and
(2₁All ATM cells (C) stored in () are extracted and
At that point, the ATM cells (C) are read from both systems.
Had been synchronized.

Note that A arriving from the input highway (5)
If the number of TM cells (C) arriving per unit time (so-called band) is small and the variation of the arrival interval (so-called band change) is small, both common buffer memories (CBM) (2)
₀ ) and (2 ₁ ) often have no ATM cell (C) stored therein, but the ATM cell (C) arriving from the input highway (5) has a wide band and a large band change. Has a common buffer memory (CBM)
The ATM cells (C) stored in (2 ₀ ) and (2 ₁ ) hardly disappeared, and there was no chance of making the system switching executable.

[0018]

As is apparent from the above description, in the conventional ATM switch device, the opportunity to execute the system switching is provided by the common buffer memories (CBM) (2 ₀ ) and (2 ₀ ) of both systems. At the time when there is no ATM cell (C) stored in 2 ₁ ), when the ATM cell (C) arriving from the input highway (5) has a wide band and a large band change, it is common to both systems. The ATM cells (C) currently stored in the buffer memories (CBM) (2 ₀ ) and (2 ₁ ) hardly run out, and there is a problem that the opportunity to perform system switching is lost.

It is an object of the present invention to quickly synchronize cell reading from both systems irrespective of the band of the arriving cell group and band changes.

[0020]

FIG. 1 is a diagram illustrating the principle of the present invention. In FIG. 1, 1 is a duplicated ATM switch, 2 is a common buffer memory provided in each ATM switch (1), 5 is an input highway, and 6 is an output highway.

Each of the ATM switches (1) operates as a working system and the other as a standby system.
The cells arriving from the common buffer memories (2) of the two systems are once stored in parallel and extracted, and only the cells extracted from the common buffer memory (2) of the active system are sent to the output highway (6).

When changing the system configuration, each ATM switch (1) is provided with a common buffer memory (CBM) for both systems.
After setting pseudo cells so that the same amount of cells are stored in (2), the cells and pseudo cells stored in the common buffer memories (2) of both systems are synchronously extracted, and the common cells of both systems are extracted. When the same amount of cells and pseudo cells have been extracted from the buffer memory (2), cell reading from both systems is synchronized. [Regarding the Present Invention (Claim 1)] When each ATM switch (1) divides the storage area of each common buffer memory (2) into a plurality of storage areas in the same format, and changes the system configuration. In addition, it is considered that the pseudo cells are set so that the same storage area section of each common buffer memory (2) is all stored. [Regarding the Present Invention (Claim 2)] When the system configuration is changed, the active ATM switch (1 ₀ ) is used in common with the active system currently storing cells arriving from the input highway (5). a storage area segment of the buffer memory (2 ₀₎ and notifies the spare system ATM switch (1 _1), as the storage area segment which notifies the ATM switch (1 ₁₎ of the standby is being stored all the pseudo A cell is set, and the standby ATM switch (1 ₁ ) has the same storage area as that of the storage area section notified from the active ATM switch (1 ₀ ) of the standby common buffer memory (2 ₁ ). It is considered to set a pseudo cell so that all sections are being stored. [Regarding the Present Invention (Claim 3)] Further, each ATM switch (1) has an input highway (5) before extracting the same amount of cells and pseudo cells from each common buffer memory (2). After adding predetermined identification information to cells newly arriving from, and storing them in the common buffer memory (2), after the same amount of cells and pseudo cells have been extracted from each common buffer memory (2), It is considered that the cell to which the identification information is added can be read. [As above, the present invention (claim 4)] Accordingly, in the duplicated ATM switch, all the cells stored in the common buffer memories of both systems have been completely extracted, and the cells stored in each of the common buffer memories have been extracted. There is no need to eliminate them, and cell reading from both systems is quickly synchronized irrespective of the storage capacity of the common buffer memory and the band of the arriving cell and band changes.

[0023]

Embodiments of the present invention will be described below with reference to the drawings. 2 is a diagram illustrating an ATM switch device according to an embodiment of the present invention, FIG. 3 is a diagram illustrating a common buffer memory in FIG. 2, FIG. 4 is a diagram illustrating a read control unit in FIG. FIG. 5 is a diagram illustrating the read control register in FIG. 4, FIG. 6 is a diagram illustrating the read control table in FIG. 4, and FIG. 7 is a diagram illustrating the read control register and the update process of the read control table in FIG. FIG. 8 is a diagram exemplifying the read address issuing process in FIG. The same reference numerals indicate the same objects throughout the drawings.

The ATM switch device shown in FIG.
Instead of the common buffer memory (CBM) (2) and the read control unit (RC) (4) provided in the conventional ATM switch device shown in FIG. 9, a common buffer memory ( CBM) (2 _A ) and a read controller (RC) (4 _A ) having the configuration shown in FIG.
Are provided in both systems of ATM switch (1).

Common buffer memory (CBM) (2 _A )
As shown in FIG. 3, the entire storage area is divided into storage areas having a predetermined storage capacity (for example, 4 kilowords).

In FIG. 3, a level number (Lvn) [Lv0) in order from the head storage area
(Lv1),..., (LvN)], and the currently valid ATM cell (C) is assigned a level (Lv1) to (LvN).
It is being stored up to the storage area during 2).

Thereafter, a common buffer memory (CBM)
The amount of the called cell storage amount (n _C), also the buffer using the storage area up to the level (Lv2) being used by the cell storage amount (n _C) of (2 _A) into ATM cells in storage (C) This is referred to as a level (blv).

As shown in FIG. 4, the read control unit (RC) (4 _A ) includes the read address control unit (RAC) (4 _A ).
1) A read address buffer (ABMR) (42) and a QCP scheduler (QRS) (43) are provided.

Read address control unit (RAC) (41)
Are the write control unit (WC) (3) in the same system and the read address buffer unit (AB) in the read control unit (RC) (4 _A ).
MR) (42) and QCP scheduler (QRS)
It acts as an intermediary for exchanging various information with (43), and has a QCP scheduler (QRS) (4) in the same system.
Issue a read address (ra) to the common buffer memory (CBM) (2 _A ) in the same system in accordance with the instruction from 3);
The write address (wa) is returned to the write controller (WC) (3) in the same system.

Read address buffer section (ABMR)
(42) a read control register (RCR) provided for each QCP class for each output highway (6)
(421) and a read control table (RT) (422) provided for each output highway (6).

The read control table (RT) (422)
ATM cells (C) each having a configuration as shown in FIG. 5 and to be output to the corresponding output highway (6)
Common buffer memory (CBM) in the same system (2 _A )
Is stored in a chain format for each QCP class.

The read control register (RCR) (42)
1) each have a configuration as shown in FIG. 4 and have a common buffer memory (C
BM) (2 _A ), the start and end of the read control table (RT) (422) storing the read address (ra) of the ATM cell (C) to be extracted, and the pseudo cell amount (n _CD) ) Hold.

The QCP scheduler (QRS) (43)
Is a read band calculation counter [hereinafter referred to as a QCP counter (C), corresponding to each QCP class of each output highway (6).
NT) (431)].

In order to enable the ATM switches (1 ₀ ) and (1 ₁ ) to execute system switching, each QCP scheduler (QRS) in each read control unit (RC) (4 _A0 ) and (4 _A1 ) (43 ₀₎ and (43 ₁₎ QCP counter (CNT) (431 ₀₎ as specified in and (4
31 ₁ ) is initialized (that is, the count value is set to 0).
Therefore, in the present invention, enabling the system switching will be referred to as “scheduler reset” in the present invention.

Next, the read address control unit (RAC) (4)
The function 1) will be described. In the following description, only the inside of the 0-system ATM switch (1 ₀ ) will be mainly described, and the 1-system ATM switch (1 ₁ ) will be used only in cooperation with the 1-system ATM switch (1 ₁ ). And touch it.

Read address control unit (RAC) (41 ₀ )
Is a read control register (RCR) (42) provided in a read address buffer (ABMR) (42 ₀ ).
10 ₀ ) and the read control table (RT) (422 ₀ ) management function, and the read address (ra) or write to the common buffer memory (CBM) (2 _A0 ) and the write control unit (WC) (3 ₀ ). Address (wa) issue / return function, so-called "scheduler reset" function, and stored ATM
The cell (C) has a no-monitoring function.

First, the read control register (RCR) (421)
₀ ) and the management function of the read control table (RT) (422 ₀ ) will be described. Read address control unit (RA
C) (41 ₀ ) is a common buffer memory (CBM) (2
_{When the} ATM cell (C) is stored or extracted in ( _A0 ), the read control register (RCR) (42) provided in the read address buffer (ABMR) (42 ₀ ).
10 ₀ ) and the read control table (RT) (422 ₀ ) are updated.

First, the common buffer memory (CBM) (2
_{When the} ATM cell (C) is stored in _A0 ), the read address control unit (RAC) (41 ₀ ) writes the write address valid information (e) for each input highway (5).
_WA ), write address (wa), output destination information (displayed as an 8-bit bitmap in consideration of broadcasting), QC
P class information (qcp), broadcast identification information (c), a cell loss priority of (CLP), receives from the write controller (WC) (3 _0).

Read address control unit (RAC) (41 ₀ )
Is based on the received write address valid information (e _WA )
The validity of the write address (wa) is analyzed. If it is determined that the write address (wa) is valid, the output destination information is analyzed to identify the output highway (6), and the QCP class information (qcp) is analyzed. The class is recognized, and the corresponding read control register (RCR) (421 ₀ ) and read control table (R
T) (422 ₀ ) is updated.

The read control register (RCR) (421)
The update process ₀ ) differs as follows depending on the state before the update process. First, when the corresponding QCP class before the update process is empty (that is, when the cell storage amount (n _C ) of the ATM cell (C) having the corresponding QCP class is 0), the read control register (RCR) (421 ₀ ) The start address (a _P ) and the end address (a _L ) are updated to the write address (wa).

If the corresponding QCP class before the update processing is not empty (ie, if the cell storage amount (n _C ) of the ATM cell (C) having the corresponding QCP class is not 0), the read control before the update is performed. Register (RCR) (421 ₀ )
The end address searching (a _L), the read control table (RT) (422 ₀₎ of the tail address (a _L) for storing already follows the address (a _N) write address that received the (wa)
And the output destination information described above, and the next address (a
_N ), cell loss priority indication (cLp), broadcast identification information (c), scheduler reset arrival flag (ar
vf) is updated with the received information.

The read control register (RCR) (421)
₀), The ending address (a _L) Is the write address
(Wa). However, the so-called “scheduler reset”
To the effective write address (wa) arrived during
Is a read control register (RCR) (421).₀)
The arrival flag (arvf) during scheduler reset
Set to logic "1" and stored.

The above process is shown in FIG. Next, from the common buffer memory (CBM) (2 _A0 ) to the ATM
When the cell (C) extraction process is performed, the read address control unit (RAC) (41 ₀ ) sends the read instruction class information or invalidity from the QCP scheduler (QRS) (43 ₀ ) for each output highway (6). A cell output instruction is received.

The QCP scheduler (QRS) (43 ₀ )
, The read address control unit (RAC) (41 ₀ ) reads the read address (ra) of the corresponding QCP class corresponding to each output highway (6).
Output processing and the read control register (RCR) (42)
10 ₀ ) and the read control table (RT) (422 ₀ ) are updated.

The QCP scheduler (QRS) (43)
_{When the} invalid cell output instruction is notified from ( ₀ ), the read address valid information (e _RA ) is set to invalid, and the read control register (RCR) (421 ₀ ) is not accessed.

Regarding the read address (ra), the head address (a _P ) of the read control register (RCR) (421 ₀ ) at that time, broadcast identification information (c), cell loss priority display (cLp) Issue

However, the corresponding read control register (RCR)
The pseudo cell amount (n _CD ) stored in (421 ₀ ) is 0
If not, it is in a so-called "scheme scheduler reset", and in this case, it is added to the head address (a _P ) in the read control register (RCR) (421 ₀ ) to be issued as the read address (ra). The scheduler reset arrival flag (arvf) is referred to, and if the scheduler reset arrival flag (arvf) is not set to logic “1”, the read address (r
a) is issued, and 1 is subtracted from the pseudo cell amount (n _CD ).

If the scheduler reset arrival flag (arvf) is set to logic "1", the address cannot be issued and the read address (ra) is not issued, but the pseudo cell amount (n Subtract 1 from _CD ).

Read control register (RCR) (421 ₀ )
Update processing differs as follows depending on the state after the issuance of the read address (ra). First, when the cell storage amount (n _C ) becomes 0 by issuing the read address (ra), the update processing is not performed.

If the cell storage amount (n _C ) does not become 0 even after the issuance of the read address (ra), the next address (a _N ) and the cell loss priority display from the read control table (RT) (422 ₀ ). (CLp), the broadcast identification information (c) and the scheduler reset arrival flag (arvf) are extracted and set in the start address (a _P ) area and updated.

The above process is shown in FIG. next
QCP scheduler (QRS) (43₀Read finger from)
And the aforementioned read control register (RCR) (421)
₀) And read control table (RT) (422)₀)
New processing allows each output highway (6) at a certain cell time
Determines the storage address of the ATM cell (C) to be read.
This is issued as a read address (ra).
Issue to write control unit (WC) (3) for dress release
In this case, the read address valid information (e_RA) And the read address
Address (ra) and Q of the stored ATM cell (C).
CP class information (qcp) and the stored ATM cell
(C) cell loss priority indication (cLp) and broadcast identification information
(C) is the write control unit (WC) (3)₀) Issued on
Control unit (WC) (3)₀) The ad
Executes the release return process of the
(CBM) (2 _A), The read control unit
(RC) (4_A0) Is a write control unit (WC) (3)₀From)
Among the information of the write address (wa) to be received, the write address
(Wa) and write address valid information (e_WA) And just choose
And issues it together with the read address (ra).

In this state, when executing a so-called “scheduler reset”, the active write control unit (WC)
(3 ₀ ) transmits the scheduler reset start instruction (srs) and the buffer use level (blv) to the read control unit (RC) (4 _A0 ) of the active system.

In the active read control unit (RC) (4 _A0 ), the read address control unit (RAC) (41 ₀ )
When the write controller (WC) (3 ₀₎ for receiving a scheduler reset start instruction (srs), after holding the received buffer usage level (blv), the read control unit of the standby system (RC) (4 _A1) In response, a scheduler reset start instruction (srs) and a buffer use level (blv) are transmitted.

Next, the read control unit (RC) (4 _A0 ) refers to the QCP class information (qcp) for executing the scheduler reset notified from the write control unit (WC) (3 ₀ ), and Read control register (RCR) (421) of output highway (6) corresponding to each QCP class
Is set to the pseudo cell amount (n _CD ) in the above.

The set pseudo cell amount (n _CD ) corresponds to the storage capacity of the common buffer memory (CBM) (2 _A0 ) up to the held buffer use level (blv). FIG.
According to the common buffer memory (CBM) (2 _A ), the buffer use level (blv) is the level (Lv
2), and the pseudo cell amount (n _CD ) corresponds to three storage areas divided by the level (Lv).

Read control register (RCR) (421 ₀ )
Control unit (RC) which sets the number of pseudo cells (n _CD )
(4 _A0 ) is a QCP scheduler (QRS) (43 ₀ )
Of the QCP counter (CNT) (431 ₀ ) to be the target of the scheduler reset, and enters a reset processing state.

[0057] After entering the scheduler reset processing state, when the pseudo-cell volume (n _CD) = 0 in all the read control register set the pseudo cell amount _{(n CD) (RCR) (} 421 0), the read control Part (RC) (4 _A0 )
Releases the reset processing state, and the write control unit (WC)
(3 ₀ ) scheduler reset completion notification (sr
f) is returned.

On the other hand, the readout control unit (RC) of the standby system
In (4 _A1 ), the active read control unit (RC) (4)
Upon receiving the scheduler reset start instruction (srs) and the buffer use levels (blv) from _A0), after holding the received buffer usage level (blv), notifies the write control unit of the standby system (WC) (3 ₁₎ Refer to the QCP class information (qcp) that executes the scheduler reset to be performed, and check the QC of each output highway (6).
Read control register (RCR) (42) corresponding to P class
The pseudo cell amount (n _CD ) in 1) is set.

The pseudo cell amount (n _CD ) to be set is the same as the pseudo cell amount (n _CD ) set by the read control unit (RC) (4 _A0 ) of the active system. Read control register (RCR)
The read control unit (RC) (4 _A1 ) that has set the pseudo cell amount (n _CD ) in (421 ₁ ) is the QCP scheduler (QR
S) (43 ₁₎ within, to set a reset instruction QCP counter of interest scheduler reset (CNT) (431 _1), enters a reset processing state.

After entering the reset processing state, all the read control registers (RCR) in which the pseudo cell amount (n _CD ) is set.
When the pseudo cell amount (n _CD ) becomes equal to 0 in (421 ₁ ), the read control unit (RC) (4 _A1 ) cancels the reset processing state, and the standby write control unit (WC) (3 ₁ ). , A scheduler reset completion notification (srf) is returned.

The read address control unit (RAC) (41)
₀ ) has a no-monitoring function in order to recognize the presence / absence of an ATM cell (C) to be read from each QCP counter (CNT) (431 ₀ ) in the QCP scheduler (QRS) (43 ₀ ). I do.

A specific QCP counter (CNT) (431)
_{The zero} state at ₀ ) indicates that the ATM cell (C) to be read
Is determined by the fact that both the cell storage amount (n _C ) and the pseudo cell amount (n _CD ) are 0.

The fact that the cell storage amount (n _C ) is 0 means that the read address (ra) issued and the read control register (RCR) (421) are issued after the read address (ra) is issued.
_The determination is made based on a match with the end address (a _L ) in ( ₀ ).

The blank state is canceled when the effective write address (wa) is received and the start address (a _P ) and the end address (a _L ) are set in the subsequent cell time.

As is clear from the above description, the present invention
According to the embodiment, each common buffer memory (CBM) (2
_A0) And (2)_A1) Is divided into multiple levels,
When executing a reset, the current buffer is used.
Storage area up to level (blv) [ie, pseudo cell amount
(N_CD)] For the working system and the standby system at the same time.
By initiating a scheduler reset, of course
System and standby system common buffer memory (CBM)
(2_A0) And (2)_A1) Are synchronized and have no state
Allows the scheduler reset to be completed.
Cell buffer synchronous control method
(CBM) (2₀) And (2)₁) No storage space
There is no need to set the state, and the common buffer memory (CB
M) (2_A0) And (2) _A1) Storage capacity and arrive
Regardless of the band of ATM cell (C) and band change, schedule
The joule reset can be executed promptly.

FIGS. 2 to 8 are merely one embodiment of the present invention. For example, the configuration of the ATM switch is not limited to the illustrated one, and various other modifications may be considered. However, the effect of the present invention does not change in any case.

[0067]

As described above, according to the present invention, in the duplicated ATM switch, all the cells stored in the common buffer memories of both systems have been completely extracted, and the cells stored in each of the common buffer memories have been extracted. There is no need to eliminate them, and cell reading from both systems is quickly synchronized irrespective of the storage capacity of the common buffer memory and the band of the arriving cell and band changes.

[Brief description of the drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is an ATM switch device according to an embodiment of the present invention;

FIG. 3 shows a common buffer memory in FIG. 2;

FIG. 4 is a read control unit in FIG. 2;

FIG. 5 is a read control register in FIG. 4;

FIG. 6 is a read control table in FIG. 4;

7 is a process of updating a read control register and a read control table in FIG.

FIG. 8 is a read address issuing process in FIG. 4;

FIG. 9 shows a conventional ATM switch device.

FIG. 10 shows a conventional cell read synchronization control method.

[Explanation of symbols]

1 ATM switch 2, 2 _A shared buffer memory (CBM) 3 write controller (WC) 4,4 _A read controller (RC) 5 input highways 6 output highways 7 preceding apparatus (X) 41 read address controller (RAC ) 42 Read address buffer (ABMR) 43 QCP scheduler (QRS) 421 Read control register (RCR) 422 Read control table (RT) 431 QCP counter (CNT)

Claims (4)

[Claims] Claims: 1. Each comprises a common buffer memory,
One is operated as the active system and the other is operated as the standby system, and cells arriving from the input highway are stored in parallel in the common buffer memories of the two systems and then extracted, and only the cells extracted from the common buffer memory of the active system are extracted. Are output to the output highway. Each of the ATM switches, when changing the system configuration, stores pseudo cells such that the same amount of cells are stored in the common buffer memories of both systems. After the setting, the cells and the pseudo cells stored in the common buffer memories of the two systems are synchronously extracted, and at the stage where the same amount of cells and pseudo cells are respectively extracted from the common buffer memories of the two systems. And synchronizing the cell readings from the two systems. 2. Each of the ATM switches divides a storage area of each of the common buffer memories into a plurality of storage areas in the same format, and when changing the system configuration, stores the same storage area of each of the common buffer memories. 2. The method according to claim 1, wherein the pseudo cells are set such that all the area divisions are being stored. 3. The working ATM switch, when changing the system configuration, changes the storage area division of the working common buffer memory, which is currently storing cells arriving from the input highway, of the protection system. At the same time as notifying the ATM switch, the pseudo cell is set so that the storage area divisions notified to the standby ATM switch are all stored. 3. The cell read synchronization control method according to claim 2, wherein the pseudo cell is set such that all storage area sections identical to the storage area section notified from the active ATM switch are being stored. . 4. The ATM switch adds predetermined identification information to cells newly arriving from the input highway until the same amount of cells and pseudo cells have been extracted from the respective common buffer memories. And storing the cells in the common buffer memory, and after extracting the same amount of cells and pseudo cells from each of the common buffer memories, reading the cells to which the identification information is added can be read out. Item 2. The cell reading synchronization control method according to Item 1.