JPH11136204A - Demodulator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the demodulator that demodulates each incoming signal of a CATV by using a comparatively low sampling frequency, while effectively utilizing a frequency band. SOLUTION: A control section 15 selects a pass-band bj of a proper BPF and a sampling frequency fsk , in response to an incoming channel from a table 151 and gives an instruction to a clock generating section 14. The clock generation section 14 generates a clock, whose frequency is fsk and provides an output of it to an A/D converter 12 and a digital demodulation section 13 and sets the pass-band bj of the BPF. The BPF passes an incoming signal included in the set pass band bj . The A/D converter 12 applies under-sampling to the received analog signal at a sampling frequency fsk and provides an output of a digital signal. The digital demodulator section 13 applies digital signal processing to the output of the A/D converter 12 for obtaining demodulated data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a demodulator, and more particularly to a CATV (Cable) capable of two-way communication.
The present invention relates to a demodulator that selectively demodulates an arbitrary upstream signal from all upstream signals of Television.

[0002]

2. Description of the Related Art Conventionally, CATV has a service such as video-on-demand (hereinafter referred to as VOD) that requires bidirectional communication. Taking this VOD as an example, a slave station accommodated in a CATV system transmits an uplink signal to a center station using an upstream channel arranged in advance in the system in order to request video data to be viewed from a center station. Send to the station. Since a large number of slave stations are accommodated in the CATV system, the center station includes a demodulator for demodulating an uplink signal transmitted using a plurality of uplink channels. Here, FIG. 9 is a block diagram showing a first configuration example of a conventional demodulator (hereinafter, referred to as a first demodulator). In FIG. 9, the first demodulator is A
It includes a / D converter 91, a digital demodulation unit 92, and a clock generation unit 93.

Hereinafter, the operation of the first demodulator will be described. The A / D converter 91 samples the upstream signal input via the upstream channel using the clock input from the clock generation unit 93, and directly converts it into a digital signal. The frequency of this clock is the sampling frequency _fs1 , and the sampling frequency _fs1 is set to satisfy the sampling theorem. Here, FIG. 10 is a diagram for explaining the relationship between the frequency allocation of the uplink channel and the sampling frequency _fs1 . In FIG. 10, C
In the ATV system, a total of seven uplink channels are arranged in the uplink band so as not to overlap and be continuous on the frequency axis. As shown in FIG. 10, all uplink channels are:
In order to satisfy the sampling theorem, it must be arranged at a frequency lower than 1/2 of the sampling frequency _fs1 .

[0004] The digital demodulation section 92 performs digital signal processing on a digital signal input from the A / D converter 91 if the upstream channel is arranged at a frequency as shown in FIG. It extracts and demodulates an uplink signal input from a channel and outputs the demodulated data.

Japanese Patent Laid-Open Publication No. Hei 8-162990 discloses a second example of a conventional demodulator (hereinafter, referred to as a second demodulator). FIG. 11 is a block diagram showing a configuration of the second demodulator. In FIG.
The second demodulator is configured to perform undersampling while preventing the influence of aliasing noise, and includes an RF signal processing circuit 111 and an RF / IF frequency conversion circuit 112.
, IF signal processing circuit 113, A / D conversion circuit 114
, IF signal processing circuit 115, digital demodulation circuit 1
16 are provided.

FIG. 12 is a diagram for explaining the relationship between the frequency allocation of uplink channels that can be demodulated by the demodulator shown in FIG. 11 and the sampling frequency. In FIG. 12, a total of five uplink channels Ch _{1 to} Ch ₅ are arranged in the uplink band such that they do not overlap each other on the frequency axis. For the uplink channel, the sampling frequency is f _s2
Is not assigned to include a frequency that is an integral multiple of f _s2 / 2. In addition, according to the channel arrangement shown in FIG. 12, since the second demodulator performs undersampling, the uplink channels Ch ₃ , Ch ₄ and Ch _5
Are arranged at frequencies higher than 1/2 of the sampling frequency _fs2 . As is clear from comparison with the channels of FIGS. 12 and 10, the sampling frequency f _s2 is f _s1
Can be set lower.

The operation of the second demodulator when demodulating the uplink signal of the uplink channel Ch ₄ among the uplink channels shown in FIG. 12 will be described with reference to FIG. The IF signal processing circuit 113 includes a band-pass filter, and the band-pass filter has a pass band of f _s2 / 2 to f _s2 , as shown by a dotted line in FIG. This band-pass filter includes an RF signal processing circuit 111 and an R signal processing circuit.
Performing bandpass filtering on the uplink signal for which the predetermined processing has been performed by the F / IF frequency conversion circuit 112 extracts the uplink signal of the channel Ch ₃ and Ch ₄ are included from the bandwidth f _s2 / 2 to f _s2. A / D conversion circuit 11
4 performs A / D conversion at a sampling frequency f _s2 on the upstream signal extracted by the band-pass filter. Here, a position folded in half integer multiple of the frequency of the sampling frequency f _s2, appear folded Ch _3s and Ch _4s of the uplink signal of the uplink channel Ch ₃ and Ch _4. Further, since the f _s2 does not meet the sampling theorem, the in-band of f _s2 from f _s2 / 2, upstream channel Ch
_1, although Ch ₂ and Ch ₅ is supposed appears as aliasing, a band pass filter of the IF signal processing circuit 113 to prevent the influence of the aliasing noise from f _s2 / 2 into the band of f _s2 I have.

[0008] The A / D conversion circuit 114 converts the IF signal processing circuit 115 and the digital demodulation circuit 116 into A / D signals.
Digital signal processing is performed on the D-converted upstream signal. As a result, the uplink signal of the uplink channel Ch ₄ is demodulated, and as a result, demodulated data is obtained. As described above, the second demodulator can sample at a lower frequency than the first demodulator.

[0009]

By the way, the upstream channel of CATV is generally arranged at a frequency not exceeding 60 MHz. If the first demodulator attempts to guarantee digital demodulation for all such upstream signals, the sampling frequency f _s1 is 120 MHz.
It must be set to about z. However, at such a high frequency, there is a first problem that it is difficult to realize digital signal processing such as A / D conversion processing performed by the first demodulator.

When the second demodulator is applied, the upstream channel cannot be arranged at a frequency position that is an integral multiple of 1/2 of the sampling frequency _fs2 as described above. This is because the uplink signal of such an uplink channel is affected by aliasing and is not correctly digitally demodulated, and therefore cannot be arranged so as to be continuous on the frequency axis as shown in FIG. As a result, there is a second problem that the upstream band cannot be used effectively.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a demodulator capable of demodulating each CATV upstream signal using a relatively low sampling frequency while effectively utilizing the upstream band.

[0012]

Means for Solving the Problems and Effects of the Invention A first invention is a demodulation for demodulating a predetermined analog signal among all analog signals transmitted from outside through a plurality of channels arranged in advance. A channel selecting unit including a band-pass filter, selecting a channel from which the analog signal to be demodulated is transmitted, and passing the analog signal to be demodulated out of the plurality of channels; An A / D conversion unit that undersamples an analog signal passed by the unit and converts it into a digital signal; a digital demodulation unit that demodulates a digital signal output from the A / D conversion unit by digital signal processing;
A clock generator for generating clocks having different clock frequencies in accordance with the channel from which the analog signal to be demodulated is transmitted, wherein the A / D converter converts the frequency of the clock input from the clock generator to a sampling frequency. Is characterized by executing undersampling.

According to the first aspect, the A / D converter performs undersampling at a lower sampling frequency than the conventional one, so that it is easy to realize digital signal processing such as A / D conversion processing. become. Moreover, since the sampling frequency can be changed according to the channel through which the analog signal is transmitted, even if each channel is arranged so as to be continuous on the frequency axis,
The analog signal of each channel is correctly digitally demodulated without being affected by aliasing. by this,
The bandwidth can be used effectively.

In a second aspect based on the first aspect, each of the channels is configured by multiplexing first to n-th carriers (n is an integer of 2 or more) using a frequency division multiplexing method. And the digital demodulation unit includes first to first
An n-th digital demodulation unit;
Is characterized by demodulating a digital signal transmitted by the first to n-th carriers and output from the A / D converter.

According to the second aspect of the present invention, the signals frequency-division multiplexed by the n digital demodulation units can be demodulated in parallel. However, since only a single A / D converter 12 is provided, the circuit scale is extremely large. Does not grow.

In a third aspect based on the first or second aspect, the demodulator is a CATV (Cable Televis).
ion) It is characterized by being used in a system.

According to the third aspect, since the demodulator is used for CATV, it is possible to effectively use the band allocated to CATV.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) As described above, the demodulator according to the present invention is typically installed in a center station of a CATV system capable of bidirectional communication, and performs bandpass filtering, undersampling, and digital sampling. By executing the signal processing, an uplink signal (analog signal) transmitted through an arbitrary uplink channel is selectively demodulated among all the uplink channels used by the child station to access the center station.

Here, FIG. 1 shows the arrangement of uplink channels in the CATV system according to the first embodiment, the sampling frequency f _s1 and the sampling frequency f _s1 used when the demodulator according to the first embodiment performs undersampling. It is a figure for explaining _fs2 . In Figure 1, the CATV system, a total of seven up channel Ch _i (i is 1 ≦ i ≦
(Integers satisfying 7) are arranged so as not to overlap and be continuous on the frequency axis. Sampling frequency f _s1
The bandwidth of the upstream channel Ch ₃ is to contain the frequency f _s1 / 2, is set in the band of the uplink channel Ch _6. The sampling frequency f _s2 is set so that the band of the uplink channel Ch ₂ includes the frequency f _s2 / 2.
It is set within the band of ₅ . Further, the upstream channel C
The bands of h ₁ , Ch ₂ , Ch ₄ , Ch ₅ and Ch ₇ are:
The frequency is set so as not to include a frequency that is an integral multiple of f _s1 / 2. The bands of the uplink channels Ch ₃ and Ch ₆ are as follows:
The frequency is set so as not to include a frequency that is an integral multiple of f _s2 / 2. As will be described later in detail, the demodulator performs undersampling at the sampling frequency _fs1 or _fs2 . Therefore, according to the channel arrangement shown in FIG.
Some of the uplink channels Ch are assigned sampling frequencies f
It can be placed at a frequency higher than 1/2 of _s1 and _fs2 . In other words, the sampling frequencies f _s1 and f _s2 can be set relatively low, so that digital signal processing such as A / D conversion processing can be easily realized.

FIG. 2 is a block diagram showing the configuration of the demodulator according to the first embodiment of the present invention. 2, the demodulator includes a channel selection unit 11, an A / D converter 12, a digital demodulation unit 13, and a clock generation unit 1.
4 and a control unit 15.

The channel selection section 11 includes a variable pass band type band pass filter (hereinafter, referred to as a BPF). The channel selection unit 11 sets any of the BPF pass bands b _{1 to} b ₅ based on the instruction of the control unit 15,
Band b _j pass which the set (j is an integer satisfying 1 ≦ j ≦ 5) for selecting an uplink signal of the uplink channel Ch _i to be included in (analog signal). Here, the pass band b ₁ (0 <b
₁ <f _s1 / 2), as shown in FIG. 3 (a), including bandwidth of the uplink channel Ch ₁ and Ch _2. Further, the pass band _{b 2 (f s2 / 2 <} b 2 <f s2) , as shown in FIG. 3 (b), including bandwidth of the uplink channel Ch _3. Further, the pass band _{b 3 (f s1 / 2 <} b 3 <f s1) , as shown in FIG. 3 (a), including bandwidth of the uplink channel Ch ₄ and Ch _5. Further, the pass band _{b 4 (f s2 <b 4} <3f s2 / 2)
As shown in FIG. 3 (b), including bandwidth of the uplink channel Ch _6. Furthermore, the passband _{b 5 (f s1 <b 5} <3f
_s1 / 2), as shown in FIG. 3 (a), including bandwidth of the uplink channel Ch _7. The A / D converter 12 performs undersampling on the upstream signal (analog signal) output from the channel selection unit 11 at the clock frequency (sampling frequency) _fsk of the clock input from the clock generation unit 14, Convert to a signal.
Here, k is an integer satisfying 1 ≦ k ≦ 2. The digital demodulation unit 13 operates according to the clock input from the clock generation unit 14. Specifically, the digital demodulation unit 13 performs digital signal processing on the signal undersampled by the A / D converter 12, and extracts and outputs an uplink signal to be demodulated as demodulated data.

The clock generation unit 14 receives an instruction from the control unit 15
Based on the clock frequency f_s1Or f_s2With
By generating a lock, the A / D converter 12 and the digital
And outputs the result to the demodulation unit 13. Specifically, clock generation
Unit 14 includes a reference oscillator and a programmable frequency divider.
Contains. The frequency division ratio of this frequency divider is specified by the control unit 15.
Is set based on The frequency divider is set according to the set frequency division ratio.
Divide the clock output from the reference oscillator. to this
Therefore, the clock frequency f_s1Or f_s2Clock with
Is generated. The control unit 15 outputs the uplink signal to be demodulated.
Uplink channel Ch to be transmitted_iIs recognized in advance. control
The unit 15 transmits the recognized uplink channel Ch_iBased on
And the pass band b of the BPF_jAnd sampling cycle
Wave number f_sk151 having a combination of
(See FIG. 4). More specifically, the figure
As shown in FIG.
Channel Ch₁Is recognized, the pass band b₁
And the sampling frequency f_s1Is selected. Also up
Channel Ch_TwoIs also recognized, the uplink channel
Ch₁Is the same as Uplink channel Ch_ThreeIs recognized
Pass band b_TwoAnd the sampling frequency f_s2
Is selected. Uplink channel Ch_FourWhere is recognized
Pass band b _ThreeAnd the sampling frequency f_s1Is chosen
It is. Also, the uplink channel Ch_FiveWhere is recognized
In the case, the uplink channel Ch_FourIs the same as Uplink channel C
h₆Is recognized, the pass band b_FourAnd sump
Ring frequency f_s2Is selected. Uplink channel Ch₇Recognized
If known, passband b_FiveAnd sampling cycle
Wave number f_s1Is selected.

In a typical CATV system, a center station grants use of an uplink channel to a slave station, and the slave station transmits an upstream signal to the center station using the permitted uplink channel. Now, the center station sends an uplink channel C to the slave station.
Assume that gave permission to use the h _5. The following is a specific description of the operation of the demodulator shown in FIG. 2, among the uplink channels shown in FIG. 1, the operation for demodulating the uplink signal of the uplink channel Ch _5, with reference to FIGS. 5 and 6 Will be explained.

[0024] As described above, the control unit 15, since the center station gives permission to use the up channel to the slave station, previously knows the uplink channel Ch ₅ for transmitting an uplink signal to be demodulated. Control unit 15, from the table 151 for holding therein (see FIG. 4), remove the passband b ₃ and the sampling frequency f _s1 corresponding to the uplink channel Ch _5, instructs the channel selection unit 11 and the clock generator 14 . As a result, the channel selection unit 11 sets the pass band of the BPF included therein to the designated pass band b.
₃ (See Fig. 3 (a)). Further, the clock generator 14 generates a clock having the designated sampling frequency (clock frequency) f _s1 and outputs the clock to the A / D converter 12 and the digital demodulator 13.

The BPF of the channel selector 11 is a CATV
Of the uplink signals from the slave station of the system transmitted via the transmission path, by passing only the uplink signal and outputs included in the band b ₃ indicated by a dotted line in FIG. At this time, the spectrum of the output signal of the channel selector 11 includes the upstream signals of the upstream channels Ch ₄ and Ch ₅ as shown in FIG. The A / D converter 12 includes a channel selection unit 1
_{Undersampling} is performed on one output signal with the frequency of the clock input from the clock generation unit 14 as the sampling frequency _fs1 . As a result, A /
The D converter 12 converts an analog output signal of the channel selector 11 into a digital signal and outputs the digital signal. At this time, as shown in FIG. 6, the return signals Ch _4s and Ch _5s of the uplink signals of the uplink channels Ch ₄ and Ch ₅ appear at a frequency that is an integral multiple of f _s1 / 2. Also, band b
₃ , the return noise of the uplink signals of the uplink channels Ch ₁ , Ch ₂ and Ch ₇ should appear, but the BPF of the channel selector 11 prevents the return noise from affecting the band b ₃ . .

The digital demodulation unit 13 operates according to the clock (frequency f _s1 ) input from the clock generation unit 14, performs digital signal processing on the digital signal sampled by the A / D converter 12, and performs an up-channel Ch _5. Is extracted and demodulated.

As described above, in the demodulator according to the first embodiment, the control unit 15 controls the passband b of the appropriate BPF in accordance with the upstream channel for transmitting the upstream signal to be demodulated.
_j and the sampling frequency _fsk are selected from the table 151, and the channel selection unit 11 and the clock generation unit 1 are selected.
Instruct 4 By this instruction, the clock generation unit 14
Generates a clock having a clock frequency (sampling frequency) _fsk and outputs the clock to the A / D converter 12 and the digital demodulation unit 13.
_Is set. The BPF passes an upstream signal included in the set pass band b _j . The A / D converter 12 performs undersampling on the input analog signal (output signal of the BPF) at the sampling frequency _fsk . As a result, a digital signal is output from the A / D converter 12. The digital demodulation unit 13
By performing digital signal processing, the output digital signal of the A / D converter 12 is demodulated to obtain demodulated data.

Here, as apparent from FIG. 4, when demodulating the uplink signals of the uplink channels Ch ₃ and Ch ₆ , the sampling frequency f _s2 is selected. The reason will be described below. Now, the sampling frequency f _s1
Is used in undersampling the uplink signals of the uplink channels Ch ₃ and Ch ₆ . The bands occupied by the uplink channels Ch ₃ and Ch ₆ are as follows:
A frequency corresponding to an integer multiple of f _s1 / 2 is included. for that reason,
The upstream signals of these upstream channels Ch ₃ and Ch ₆ are represented by f
If you undersampling at _s1, their folding appears in the band in which the uplink channel Ch ₃ and Ch ₆ occupies. As a result, the upstream signals of these upstream channels Ch ₃ and Ch ₆ are adversely affected by this return,
Not demodulated correctly. Therefore, the sampling frequency is a frequency that is an integral multiple of the sampling frequency / 2 and the uplink channels Ch ₃ and Ch ₃
It must be chosen so that it is not included in band ₆ . As described above, by selecting a different sampling frequency according to the uplink channel, each uplink channel is configured as shown in FIG.
As shown in (1), they can be arranged so as to be continuous and non-overlapping on the frequency axis. Thereby, the upstream band (band in which the upstream channel is allocated) can be effectively used.

In the first embodiment, the BP is such that the channel selector 11 can arbitrarily change its frequency characteristic.
F. However, the channel selection unit 11 includes a plurality of band-pass filters having different frequency characteristics from each other and each frequency characteristic being fixed. A configuration may be included in which an appropriate band pass filter is switched by a switch from among the band pass filters. In addition, it has been described that the pass band of the BPF is a bandwidth that is a half of the sampling frequency.
However, the pass band of the BPF is only required to be able to pass even the uplink channel to be demodulated, and the BPF having the pass band for each uplink channel may be used for the number of channels. In the first embodiment, the clock generation unit 1
4 generates two kinds of sampling frequencies. However, the clock generation unit 14 may generate three or more types of sampling frequencies. Furthermore, in the first embodiment, it has been described that the programmable frequency divider divides the frequency of the clock oscillated from the reference oscillator to generate a plurality of types of clocks having different frequencies. However, such a clock is a PLL (Phase Locked) synchronized with an external clock.
Loop).

(Second Embodiment) Next, a demodulator according to a second embodiment of the present invention will be described. The second embodiment differs from the first embodiment in the following. Differs in that Apart from that, there is no difference between the two,
The description of the corresponding parts is omitted. First, the first difference will be described. FIG. 7 illustrates an uplink channel arrangement of the CATV system according to the second embodiment and sampling frequencies f _s1 and f _s2 used when the demodulator according to the second embodiment performs undersampling. FIG. The uplink channel arrangement shown in FIG. 7 is different from that shown in FIG.
The difference is that a carrier of a wave (n is an integer of 2 or more) is configured to be frequency-multiplexed. Since there are no other differences, the description of FIG. 7 corresponding to FIG. 1 will be omitted.

Next, the second difference will be described. FIG. 8 is a block diagram illustrating a configuration of the demodulator according to the second embodiment. The demodulator shown in FIG. 8 is different from the demodulator shown in FIG.
In that the digital demodulators 13 _{1 to} 13 _n are provided. Since there is no other difference, in the configuration of FIG. 8, components corresponding to those of FIG. 2 are denoted by the same reference numerals, and description thereof is omitted.

In the demodulator of FIG. 8, the output signal from the A / D converter 12 is branched into n (that is, the number of digital demodulators). The branched output signals are
It is input to the digital demodulator 13 ₁ to 13 _n of the n.
Digital demodulating section 13 ₁ to 13 _n of first through n operate in accordance with the clock inputted from the clock generator 14. Specifically, the digital demodulators 13 _{1 to} 13 _n
Digital signal processing is performed on the first to n-th carriers of the n-branch upstream signal (digital signal) output from the A / D converter 12 and extracted and output as first to n-th demodulated data.

As described above, by relatively lowering the sampling frequency, the output signal of a single A / D converter 12 can be easily distributed over a subsequent bus (not shown). Digital demodulation units 13 _{1 to} 13
_n can be connected in parallel to simultaneously demodulate the uplink signal of each carrier. As described above, since the demodulator includes only a single A / D converter 12, the circuit scale does not become extremely large.

[Brief description of the drawings]

FIG. 1 illustrates an uplink channel arrangement of the CATV system according to the first embodiment and sampling frequencies f _s1 and f _s2 used when the demodulator according to the first embodiment performs undersampling. FIG.

FIG. 2 is a block diagram illustrating a configuration of a demodulator according to the first embodiment of the present invention.

FIG. 3 is a BPF included in a channel selection unit 11 shown in FIG. 1;
FIG. 4 is a diagram for explaining a pass band b _j of a (band-pass filter).

FIG. 4 is a diagram showing a table 151 included in a control unit 151 shown in FIG. 1;

FIG. 5 shows an uplink channel C among the uplink channels shown in FIG.
It is a diagram for explaining the operation when demodulating the uplink signal h _5.

FIG. 6 shows an uplink channel C among the uplink channels shown in FIG.
It is a diagram for explaining the operation when demodulating the uplink signal h _5.

FIG. 7 illustrates an uplink channel arrangement of the CATV system according to the second embodiment and sampling frequencies f _s1 and f _s2 used when the demodulator according to the second embodiment performs undersampling. FIG.

FIG. 8 is a block diagram illustrating a configuration of a demodulator according to a second embodiment.

FIG. 9 is a block diagram illustrating a first configuration example of a conventional demodulator.

FIG. 10 is a diagram for explaining a relationship between an uplink channel frequency arrangement and a sampling frequency f _s1 .

FIG. 11 is a block diagram showing a configuration of a demodulator (second demodulator) disclosed in Japanese Patent Application Laid-Open No. 8-162990.

12 is a diagram for explaining a relationship between a frequency arrangement of uplink channels that can be demodulated by the demodulator shown in FIG. 11 and a sampling frequency.

Second demodulation SL shown in FIG. 13 FIG. 11 is, among the uplink channels shown in FIG. 12 is a diagram for explaining the operation when demodulating the uplink signal of the uplink channel Ch _4.

[Explanation of symbols]

11 channel selection unit 12 A / D converter 13, 13 _{1 to} 13 _n digital demodulation unit 14 clock generation unit 15 control unit

Claims (3)

[Claims] 1. A demodulator for demodulating a predetermined analog signal out of all analog signals transmitted from outside via a plurality of channels arranged in advance, the demodulator including a band-pass filter, Of the plurality of channels, a channel from which an analog signal to be demodulated is transmitted is selected, and a channel selection unit that allows the analog signal to be demodulated to pass, and an undersampling of the analog signal passed by the channel selection unit A / D to convert to digital signal
A converter, a digital demodulator for demodulating the digital signal output from the A / D converter by digital signal processing, and a clock having a different clock frequency according to the channel from which the analog signal to be demodulated is transmitted. A demodulator, comprising: a clock generation unit that generates the clock; and the A / D conversion unit performs the undersampling using a frequency of a clock input from the clock generation unit as a sampling frequency. 2. Each of the channels is configured by multiplexing first to n-th carriers (n is an integer of 2 or more) using a frequency division multiplexing method. A first to an n-th digital demodulation unit, wherein the first to the n-th demodulation units transmit digital signals transmitted by the first to n-th carriers and output from the A / D conversion unit. The demodulator according to claim 1, wherein demodulation is performed. 3. CATV (Cable Televis)
3. The demodulator according to claim 1, wherein the demodulator is used in an (ion) system.