JPH11136131A - A/d converter and its a/d conversion method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid an idle tone and also to prevent an added direct current component from being included in a digital signal output to be outputted, by adding the same direct current component to a positive phase signal and a reverse phase signal after converting an analog signal into the positive phase signal and the negative phase signal and performing A/D conversion afterward. SOLUTION: After an analog input signal is converted into a positive phase signal and a negative phase signal by an inverted amplifier circuit 5, a positive phase signal and a direct current component Vdc are added to it in an analog adder 6 and also, a negative phase signal and the component Vdc are added to it in an analog adder 7. These signals are outputted to a digital subtracted 4 after they are converted into a digital signal by a ΔΣ type A/D conversion circuit 1 and a ΔΣ type A/D conversion circuit 2. Because subtraction processing of an inputted signal is performed in the subtracter 4, a signal component of a digital output signal is canceled by the component Vdc that is added in a balancing circuit 3 and is not included in an output any more.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D (analog / digital) converter for converting an analog signal into a digital signal and a method of converting the same, and more particularly to a .DELTA..SIGMA.
The present invention relates to improvement in noise characteristics of a / D conversion circuit.

[0002]

2. Description of the Related Art As one of A / D converters, a ΔΣ type A
An A / D conversion device using a / D conversion circuit has been proposed. For example, there is an A / D conversion circuit as disclosed in Japanese Patent Application Laid-Open No. 2-126727. Hereinafter, an A / D conversion device using a conventional ΔΣ A / D conversion circuit will be described.

FIG. 5 is a block diagram showing a configuration of a conventional A / D converter. 50 is a ΔΣ type A / D conversion circuit, 5
1 is an analog subtractor, 52 is an integrator, 53 is a quantizer for quantizing an input signal to 1 bit, 54 is a D-type flip-flop (hereinafter, referred to as DFF), and 55 is a D / A converter.

FIG. 6 is a block diagram showing a configuration of the integrator 52. In FIG. 6, 56 is an analog adder, 57
Is a delay unit that delays by one sampling period. An input signal from the analog subtractor 51 is supplied to an analog adder 56.
The output signal is output to the quantizer 53 via the delay circuit 57, and is positively fed back to the analog adder 56 via the delay unit 57.
That is, the input signal is cumulatively added for each sampling period, and the transfer characteristic Hi (z) is represented by the Z function as shown in (Equation 1).

Hi (z) = 1 / (1−z ⁻¹ ) (1) where z = cos θ−j · sin θ j: imaginary unit The conventional A / D converter configured as described above The operation of the apparatus will be described below with reference to FIGS. The analog input signal is input to an integrator 52 via an analog subtractor 51, and is cumulatively added by an analog adder 56 in the integrator 52.
It is quantized into a binary (1 bit) digital signal of 1 and -1. The quantized digital signal is output as a digital output signal, is input to the D / A converter 55 via the DFF 54, and is converted into a binary (1 bit) analog signal of + Vt and -Vt. Thereafter, the signal is fed back to the analog subtractor 51.

When the analog input signal of the ΔΣ A / D conversion circuit 50 is X, the digital output signal is Y, and the quantization error generated by the quantizer 53 (the difference between the input and output of the quantizer 53) is Vqn. , And the relationship between the input and output is expressed by (Equation 2).

Y = X + (1−z ⁻¹ ) Vqn (Equation 2) As is apparent from (Equation 2), the digital output signal Y includes not only the analog input signal component X but also the quantization error Vqn. Although the term is included, the noise due to Vqn decreases as the frequency becomes lower because of multiplication by the first-order differential characteristic (1-z ^-1 ), and even if only one bit is quantized, a wide dynamic range is obtained in the low frequency region. Can be obtained.

In order to obtain a wider dynamic range, the sampling period is set shorter (the sampling frequency is higher) than the digital output signal to be obtained, and the A / D
The conversion may be performed and the output digitally processed to use only the low frequency region. For this reason, this method is also called an oversampling method, and is widely applied especially in the digital audio field.

[0009]

However, in the conventional configuration as described above, when a DC component (DC voltage) is added to an analog input signal, the digital output signal has a characteristic of having a periodicity. There is a problem that a specific frequency component (idle tone) appears in Vqn, which is noise (white) having no frequency characteristics.

The principle of occurrence of this problem will be briefly described with reference to FIG. FIG. 7 is a waveform diagram of an input signal and an output signal of the quantizer 53 of the ΔΣ A / D conversion circuit 50.

First, when a DC component Vdc is input to a ΔΣ A / D conversion circuit 50, the DC component Vdc is cumulatively added by an integrator 52 and input to a quantizer 53. When the input signal exceeds a predetermined threshold value, the quantizer 53 inverts the output signal and feeds it back to the analog subtractor 51, so that the input waveform of the quantizer 53 becomes a sawtooth wave as shown in FIG. , And the output waveform is a pulse train.

The pulse interval at this time has a fixed period determined by the ratio between the input DC component Vdc and the quantized output Vt, and the period t ₀ is represented by (Equation 3).

T ₀ = Ts × Vt / Vdc (Equation 3) where Vdc: DC component (DC voltage) Ts: sampling cycle Since a pulse train with a constant cycle t ₀ is obtained, a digital output signal is Noise at the fundamental frequency 1 / t ₀ and its integral multiple (harmonic) appears. This is generally called an idle tone. This idle tone does not appear unless there is a DC component in the input signal, but it is extremely difficult to completely remove the DC component from the analog input signal, and the DC component of the A / D converter circuit itself has a DC component. The effects are also difficult to avoid.

The simplest way to avoid this idle tone is to add the DC component Vdc so that the frequency of the idle tone determined by (Equation 3) is outside the desired signal band.

As described above, in the ΔΣ A / D conversion circuit,
Since a low frequency region in which a wide dynamic range can be obtained is used as a signal band, it is only necessary that the fundamental frequency 1 / t ₀ of the idle tone be higher than the upper limit frequency of this signal band.

However, if this means is simply used, the digital output signal naturally includes the added DC component Vdc, and a problem arises in that digital processing for removing the DC component Vdc is required separately.
In order to remove the DC component Vdc contained in the digital output signal, it is necessary to first obtain the DC value. However, when the DC value is obtained only from the digital output signal and removed, the DC component contained in the original analog input signal is removed. Will be removed. It is also possible in principle to obtain the DC value contained in the digital output signal in advance from the ratio of the DC component Vdc to be added and the quantized output Vt and to remove the DC value. It is not easy to remove the DC component with sufficient accuracy by, for example, the following. It is even more difficult considering the current situation where various means are taken to remove the DC component of the A / D conversion circuit itself.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problems, in which an idle tone is avoided by adding a DC component to an analog input signal, and the added DC is added to an output digital output signal. It is an object of the present invention to provide an A / D conversion device containing no components.

[0018]

Means for Solving the Problems A first A / A according to the present invention is provided.
A D converter for converting an analog signal into a positive-phase signal and a negative-phase signal, and then adding the same DC component to the positive-phase signal and the negative-phase signal; and a positive-phase signal output from the balance circuit. A first ΔΣ-type A / D conversion circuit that receives a signal, a second ΔΣ-type A / D conversion circuit that receives an antiphase signal output from the balance circuit, and the first and second A / D conversion circuits Digital subtraction means for subtracting a digital signal output from the ΔΣ A / D conversion circuit, wherein the first and second ΔΣ A / D conversion circuits have the same circuit configuration. .

According to the first configuration, after converting an analog signal into a normal-phase signal and a negative-phase signal, the same DC component is added to the normal-phase signal and the negative-phase signal, and then A / D-converted. As a result, the frequency of the idle tone component included in the output of the A / D conversion circuit falls outside the predetermined signal band.
Idle tones (noise) can be avoided. Moreover, the DC component added to the positive-phase signal and the negative-phase signal is canceled by the subtraction processing by the digital subtraction means, so that a digital output signal that does not include the added DC component can be obtained.

According to a second A / D converter according to the present invention, the first A / D converter comprises a first and a second ΔΣ type A.
Analog subtraction means for subtracting an analog signal of the quantization error component output from the / D conversion circuit; and a third inputting the analog signal output from the analog subtraction means.
, A digital signal output from the third ΔΣ A / D conversion circuit as an input, differentiating means for differentiating the digital signal, output from a digital subtracting means and the differential Digital addition means for adding the output from the means.

According to the second configuration, the first configuration is obtained by adding a third ΔΣ A / D conversion circuit, a differentiator, an analog subtractor, and a digital adder to the first configuration.
A / D having second-order differential characteristics in addition to the operation and effect of the configuration of
A conversion circuit can be configured.

A third A / D converter according to the present invention is characterized in that the second to fourth A / D converter includes a fourth to an n-th ΔΣ A / D converter.
A conversion circuit connected to the outputs of the fourth to n-th ΔΣ A / D conversion circuits, respectively,
And a fourth to n-th differentiating means for differentiating the digital signal output from the / D conversion circuit into predetermined differential characteristics (n is an integer of 4 or more). A / D
The conversion circuit receives as input the analog signals of the quantization error components output from the third to (n−1) th ΔΣ-type A / D conversion circuits, and outputs the analog signals from the fourth to nth differentiating means. It is characterized in that the output is inputted to a digital adding means and added.

According to the third configuration, the second A /
A Δ 変 換 type A / D conversion circuit and the ΔΣ type A / D
As a set of circuits including the conversion circuit differentiating means, a circuit having a third-order differential characteristic can be configured by adding one set, and a circuit having a fourth-order differential characteristic can be configured by adding two sets. That is, if (n-3) sets of circuits including the fourth to n-th ΔΣ A / D conversion circuits and the fourth to n-th differentiating means are added, the effect of the second configuration can be obtained. (N-
1) An A / D conversion circuit having the following differential characteristics can be configured.

In one of the first to third A / D converters, a balance circuit converts an analog input signal to output a positive-phase signal and a negative-phase signal; First analog adding means for adding the component and outputting the result to the first ΔΣ A / D conversion circuit; and adding the negative phase signal and the DC component to obtain the second ΔΣ A And a second analog adding means for outputting to the / D conversion circuit.

By using this balance circuit, after converting an analog signal into a positive-phase signal and a negative-phase signal, the same DC component can be added to the positive-phase signal and the negative-phase signal by analog adding means. At this time, the DC component superimposed on the analog input signal is A / D-converted as it is and is included in the digital output signal and output.

The balance circuit of any one of the first to third A / D converters may include a capacitor for inputting an analog input signal, an output from the capacitor as an input to an inverting input terminal, and a DC component. A first inverting amplifier circuit having a first operational amplifier as an input of a non-inverting input terminal, and an output from the first inverting amplifier circuit as an input of an inverting input terminal; A second inverting amplifier circuit having a second operational amplifier as an input of a non-inverting input terminal, wherein the first and second inverting amplifier circuits have the same circuit configuration; The circuit outputs a negative-phase signal to which a DC component is added, and the second inverting amplifier circuit outputs a positive-phase signal to which a DC component is added. Further, the input resistance and the feedback resistance included in the first and second inverting amplifier circuits have the same resistance value.

If this balanced circuit is used, the DC component superimposed on the analog input signal is removed by the capacitor, and the same as the normal phase signal and the negative phase signal with a simple circuit configuration without using an adder. Can be added. Therefore, after the A / D conversion, a digital output signal of only the AC component that does not include the DC component superimposed on the analog input signal is obtained.

An A / D conversion method for an A / D conversion apparatus according to the present invention is the A / D conversion method for an A / D conversion apparatus having a ΔΣ type A / D conversion circuit, wherein an analog input signal is converted to a positive-phase signal. After converting the signal into a negative-phase signal and adding the same DC component to each of the positive-phase signal and the negative-phase signal,
D-conversion is performed, and the added DC component is removed by performing a subtraction process between the A / D-converted normal-phase signal and the negative-phase signal.

According to this A / D conversion method, after converting an analog signal into a positive-phase signal and a negative-phase signal, the same DC component is added to the positive-phase signal and the negative-phase signal, and then A / D converted. Therefore, the frequency of the idle tone component included in the A / D conversion output falls outside the predetermined signal band, and the idle tone can be avoided. Moreover, the DC component added to the positive-phase signal and the negative-phase signal is canceled by the subtraction process before obtaining the digital output signal, so that a digital output signal containing no added DC component can be obtained.

Further, in the above-mentioned A / D conversion method, after the DC component superimposed on the analog input signal is removed by a capacitor, the analog input signal is converted into a normal phase signal and a negative phase signal.

According to this A / D conversion method, the DC component superimposed on the analog input signal is removed by the capacitor, and after the A / D conversion, does not include the DC component superimposed on the analog input signal. A digital output signal of only the AC component is obtained.

[0032]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a block diagram showing a configuration of an A / D converter according to Embodiment 1 of the present invention. In FIG. 1, reference numerals 1 and 2 denote a delta-sigma A / D conversion circuit having the same circuit configuration, 3 denotes a balance circuit, and 4 denotes a digital subtractor. The ΔΣ A / D conversion circuits 1 and 2 are blocks having the same configuration and function as the A / D conversion circuit 50 shown in FIG. The balance circuit 3 outputs an inverting amplifier circuit 5 that outputs a positive-phase (in-phase) signal of an analog input signal and a negative-phase signal whose sign is inverted, a ΔΣ-type A / D conversion by adding the positive-phase signal and the DC component Vdc. Analog adder 6 for outputting to circuit 1
And the negative-phase signal and the DC component Vdc are added to obtain a ΔΣ A / D
And an analog adder 7 for outputting to the conversion circuit 2. The digital subtractor 4 subtracts the outputs from the ΔΣ A / D converter 1 and the ΔΣ A / D converter 2 and outputs the result.

An example of the operation of the A / D converter according to the first embodiment configured as described above will be described below.

First, the analog input signal is converted into a positive-phase signal and a negative-phase signal by the inverting amplifier circuit 5 of the balance circuit 3, and then the analog adder 6 adds the positive-phase signal and the DC component Vdc to each other. The adder 7 adds the negative phase signal and the DC component Vdc.

Therefore, if the analog input signal is X, then Δ
The positive-phase signal input to the Σ-type A / D conversion circuit 1 is (X + V
dc), and the negative-phase signal input to the ΔΣ A / D conversion circuit 2 is (−X + Vdc). These signals are Δ
After being converted into a digital signal by the Σ-type A / D conversion circuit 1 and the ΔΣ-type A / D conversion circuit 2, it is output to the digital subtractor 4. Since the input signal is subtracted in the digital subtractor 4, the DC component Vdc added by the balance circuit 3 is canceled out and included in the output of the signal component of the digital output signal, as is apparent from (Equation 4). No longer.

(X + Vdc) − (− X + Vdc) = 2X (Equation 4) Moreover, even if the DC component Vdc fluctuates due to a manufacturing error, a temperature drift, or the like, it is the reverse of the normal phase signal output from the balance circuit 3. Since the phase signal contains the same DC component Vdc, it does not affect the cancellation of the DC component processed by the digital subtractor 4.

In the first embodiment, the balanced circuit 3
As described above, the circuit constituted by the inverting amplifier circuit 5 and the analog adders 6 and 7 has been described. However, after the analog input signal is converted into the positive-phase signal and the negative-phase signal as described above, A similar effect can be obtained as long as the conversion means has a function of adding the same DC component to each signal and outputting the signal.

(Embodiment 2) Next, an A / D converter according to Embodiment 2 of the present invention will be described.

FIG. 2 is a block diagram showing a configuration of a balanced circuit according to the A / D converter of the second embodiment. By using the balance circuit 12 shown in FIG. 2 instead of the balance circuit 3 in the first embodiment shown in FIG. 1, when a DC component included in an analog input signal is unnecessary, an adder is not used.
The same DC component can be easily added to the positive-phase signal and the negative-phase signal.

In FIG. 2, 13 and 14 are operational amplifiers (operational amplifiers), 15 and 16 are input resistors, 17 and 18 are feedback resistors, and 19 is a capacitor. The input resistance 1
The resistors 5 and 16 and the feedback resistors 17 and 18 are all resistors having the same resistance value R.

The balance circuit 12 comprises a first inverting amplifier circuit 20 comprising three elements of an operational amplifier 13, an input resistor 15 and a feedback resistor 17, and a second inverting circuit 20 comprising three elements of an operational amplifier 14, an input resistor 16 and a feedback resistor 18. An inverting amplifier circuit 21 is connected in series, and an analog input signal is supplied to a first inverting amplifier circuit 20 via a capacitor 19. The same DC component Vdc is input to the non-inverting input terminals of the operational amplifiers 13 and 14.

With the above configuration, the first inverting amplifier circuit 2
From 0, an inverted phase signal is output as an output signal,
The input signal is input as an input signal to the second inverting amplifier circuit 21 connected in series, and a positive-phase signal is output from the second inverting amplifier circuit 21 as an output signal.

An example of the operation of the balanced circuit 12 according to the second embodiment configured as described above will be described below.

The input resistor 15 and the feedback resistor 17 of the first inverting amplifier circuit 20, and the input resistor 16 and the feedback resistor 18 of the second inverting amplifier circuit 21 are all resistors having the same resistance value R. , The amplification rate (gain) becomes “1”. Further, since the analog input signal is input to the first inverting amplifier circuit 20 via the capacitor 19, the DC component superimposed on the analog input signal is removed by the capacitor 19, and the analog input signal output from the capacitor 19 Assuming that the AC component is Xo, the positive-phase signal output and the negative-phase signal output are signals shown in (Equation 5), and the DC component Vdc can be added to be equal to the AC component Xo of the analog input signal.

Positive-phase signal output = + Xo + Vdc (Equation 5) Negative-phase signal output = −Xo + Vdc In the second embodiment, for the sake of simplicity, the same amplification factor is set to “1”. Although the description has been made using the resistor having the resistance value R, a different circuit configuration may be used as long as the function of adding the same DC component is not impaired as described above. For example, the gain can be changed by changing the resistance value of the resistor 15, and the frequency characteristic can be provided by connecting a capacitor in parallel with any one of the resistors.

In the description of the first embodiment and the second embodiment, the accuracy of each analog element and the direct current component of the operational amplifier are ignored, but actually, these elements are the causes. The digital output signal contains a DC component. Particularly, the operational amplifier of a CMOS type integrated circuit has a level at which a DC component generated due to a manufacturing error or a temperature drift cannot be ignored.
When an A / D converter is constituted by an OS type integrated circuit, it is almost essential to remove a DC component by digital processing. However, if analog devices are configured close to each other on the same integrated circuit, it is possible to obtain relative accuracy much higher than absolute accuracy. Utilizing this feature, if the above-mentioned ΔΣ A / D conversion circuit 1, ΔΣ A / D conversion circuit 2 and balance circuit 3 or balance circuit 12 are arranged close to each other on the same integrated circuit, generation by analog elements will occur. The DC components are very close relative values, and can be accurately canceled by the digital subtractor 4.

(Embodiment 3) In the A / D converter shown in FIG. 5, the differential characteristic multiplied by Vqn is a first-order characteristic as shown in (Equation 2), and the noise suppression amount in the low frequency region is not always required. In general, circuits having third and fourth order differential characteristics are often used because they are not sufficient. Needless to say, the circuit configuration of the third- and fourth-order differential characteristics is more complicated and large-scale than the circuit configuration of the first-order differential characteristics. Therefore, if a circuit using two identical ΔΣ-type A / D conversion circuits as shown in FIG. 1 and simply obtaining a differential characteristic higher than the secondary characteristic is formed, the circuit scale becomes twice or more. . Therefore, in the A / D converter according to the third embodiment, a circuit configuration in which the A / D converter shown in FIG. 1 is used as a basic circuit, and a secondary or higher-order differential characteristic can be obtained by adding a small number of circuits. provide.

FIG. 3 shows an A / A according to the third embodiment of the present invention.
FIG. 2 is a block diagram illustrating a configuration of a D conversion device. 3, blocks having the same configurations and functions as those in FIG. 1 are denoted by the same reference numerals. Reference numerals 1, 2, and 8 denote a delta-sigma A / D conversion circuit having the same circuit configuration, 3 denotes a balance circuit, 4 denotes a digital subtractor, 9 denotes a differentiator, 10 denotes an analog subtractor, and 11 denotes a digital adder. The balance circuit 3 adds an inverting amplifier circuit 5 that outputs a positive-phase (in-phase) signal of an analog input signal and a reverse-phase signal whose sign is inverted, as in FIG. 1, and adds the positive-phase signal and the DC component Vdc. Adder 6 for outputting to the ΔΣ type A / D conversion circuit 1,
And an analog adder 7 for adding the result to the A / D conversion circuit 2.

The ΔΣ type A / D conversion circuits 1, 2, and 8 convert analog signals input to the respective circuits into digital signals under the same sampling clock and output the digital signals.
At the same time, the quantization error component (the difference between the input and output of the quantizer 53) is output as analog signals Vq1, Vq2, and Vq8 (Vq8 is not shown). The digital subtractor 4 has a ΔΣ type A
The digital output signals output from the / D conversion circuit 1 and the ΔΣ A / D conversion circuit 2 are input, subjected to subtraction processing, and then output to the digital adder 11. Analog subtractor 10
Are ΔΣ A / D conversion circuit 1 and ΔΣ A / D conversion circuit 2
Analog signals Vq1 and V of quantization error components output from
q2 is input, subtracted, and then output to the ΔΣ A / D conversion circuit 8. The differentiator 9 receives the digital output signal output from the A / D conversion circuit 8 as an input, performs ideal first-order differentiation, and outputs the result to the digital adder 11.

FIG. 4 is a block diagram showing the configuration of the differentiator 9 according to the present invention. In FIG. 4, reference numeral 22 denotes a digital subtractor, and reference numeral 23 denotes a DFF. ΔΣ A / D conversion circuit 8
Is input directly to the digital subtractor 22, is input to the digital subtracter 22 after passing through the DFF 23, and is input from the input signal directly input to the digital subtracter 22 through the DFF 23. Is subtracted and output to the digital adder 11. The transfer characteristic Hd of the differentiator 9 is expressed by (Equation 6) using a Z function.

Hd (z) = 1−z ⁻¹ (Equation 6) In the A / D converter of FIG. 3, the balanced circuit 3 and the ΔΣ type A
The operations and functions of the A / D conversion circuit 1, the ΔΣ A / D conversion circuit 2, and the digital subtractor 4 are the same as those of the A / D conversion circuit 50 shown in FIG.
Is a digital output signal Y _{1 as shown} in (Equation 7).

Y ₁ = 2X + (1−z ⁻¹ ) (Vq ¹ −Vq 2) (Equation 7) The digital output signal Y ₂ from the ΔΣ A / D conversion circuit 8 is represented by (Equation 8) become.

Y ₂ = (Vq1−Vq2) + (1−z ⁻¹ ) Vq8 (Equation 8) Further, the digital output signal Y ₂ from the ΔΣ type A / D conversion circuit 8 is supplied to a differentiator 9. is output to the digital adder 11 via, the digital output signal Y ₃ are added to the digital output signal Y ₁ from the digital subtractor 4. Therefore, the digital output signal Y ₃ is represented by (Equation 9) from (Equation 6), (Equation 7), and (Equation 8).

Y ₃ = Y ₁ + Hd × Y ₂ = 2X + (1-z ⁻¹ ) ² Vqn (Equation 9) In other words, as can be seen from (Equation 9), A having the secondary characteristic
/ D converter can be obtained. As described above, adding only a small number of circuits to the A / D conversion circuit 50 of FIG.
An A / D converter having the following differential characteristic can be realized.

Therefore, the digital signal output obtained by subtracting the output from the ΔΣ A / D conversion circuit 1 and the ΔΣ A / D conversion circuit 2 by the digital subtractor 4 is given by Δ
If the technical idea of obtaining a digital output signal having a second-order differential characteristic by adding digital output signals obtained by the Σ-type A / D conversion circuit 8 and the differentiator 9 is developed, it is easy to add a small number of circuits to obtain a digital output signal. A digital output signal having the following differential characteristic can be obtained.

For example, a circuit configuration for obtaining a digital output signal having a third-order differential characteristic will be briefly described. An A / D converter shown in FIG. One additional circuit consisting of a characteristic differentiator
The quantization error output Vq8 of the type A / D conversion circuit 8 is input to the Δ 特性 type A / D conversion circuit for tertiary characteristics, and the ΔΣ type A / D
The output from the D conversion circuit is output to the digital adder 11 via the tertiary characteristic differentiator and subjected to addition processing. Since the third-order characteristic differentiator needs to obtain the second-order differential characteristic in order to cancel the term of the quantization error Vq8 included in the digital output signal of the differentiator 9, the differentiator in FIG. It is configured by connecting them in series.

That is, in the A / D converter shown in FIG.
A type A / D conversion circuit and a differentiator for the conversion circuit are regarded as one set of circuits. If one set is added, a circuit having a tertiary differential characteristic is configured. If two sets are added, a circuit having a fourth differential characteristic is provided. Can be configured. Therefore, the fourth to n-th ΔΣ type A
/ D conversion circuit and (n-3) sets of circuits consisting of fourth to n-th differentiating means are added, and the outputs from the (n-3) sets of conversion circuits are input to the digital adder 11 for addition. By performing the processing, an A / D conversion circuit having (n-1) th-order differential characteristics can be configured (an integer of n ≧ 4).

In the third embodiment, the ΔΣ A / D
Although the A / D conversion circuit shown in FIG. 5 has been used as the conversion circuits 1, 2, and 8 as the same circuit, the purpose of the present invention is to subtract the outputs of the ΔΣ A / D conversion circuits 1 and 2. Thus, the DC component is canceled out, and the ΔΣ A / D conversion circuits 1 and 2 need only be the same circuit, and the ΔΣ A / D conversion circuit for obtaining secondary characteristics or higher is not limited to this. For example, the ΔΣ A / D conversion circuit 8 may be a double integration circuit.

When the DC component included in the analog input signal is unnecessary in the third embodiment, the balanced circuit 1 shown in FIG.
2 may be used.

[0061]

As described above, according to the A / D conversion apparatus and the A / D conversion method of the present invention, an idle tone can be effectively avoided and added by adding a DC component to an analog input signal. Since the added DC component is eliminated by subtraction processing before obtaining the digital output signal, the digital output signal has an excellent feature that the added DC component is not included.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an A / D converter according to Embodiment 1 of the present invention.

FIG. 2 is a block diagram showing a configuration of a balanced circuit of an A / D converter according to Embodiment 2 of the present invention.

FIG. 3 is a block diagram showing a configuration of an A / D converter according to Embodiment 3 of the present invention.

FIG. 4 is a block diagram showing a configuration of a differentiator 9 in FIG.

FIG. 5 is a block diagram showing a configuration of a conventional A / D converter.

6 is a block diagram showing a configuration of an integrator 52 in FIG.

FIG. 7 is a waveform diagram of an input signal and an output signal of the quantizer 53 in FIG.

[Explanation of symbols]

1, 2, 8 ΔΣ-type A / D conversion circuit 3, 12, balance circuit 4 digital subtractor 5 inverting amplifier circuit, which outputs positive-phase (in-phase) signal and reverse-phase signal 6, 7, analog adder 9 differentiator 10 analog subtraction Unit 11 Digital adder 13, 14 Operational amplifier 15, 16 Input resistance 17, 18 Feedback resistance 19 Capacitor 20, 21 Inverting amplifier circuit 22 Digital subtracter 23 DFF

Claims (8)

[Claims] 1. A balance circuit for converting an analog signal into a positive-phase signal and a negative-phase signal, and then adding the same DC component to the positive-phase signal and the negative-phase signal, and a positive-phase signal output from the balance circuit. A first ΔΣ-type A / D conversion circuit that receives a signal, a second ΔΣ-type A / D conversion circuit that receives an antiphase signal output from the balance circuit, and the first and second A / D conversion circuits Digital subtraction means for subtracting a digital signal output from the ΔΣ A / D conversion circuit, wherein the first and second ΔΣ A / D conversion circuits have the same circuit configuration. A / D converter. 2. An analog subtractor for subtracting an analog signal of a quantization error component output from the first and second ΔΣ-type A / D converters, and an analog signal output from the analog subtractor. The third ΔΣ type A /
A D conversion circuit, a digital signal output from the third ΔΣ type A / D conversion circuit, a differentiating means for differentiating the digital signal, an output from the digital subtracting means, and an output from the differentiating means. 2. The A / D conversion apparatus according to claim 1, further comprising: a digital addition means for performing addition processing. 3. A fourth to n-th ΔΣ A / D conversion circuits,
The digital signals output from the fourth to n-th ΔΣ A / D conversion circuits are connected to the outputs of the fourth to n-th ΔΣ A / D conversion circuits, respectively, and are differentiated into predetermined differential characteristics. And a fourth to n-th differentiating means (n ≧ 4
), The fourth to n-th ΔΣ A / D conversion circuits are
Analog signals of quantization error components output from the third to (n-1) th ΔΣ A / D conversion circuits are input, and outputs from the fourth to nth differentiating means are digitally added. 3. The A / D conversion apparatus according to claim 2, wherein the A / D conversion is performed by inputting to the means. 4. A balancing circuit for converting an analog input signal to output a positive-phase signal and a negative-phase signal, and a process for adding the positive-phase signal and a DC component to generate a first ΔΣ type A signal. / D
A first analog adding means for outputting to the conversion circuit; and a second analog adding means for performing addition processing of the negative-phase signal and the DC component and outputting the result to a second ΔΣ A / D conversion circuit. The A / D converter according to any one of claims 1 to 3, wherein: 5. A balance circuit comprising: a capacitor for inputting an analog input signal; and a first operational amplifier having an output from the capacitor as an input of an inverting input terminal and a DC component as an input of a non-inverting input terminal. A second inverting amplifier circuit, and a second operational amplifier having an output from the first inverting amplifier circuit as an input of an inverting input terminal and a DC component identical to the DC component input to a non-inverting input terminal. An inverting amplifier circuit, wherein the first and second inverting amplifier circuits have the same circuit configuration, and the first inverting amplifier circuit outputs a reverse-phase signal to which a DC component has been added, 4. The A according to claim 1, wherein the inverting amplifier circuit outputs a positive-phase signal to which a DC component is added.
/ D converter. 6. The A / D converter according to claim 5, wherein the input resistance and the feedback resistance included in the first and second inverting amplifier circuits have the same resistance value. 7. An A / D conversion method in an A / D conversion device having a ΔΣ type A / D conversion circuit, wherein an analog input signal is converted into a normal phase signal and a negative phase signal, and the normal phase signal and the negative phase signal are converted. After adding the same DC component to each signal, A / D conversion is performed, and the added DC component is removed by performing a subtraction process on the A / D converted positive-phase signal and negative-phase signal. A / D conversion method. 8. The A / D conversion method according to claim 7, wherein a DC component superimposed on the analog input signal is removed by a capacitor, and then the analog input signal is converted into a positive-phase signal and a negative-phase signal.