JPH11135520A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device with an adequate length between a gate electrode edge and a recessed edge under control, when a recessed part and a gate electrode are formed in self-alignment. SOLUTION: An insulating film 4 with an opening is formed on a semiconductor cap layer 3. A dry etching step is carried out for the semiconductor cap layer 3 with an etching stopper layer 2 selectively in an anisotropic way through the insulating film 4 as a mask. Then, a dry etching step is carried out for the semiconductor cap layer 3 with the etching stopper layer 2 selectively in an isotropic way to form a recessed part 6. A gate electrode 7 is formed in the opening of the insulating film 4, and a source electrode 8 and a drain electrode 9 are formed. In this method, the isotropic etching time is made short as compared with a case, in which the isotropic etching is carried from the beginning to form a side edge, and the control on the quantity of the side edge can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a compound semiconductor device.

[0002]

2. Description of the Related Art A compound semiconductor device, which is often used as an amplifying element in microwave and millimeter wave bands, uses a recess structure capable of realizing high output characteristics and high gate withstand voltage, thereby improving high speed and low noise characteristics. For this purpose, a semiconductor crystal material having a hetero junction is used. For example, for a semi-insulating gallium arsenide (GaAs) substrate, aluminum gallium arsenide (AlGaAs) / GaAs or indium gallium arsenide (InGaAs) / AlGaAs / Ga
A heterojunction is used in which As or the like is sequentially grown. In the case of a semi-insulating indium phosphide (InP) substrate, InGaAs / indium aluminum arsenide (I
A heterojunction grown from nAlAs) / GaAs or the like is used. In such a crystalline material, high mobility is realized by heterojunction selective doping and two-dimensional state transition of electrons.

FIG. 4 shows a heterojunction field-effect transistor (H) using a semiconductor crystal material having this heterojunction.
JFET: Hetero Junction Field Effect Transisto
The apparatus sectional view in each process of an example of the conventional manufacturing method for manufacturing r) is shown. A similar example of this conventional manufacturing method is disclosed in Japanese Patent Application Laid-Open No. 8-153871.

[0004] First, as shown in FIG.
On a substrate 21, an etching stopper layer of AlGaAs
An s layer 22 and a GaAs layer 23 as a semiconductor cap layer are sequentially stacked, and a photoresist 24 is formed thereon,
Using this as a mask, chlorine (Cl ₂ ) and sulfur hexafluoride (S
N-type Al using a mixed gas containing chlorine and fluorine, such as a mixed gas of F ₆ ) or a mixed gas of boron trichloride (BCl ₃ ) and SF _6.
The n-type GaAs layer 23 is dry-etched selectively with respect to the GaAs layer 22 to form a recess 25.

Next, as shown in FIG. 4B, after an insulating film 26 such as silicon dioxide (SiO ₂ ) is formed on the entire surface, an opening is formed in the recess 25 using lithography and dry etching. Form a part.

Subsequently, a tungsten silicide (WSi) / titanium nitride (TiN) / platinum (Pt) / gold (Au) film serving as a gate electrode is formed to a thickness of 100 nm and 15 nm, respectively.
After sequentially depositing films having a thickness of 0 nm, 15 nm, and 400 nm by a vapor deposition method or a sputtering method, a photoresist mask is formed using lithography technology, and portions other than the gate electrode head are removed using RIE or ion milling. Thus, a T-shaped gate electrode 27 is formed as shown in FIG. Further, as shown in FIG. 4D, a source electrode 28 and a drain electrode 29 are formed to manufacture an HJFET as a semiconductor device.

In the case of the above-mentioned conventional manufacturing method, the recess 25 is formed.
And the gate electrode 27 are determined by lithography alignment, and thus misalignment occurs. When the recess dimension (Lr) is sufficiently large with respect to the gate dimension (Lg), that is, when the distance between the gate end and the recess end (Lgr) is sufficiently larger than the alignment accuracy, it can be manufactured by the above method. Is small, misalignment becomes a problem.

For example, if the Lgr design dimension is 0.1 μm,
If the alignment accuracy at the time of manufacture can be guaranteed within 0.05 μm, Lgr is manufactured in the range of 0.05 to 0.15 μm, and Lgr varies up to three times at the maximum. When the gate electrode 27 approaches the recess end on the drain electrode 29 side, there arises a problem that the breakdown voltage between the gate and drain decreases. On the other hand, when the gate electrode 27 approaches the recess end on the source electrode 28 side, the capacitance between the gate and source ( Cgs) becomes large, causing a problem of deteriorating high frequency characteristics.

In order to solve the problem of misalignment, a method of forming a recess and a gate electrode by self-alignment has been proposed (for example, Japanese Patent Application No. 8-288610).
No .: Title of the invention "Field-effect transistor and manufacturing method thereof"). The proposed method of manufacturing a semiconductor device will be described with reference to FIG. In the above proposed method, 2
Although a method of forming the gate electrode at the time of the step recess is described, FIG. 5 shows a manufacturing method at the time of the single step recess for simplicity.

First, as shown in FIG.
On a substrate 21, an etching stopper layer of AlGaAs
s layer 22, are stacked GaAs layer 23 are successively a semiconductor cap layer, after forming a SiO ₂ film thereon, forming a SiO ₂ film mask 30 using a lithography technique and an etching technique. Next, the n-type AlGaAs layer 22
The n-type GaAs layer 23 is selectively dry-etched to form a recess 25.

In the dry etching for forming the recess 25, in the above-described process, the GaAs layer 23 needs to be isotropically etched to cause side etching on the SiO ₂ film mask 30. This is because, when anisotropic etching is performed, the gate electrode 27 and n-GaAs
The contact on the layer 23 increases the gate leakage current,
This is because the gate breakdown voltage decreases. That is, the gate electrode 27 described later and the n-GaAs layer 2 are formed by side etching.
The three ends have a distance, and the gate breakdown voltage can be increased.

Thereafter, as shown in FIG. 5B, the WSi.TiN.Pt is formed in the same manner as in the conventional manufacturing method shown in FIG.
After forming the T-shaped gate electrode 27 made of Au film,
As shown in FIG. 5C, a source electrode 28 and a drain electrode 29 are formed, and an HJFET as a semiconductor device is manufactured.

[0013]

However, in the conventional method of manufacturing a semiconductor device described with reference to FIG. 5 in which the recess 25 and the gate electrode 27 are formed by self-alignment, the GaAs layer 23 is isotropically etched. , SiO ₂
Since side etching is caused on the film mask 30, there is a problem that the controllability of the distance (Lgr) between the gate electrode end and the recess end is poor.

That is, the variation between the wafers and the variation in the wafer surface of the etching rate at the time of etching the GaAs layer 23 becomes the variation of Lgr as it is. When the controllability of Lgr is poor, when Lgr is smaller than desired, there arises a problem that the breakdown voltage between the gate and the drain is reduced. On the other hand, when Lgr is larger than desired, the capacitance (Cgs) between the gate and the source is increased, There is a problem that the high frequency characteristics deteriorate.

The present invention has been made in view of the above points,
It is an object of the present invention to provide a method of manufacturing a semiconductor device capable of manufacturing a distance between a gate electrode end and a recess end with good control when the recess and the gate electrode are formed in a self-aligned manner.

[0016]

In order to achieve the above object, the present invention provides a first step of sequentially laminating an etching stopper layer and a semiconductor layer on a semiconductor substrate, and forming an opening on the semiconductor layer. A second step of forming the formed insulating film, a third step of selectively and anisotropically etching the semiconductor layer with respect to the etching stopper layer using the insulating film as a mask, and etching using the insulating film as a mask. Fourth step of etching the semiconductor layer selectively and isotropically with respect to the stopper layer to cause desired side etching, and fifth step of forming a gate electrode using the insulating film as a positioning mask Is included.

Further, the present invention provides the above-mentioned third step and fourth step.
A step of removing adhering substances adhered to the side wall of the semiconductor layer in the third step may be provided between the steps, or a side wall insulating film may be formed on the side wall of the semiconductor layer after the fourth step. The forming step may be loaded.

Here, in the step of removing the deposits, the entire surface is irradiated with plasma using a hydrogen gas in an apparatus for generating plasma discharge, or a gas containing at least fluorine is used in an apparatus for generating plasma discharge. Plasma irradiation is performed on the entire surface of the substrate.

Further, the semiconductor substrate is a compound semiconductor substrate. In the anisotropic etching, the selectivity between the constituent material of the etching stopper layer and the constituent material of the semiconductor layer can be realized to be 100 or more. The isotropic etching is performed under the condition that the layer can be etched, and the isotropic etching is performed under the condition that the selectivity between the constituent material of the etching stopper layer and the constituent material of the semiconductor layer can be 100 or more and the semiconductor layer can be isotropically etched. Do.

In the present invention, the insulating film having the above-described opening is used as a mask for determining the position of the gate electrode,
After selectively etching the semiconductor cap layer selectively and anisotropically with respect to the etching stopper layer using this mask, the semiconductor cap layer is selectively and isotropically etched with respect to the etching stopper layer. Is dry-etched to produce the desired side etching, so that the time for performing the isotropic etching of the semiconductor layer can be reduced as compared with the case where the isotropic etching is performed from the beginning to cause the side etching. Variation in side etching amount can be reduced.

[0021]

Next, an embodiment of the present invention will be described with reference to the drawings.

(First Embodiment) FIG. 1 is a sectional view of a method of manufacturing a semiconductor device according to a first embodiment of the present invention in the order of steps. First, as shown in FIG. 1A, an etching stopper layer 2 and a semiconductor cap layer 3 are sequentially epitaxially grown on a semiconductor substrate 1. Next, after an insulating film 4 having an opening is formed on the semiconductor cap layer 3, as shown in FIG. 1A, the insulating film 4 is used as a mask and selectively with respect to the etching stopper layer 2 and ,
The semiconductor cap layer 3 is dry-etched anisotropically.

Subsequently, the semiconductor cap layer 3 is dry-etched selectively and isotropically with respect to the etching stopper layer 2 to produce desired side etching as shown in FIG. , A recess 6 is formed.

Next, as shown in FIG. 1C, a gate electrode 7 is formed in the opening of the insulating film, and thereafter, as shown in FIG. 1D, a source electrode 8 and a drain electrode 9 having ohmic properties. Is formed to manufacture a semiconductor device.

As described above, in this embodiment, using the mask of the insulating film 4 for determining the position of the gate electrode 7, the etching stopper layer 2 can be selectively formed.
Anisotropically, after dry etching the semiconductor cap layer 3, selectively with respect to the etching stopper layer 2, and
Since the desired side etching is caused by dry-etching the semiconductor cap layer 3 isotropically, the distance between the gate electrode end and the recess end can be manufactured with good controllability.

(Second Embodiment) Next, a second embodiment of the present invention will be described.
An embodiment will be described with reference to the drawings. FIG. 2 is a sectional view of a second embodiment of a method of manufacturing a semiconductor device according to the present invention in the order of steps. First, as shown in FIG. 2A, an etching stopper layer 2 and a semiconductor cap layer 3 are sequentially epitaxially grown on a semiconductor substrate 1. Next, after an insulating film 4 having an opening is formed on the semiconductor cap layer 3, as shown in FIG. 2A, the insulating film 4 is used as a mask and selectively with respect to the etching stopper layer 2, and Anisotropically, the semiconductor cap layer 3 is dry-etched.

After that, as shown in FIG. 2B, the deposit attached to the side wall of the semiconductor cap layer 3, that is, the side wall deposit 5 is removed by a known method. Subsequently, FIG.
As shown in (c), the semiconductor cap layer 3 is dry-etched selectively and isotropically with respect to the etching stopper layer 2 to cause desired side etching to form a recess 6.

Next, as shown in FIG. 2D, after a gate electrode 7 having a Schottky property is formed, FIG.
As shown in (1), a source electrode 8 and a drain electrode 9 having ohmic properties are formed to manufacture a semiconductor device. In this embodiment, similarly to the first embodiment, the distance between the gate electrode end and the recess end can be manufactured with good controllability. Further, since the isotropic etching is performed after removing the side wall deposit 5, the side etching starts at the same time as the etching starts, the side etching starts at the same time as the etching starts, and the start of the side etching is delayed. There is no. Therefore, the controllability of the side etching amount is the first.
It is improved as compared with the embodiment.

(Third Embodiment) Next, a third embodiment of the present invention will be described.
An embodiment will be described with reference to the drawings. FIG. 3 is a sectional view of a device in a manufacturing order according to a third embodiment of the method of manufacturing a semiconductor device according to the present invention. First, as shown in FIG. 3A, an etching stopper layer 2 and a semiconductor cap layer 3 are sequentially epitaxially grown on a semiconductor substrate 1. Next, after an insulating film 4 having an opening is formed on the semiconductor cap layer 3, as shown in FIG. 3A, the insulating film 4 is used as a mask and selectively with respect to the etching stopper layer 2, and Anisotropically, the semiconductor cap layer 3 is dry-etched.

Thereafter, as shown in FIG. 3B, the sidewall deposits 5 attached to the sidewalls of the semiconductor cap layer 3 are removed by a known method. Subsequently, as shown in FIG.
The semiconductor cap layer 3 is dry-etched selectively and isotropically with respect to the etching stopper layer 2 to cause desired side etching to form a recess 6. The above steps are the same as in the second embodiment.

Next, as shown in FIG. 3D, a sidewall oxide film 10 is formed on the sidewall of the semiconductor cap layer 3. Thereafter, as in the first and second embodiments, FIG.
A gate electrode 7 having a Schottky property is formed as shown in FIG. 3A, and a source electrode 8 and a drain electrode 9 having an ohmic property are formed as shown in FIG.

In the third embodiment, the side wall oxide film 1
By forming 0, the side-etch region of the semiconductor cap layer 3 is protected, so that the burying property of the gate electrode 7 is improved, voids are not generated in the gate electrode 7, and the gate electrode 7 has a stable shape. 7 can be formed.

[0033]

Next, embodiments of the method for manufacturing a semiconductor device according to the present invention will be described with reference to the drawings.

(First Example) A first example of the present invention is an example of the first embodiment shown in FIG. 1 and will be described with reference to FIG. First, as shown in FIG. 1 (a), a semi-insulating GaAs substrate is used as a semiconductor substrate 1, and a molecular beam crystal growth (MBE) method or a vapor phase growth (MOCVD) method using organometallic thermal decomposition is performed thereon. An Al _0.2 Ga _0.8 As layer as the etching stopper layer 2 and a GaAs layer as the semiconductor cap layer 3 are sequentially epitaxially grown.
The thickness of the Al _0.2 Ga _0.8 As layer is 120 nm, the impurity concentration is 2 × 10 ¹⁷ cm ⁻³ , and the thickness of the GaAs layer is 200
nm, and the impurity concentration is 5 × 10 ¹⁷ cm ⁻³ .

Next, the semiconductor cap layer 3 of GaAs
A 300 nm thick insulating film 4 made of SiO ₂ is grown on the layer, a photoresist film pattern is formed using lithography technology, and then reactive ion etching (RI) is performed.
E) Using a device, the gate opening 11 is formed by dry etching using a mixed gas of carbon tetrafluoride (CF ₄ ), fluorohydrocarbon (CHF ₃ ), and argon (Ar). After that, the photoresist film is removed.

Next, a dielectric coupled plasma (ICP) etching device, SiCl ₄ and SF ₆ and nitrogen (N ₂₎ 4 mixed gas of the gas: 2: 1 at flow rate, pressure 1 Pa, the plasma source power 200W (13.56 MHz) and an RF bias power of 5 W (13.56 MHz), using the insulating film 4 having the gate opening 11 as a mask as shown in FIG.
Selectively and anisotropically with respect to the _0.2 Ga _0.8 As layer,
The GaAs layer serving as the semiconductor cap layer 3 is dry-etched.

Here, the side wall deposit 5 is formed on the side surface of the GaAs layer.
Adheres to form an anisotropic shape. When the above-mentioned gas is used, the side wall deposit 5 is mainly made of a Si compound (Si
Cl _x , SiCl _x O _y, etc.). The etching condition is such that the selectivity between GaAs and AlGaAs is 10
Conditions other than the above may be used as long as 0 or more can be realized and anisotropic etching can be performed. For example, IC
P can be realized with an electron cyclotron resonance (ECR) etching apparatus or an RIE apparatus by using a gas composed of silicon and a halogen containing fluorine.
iCl ₄ + SF ₆ , SiCl ₄ + nitrogen trifluoride (NF ₃ ),
SiCl ₄ + SiF ₄ , SiBr ₄ + SF ₆ gas and the like.

Thereafter, in the same chamber,
A mixed gas of BCl ₃ and SF ₆ gas is selected at a flow ratio of 3: 1 under the conditions of a pressure of 2 Pa, a plasma source power of 200 W, and an RF bias power of 0 W with respect to the Al _0.2 Ga _0.8 As layer as the etching stopper layer 2. The GaAs layer serving as the semiconductor cap layer 3 is dry-etched in a uniform and isotropic manner, and as shown in FIG. 1B, a side opening of 0.01 μm on one side of the gate opening is caused.
The etching conditions were GaAs and AlGaAs.
Conditions other than those described above may be used as long as a selection ratio of s of 100 or more can be realized and isotropic etching can be performed.

Thereafter, an aqueous hydrochloric acid solution (HCl and H
Aluminum fluoride (AlF ₃ ) adhered to the surface of the etching stopper by dipping at a ₂ O ratio of 1: 1)
Is removed to expose a clean AlGaAs surface.
i, TiN, Pt, and Au films are 100 nm, 15
After sequentially forming a film having a thickness of 0 nm, 15 nm, and 400 nm, a T-shaped Schottky gate electrode 7 is formed in the gate opening using a lithography technique and a dry etching technique, as shown in FIG. Form.

Subsequently, as shown in FIG. 1D, in order to form an ohmic electrode, an opening is formed in the insulating film 4 using buffered hydrofluoric acid using a photoresist film as a mask, and evaporation, lift-off, and By alloy processing, A
A semiconductor device is manufactured by forming a source electrode 8 and a drain electrode 9 made of uGeNi.

During GaAs dry etching, the variation in the etching rate within the wafer surface is ± 5% (the etching rate with the above-mentioned BCl ₃ and SF ₆ gases is 260 ± 5%).
In the case of the conventional manufacturing method, since the entire etching time (1 minute and 10 seconds) was isotropic etching, the variation in the amount of side etching in the wafer surface was 0.04 μm. On the other hand, in the present embodiment, the time for performing isotropic etching is reduced (2).
5 seconds), the variation of the side etching amount in the wafer surface was 0.02 μm, and it was confirmed that the controllability of Lgr was improved.

In this embodiment, an SiO ₂ film mask is used as an etching mask for the semiconductor cap layer 3.
A photoresist may be used. In this embodiment, a GaAs layer is used as the semiconductor cap layer 3 and an AlGaAs layer is used as the etching stopper layer 2. However, any compound semiconductor layer, compound composition ratio, and donor concentration may be used as long as they play their respective roles. You may use it.
Further, in this embodiment, an example in which a one-step recess is formed has been described.
The present invention can be applied to a case where two or more recesses are formed.

Second Embodiment Next, a second embodiment of the present invention will be described with reference to the drawings. This second example is an example of the second embodiment shown in FIG. 2 and will be described with reference to FIG. First, as shown in FIG. 2A, Ga which is a semiconductor cap layer 3 formed in the same manner as in the first embodiment is used.
A mask made of the insulating film 4 is formed on the As layer, and SiCl ₄
GaAs as the semiconductor cap layer 3 selectively and anisotropically with respect to the Al _0.2 Ga _0.8 As layer as the etching stopper layer 2 by using a mixed gas of SF ₆ and SF ₆ and N ₂ gas.
The s layer is dry etched.

Subsequently, in the same chamber, H ₂ gas 2
0 sccm, pressure 1.5 Pa, plasma source power 1
Under the conditions of 00 W and RF bias power of 0 w, the wafer is irradiated with hydrogen radicals to remove the side wall deposit 5 as shown in FIG. In this step, Si compounds (SiCl _x , SiCl _x ) adhered to the surface or the side wall by the action of H ^*
_Oy ) is reduced, volatilized and removed in the form of SiH ₄ , and the sidewall deposit 5 is removed.

Subsequently, in the same chamber,
The GaAs layer serving as the semiconductor cap layer 3 is dry-etched selectively and isotropic with respect to the Al _0.2 Ga _0.8 As layer serving as the etching stopper layer 2 by using a mixed gas of BCl ₃ and SF ₆ gas, A side etching of 0.01 μm on one side is caused. After that, as in the first embodiment,
After a gate electrode 7 having a Schottky property is formed as shown in FIG. 2D, a source electrode 8 and a drain electrode 9 having an ohmic property are formed as shown in FIG. Is manufactured.

In the second embodiment, the removal of the side wall deposit 5 is performed.
Used hydrogen as the gas, but contained F as the other gas.
Gas, for example, SF₆And NF_ThreeIt can be gas. this
For gas, F^* Adhered to the surface and side walls by the action of
Compound (SiCl_x, SiCl_xO_yEtc.) is SiF_FourForm of
Is volatilized and removed. This reaction is performed at 1 atm of each compound.
As shown by the boiling point of_Four(Boiling point: 57.6 ° C)
Than SiF_Four(-86 ° C) is more volatile
Utilizing the nature. Also, on the AlGaAs layer, Al
F_ThreeAre formed, the gas containing F contains Al
The GaAs layer is not etched at all.

(Third Embodiment) Next, a third embodiment of the present invention will be described with reference to the drawings. This third example is an example of the third embodiment shown in FIG. 3, and will be described with reference to FIG. First, as shown in FIG. 3A, a mask made of an insulating film 4 is formed on a GaAs layer which is a semiconductor cap layer 3 formed in the same manner as in the first and second embodiments.
using LiCl ₄ and SF ₆ and N ₂ gas mixed gas, selective to Al _0.2 Ga _{0 .8} As layers are etching stopper layer 2, and, anisotropically, it is a semiconductor capping layer 3 The GaAs layer is dry-etched.

Subsequently, in the same chamber, as shown in FIG.
After removal of the side wall deposits 5 as shown in, BCl ₃ and S
The GaAs layer serving as the semiconductor cap layer 3 is dry-etched selectively and isotropic with respect to the Al _0.2 Ga _0.8 As layer serving as the etching stopper layer 2 by using a mixed gas of F ₆ gas, and FIG. 0.01 μm on one side as shown in (c)
Side etching occurs.

After an oxide film is formed on the entire surface, SF
_The entire surface is etched back by dry etching using ₆ gases, and as shown in FIG. 3, a sidewall oxide film 10 is formed on a side surface of the GaAs layer which is a mask of the insulating film 4 and the semiconductor cap layer 3.

Thereafter, in the same manner as in the first and second embodiments, a gate electrode 7 having a Schottky property is formed as shown in FIG. 3E, and an ohmic property is formed as shown in FIG. The semiconductor device is manufactured by forming the source electrode 8 and the drain electrode 9 having the same.

[0051]

As described above, according to the present invention,
After the semiconductor cap layer is dry-etched anisotropically and anisotropically with the use of a mask for determining the position of the gate electrode, and selectively anisotropically with respect to the etching stopper layer. Since the semiconductor cap layer is dry-etched to cause desired side etching, the distance between the gate electrode end and the recess end can be controlled and manufactured when the recess and the gate electrode are formed in a self-aligned manner.

That is, according to the present invention, the isotropic etching time can be reduced and the controllability of the side etching amount can be improved as compared with the case where isotropic etching is performed from the beginning to cause side etching. As a result, the controllability of the distance between the gate electrode end and the recess end can be improved, and an FET having designed characteristics can be manufactured with a high yield.

[Brief description of the drawings]

FIGS. 1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to a first embodiment of the present invention in the order of steps;

FIGS. 2A to 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to a second embodiment of the present invention in the order of steps, illustrating the method.

FIGS. 3A to 3C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to a third embodiment of the present invention in the order of steps;

FIG. 4 is a cross-sectional view of a device for illustrating an example of a conventional method for manufacturing a semiconductor device, which is shown in the order of steps.

FIG. 5 is a cross-sectional view of a device in order of process for explaining another example of a conventional method of manufacturing a semiconductor device.

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate (GaAs substrate) 2 etching stopper layer (AlGaAs layer) 3 semiconductor cap layer (GaAs layer) 4 insulating film (SiO ₂ ) 5 sidewall deposit 6 recess 7 gate electrode 8 source electrode 9 drain electrode 10 sidewall oxide film

Claims (6)

[Claims] A first step of sequentially laminating an etching stopper layer and a semiconductor layer on a semiconductor substrate; a second step of forming an insulating film having an opening formed on the semiconductor layer; A third step of etching the semiconductor layer anisotropically and selectively with respect to the etching stopper layer using a film as a mask, and selectively with respect to the etching stopper layer using the insulating film as a mask; And a fourth step of isotropically etching the semiconductor layer to produce a desired side etching; and a fifth step of forming a gate electrode using the insulating film as a positioning mask. Semiconductor device manufacturing method. A first step of sequentially laminating an etching stopper layer and a semiconductor layer on a semiconductor substrate; a second step of forming an insulating film having an opening formed on the semiconductor layer; A third step of etching the semiconductor layer selectively and anisotropically with respect to the etching stopper layer using a film as a mask, and removing a deposit attached to a sidewall of the semiconductor layer in the third step. A fourth step of removing, and a fifth step of selectively and isotropically etching the semiconductor layer using the insulating film as a mask with respect to the etching stopper layer to cause desired side etching. Forming a gate electrode using the insulating film as a positioning mask. A first step of sequentially stacking an etching stopper layer and a semiconductor layer on a semiconductor substrate; a second step of forming an insulating film having an opening formed on the semiconductor layer; A third step of etching the semiconductor layer selectively and anisotropically with respect to the etching stopper layer using a film as a mask, and removing a deposit attached to a sidewall of the semiconductor layer in the third step. A fourth step of removing, and a fifth step of selectively and isotropically etching the semiconductor layer using the insulating film as a mask with respect to the etching stopper layer to cause desired side etching. A sixth step of forming a side wall insulating film on a side wall of the semiconductor layer; and a seventh step of forming a gate electrode using the insulating film as a positioning mask. Method. 4. The method of manufacturing a semiconductor device according to claim 2, wherein, in the step of removing the deposits, the entire surface is irradiated with plasma by using a hydrogen gas in a device for generating plasma discharge. . 5. The semiconductor device according to claim 2, wherein, in the step of removing the deposit, plasma irradiation is performed on the entire surface by using a gas containing at least fluorine in a device that generates plasma discharge. Manufacturing method. 6. The semiconductor substrate is a compound semiconductor substrate, and in the anisotropic etching, the selectivity between the constituent material of the etching stopper layer and the constituent material of the semiconductor layer is one.
00 or more can be realized, and performed under the condition that the semiconductor layer can be anisotropically etched.
4. The method according to claim 1, wherein a selective ratio of a constituent material of the etching stopper layer to a constituent material of the semiconductor layer is 100 or more, and the semiconductor layer is isotropically etched. 13. The method of manufacturing a semiconductor device according to claim 1.