JPH11134888A - Decoder circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a decoder circuit in which data can be erased selectively by a method wherein a first level shift circuit in which a power-supply voltage and the output of a negative high-voltage generation circuit in a write operation are changed over so as to be output on the basis of an input address signal is provided and a second level shift circuit in which the output of a positive high-voltage changeover circuit in a read operation and an erasure operation by the output of the circuit and a negative high-voltage generation circuit are changed over is provided. SOLUTION: A control signal (at a negative logic) 112 in a write operation P becomes a power supply voltage Vdd in an erasure operation E and a read operation R, and it becomes 0 V in the write operation P. A control signal (at a positive logic) 113 in the write operation P becomes 0 V in the erasure operation E and the write operation P, and it becomes the power-supply voltage Vdd in the write operation P. The output of a level shift circuit 108 changes over the power-supply voltage Vdd or the output 111 of a negative high-voltage generation circuit so as to be output according to the erasure operation E, the write operation P and the read operation R. A level shift circuit 107 receives the output, and it changes over a changeover circuit 106 and the negative high-voltage generation circuit 111 in the write operation P.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decoder circuit for controlling a voltage of a memory cell array, and more particularly to a decoder circuit for controlling a word line voltage of a memory cell constituting a memory cell array.

[0002]

2. Description of the Related Art FIG. 6 shows a conventional decoder circuit. Hereinafter, the configuration of the circuit shown in FIG. 6 will be described together with the operation. First, to correspond to the selected word line 608 at the time of reading, the gate inputs S1 to S3 of the NAND gate 601 are used.
To 5 V, and the output is set to 0 V. This allows
The output of the P-channel transistor 602 is turned on, and the output Vrdec (5v) 611 of the positive high voltage switching circuit is applied to the gate of the triple well high withstand voltage N-channel transistor 604 through the connection line 609. At this time, since the predecoder output 610 is 5 V as apparent from Table 1 showing the applied voltage table in each operation, the N-channel transistor 604 is turned off. On the other hand, the P-channel transistor 605 is turned on when the output of the NAND gate 601 is applied to the gate through the connection point 607 and the potential 5 of the predecoder output 610 is applied to the word line 608.
v is output via the P-channel transistor 605.

[0003]

[Table 1]

On the other hand, NAND corresponding to an unselected word line
Gate inputs S1 to S3 are the same as the selected word line 5
As a result, the output of the P-channel transistor 602 is turned on, and 5 V of the output Vrdec of the positive / high voltage switching circuit is applied to the gate of the triple well high withstand voltage N-channel transistor 604, as in the above-described read operation. However, at this time, since the output of the predecoder is 0 V, the transistor 604 is turned on. On the other hand, the P-channel transistor 605 is connected to the NAND gate 601.
And the predecoder output 610 turns off, and the potential 0 of the predecoder output 610 is applied to the word line 608.
v is output via the P-channel transistor 604.

[0005] The operation at the time of writing is the same as that at the time of reading, but the positive potential becomes a high potential of 10.5 V. N when erasing
5V is applied to the inputs S1 to S3 of the gate of the AND gate 601, and the output is set to 0V. At this time, the negative high voltage Vb
b612 is −10 V, and the positive high voltage Vrdec is 0 V
Therefore, the high breakdown voltage N-channel transistor 603
Is turned on, the P-channel transistor 602 is turned off, and the high breakdown voltage P-channel transistor 604 is turned off. Further, a high breakdown voltage P-channel transistor 605
Is off, and the triple well high voltage N-channel transistor 606 is on.

Thus, the negative high voltage Vbb (-10 V)
612 will be applied to word line 608.

[0007]

In the above configuration, a logic cell (NAND gate 601) is used because a high voltage of 10.5 V is used at the time of writing as a selection signal.
Also needs to be configured with a high breakdown voltage transistor, and a circuit for supplying a voltage to the predecoder output 610, the output 611 of the positive high voltage switching circuit, and the negative high voltage Vbb output 612 also needs a high breakdown voltage transistor. Become. A high breakdown voltage transistor has a smaller current supply capability than a normal transistor, and thus tends to have a lower access speed at the time of reading. If the amount of current is increased, the area of the decoder section increases. In the case of performing selective erasing at the time of erasing, a configuration for switching the selected word line potential (-10 V in this case) from 0 V to -10 V is required inside the above-described logic cell, and a configuration of a voltage switching circuit for performing this type of switching is required. Difficult, plus 10.5v
A transistor that can withstand a change of from 10 V to 10 V has a problem that the disadvantage in cost is increased.

The present invention has been proposed in view of the above problems. When a decoder circuit is composed of only high-voltage transistors, the number of peripheral control circuits is reduced by using two levels of level shift circuits. An object of the present invention is to suppress an increase in area and enable selective erasure. In addition, a read / erase voltage supply circuit (or a read / write voltage supply circuit) that handles a relatively low voltage is separated from a write / read voltage supply circuit (or an erase voltage supply circuit), so that a read / erase voltage supply circuit is provided. It is an object of the present invention to realize a circuit (a voltage supply circuit for reading / writing) with low breakdown voltage transistors to realize high-speed read access.

[0009]

According to a first aspect of the present invention, there is provided a decoder circuit for a word line of a two-dimensionally arranged memory cell array, based on an input address signal for determining selection or non-selection of the word line. , A decoder circuit for supplying an operating voltage corresponding to erasing, writing, and reading, wherein the first circuit switches between a power supply voltage and an output of a negative high voltage generating circuit at the time of writing based on the input address signal and outputs the first voltage. And the output of the positive high voltage switching circuit at the time of reading and erasing and the output of the negative high voltage generating circuit at the time of writing based on the output of the first level shifting circuit. A second level shift circuit, which is turned on at least at the time of reading and erasing based on an output of the second level shift circuit to supply a positive high voltage The read voltage and the erase potential are supplied to the word line from the voltage switching circuit, and the write voltage is supplied to the word line from the voltage switching circuit that is turned on at least at the time of writing and supplies a high negative voltage based on the output of the second level shift circuit. A driver circuit to be supplied and a transfer gate element connected to the input side of the first level shift circuit for inputting an input address signal and inverting logic at the time of writing.

According to the decoder circuit of the first aspect, by using two stages of the level shift circuit, the number of voltage switching circuits can be reduced, selective erasing can be performed, and the circuit area can be reduced. Through the transfer gate element that inverts the logic at the time of writing to the address input, decoding can be performed with the same logic in each of the erasing, writing, and reading modes.

According to a second aspect of the present invention, the decoder circuit performs erasing, writing, and erasing with respect to a word line of a memory cell array arranged two-dimensionally based on an input address signal which determines selection / non-selection of the word line. A third level shift circuit for switching between a power supply voltage and an output of a negative high voltage generation circuit at the time of writing based on an input address signal, and a third level shift circuit; A first driver circuit for receiving an inverted output of the third level shift circuit and inverting and outputting a power supply voltage and an output of a negative high voltage generating circuit at the time of writing; and a source connected to an output of the first driver circuit A first N-channel transistor having a bulk and a gate connected to a ground potential, a drain connected to a word line, and a source and a bulk connected to a ground potential Is a gate connected to an output of the first driver circuit, a second having a drain connected to the word line
N-channel transistor, a fourth level shift circuit for switching between the output of the positive high voltage generation circuit at the time of reading and erasing and a ground potential based on an input address signal, and a fourth level shift circuit A non-inverted output, and a second driver circuit for inverting and outputting the output of the positive high-voltage switching circuit and the ground potential at the time of reading and erasing; a source and a bulk connected to a word line; A third N-channel transistor connected to an output of a voltage switching circuit for switching between a high voltage and a negative high voltage for writing, and having a drain connected to an output of a second driver circuit.

According to the decoder circuit of the second aspect, the same effect as that of the first aspect is obtained. According to a third aspect of the present invention, in the decoder circuit, the drain is connected to a word line and the gate is set to a positive high voltage and a negative high voltage for writing in place of the third N-channel transistor according to the second aspect. A P-channel transistor is provided which is connected to the output of the switching circuit, and whose source and bulk are connected to the output of the second driver circuit.

According to the decoder circuit of the third aspect, the same effect as that of the second aspect is obtained. According to a fourth aspect of the present invention, there is provided a decoder circuit which applies a positive high voltage to a word line at the time of writing, instead of the voltage applied to the word line at the time of writing and erasing according to the first, second or third aspect. , A high negative voltage is applied to the word line at the time of erasing.

According to the decoder circuit of the present invention, even if a positive voltage is used at the time of writing and reading and a negative voltage is used at the time of erasing, the positive voltage handled at the time of writing does not need to be so high. There is an effect similar to that of claim 1, claim 2 or claim 3. According to a fifth aspect of the present invention, in the decoder circuit according to the first aspect, a level shift circuit that switches and outputs an output of a positive high voltage generation circuit and a ground potential based on each of erasing, writing, and reading mode signals; And the bulk connected to the output of the positive high voltage generating circuit, the gate connected to the non-inverting output of the level shift circuit, and the drain connected to the output of the positive high voltage switching circuit.
Voltage switching comprising a channel transistor and an N-channel transistor having a source and bulk connected to ground potential, a gate connected to the non-inverting output of the level shift circuit, and a drain connected to the output of the positive high voltage switching circuit. It has a circuit.

According to the decoder circuit of the fifth aspect, the same effect as that of the first aspect is obtained. According to a sixth aspect of the present invention, in the decoder circuit according to the second aspect, a fifth level shift circuit that switches and outputs the output of the positive high voltage generation circuit and the ground potential based on each of the erasing, writing, and reading mode signals. , A source and a bulk connected to the output of the positive high voltage generation circuit, a gate connected to the non-inverting output of the fifth level shift circuit, and a drain connected to the gate of the third N-channel transistor. A channel transistor, a sixth level shift circuit for switching and outputting a power supply voltage and an output of a negative high voltage generation circuit based on each mode signal, and a source and a bulk connected to an output of the negative high voltage generation circuit A fourth N-channel transistor having a gate connected to the inverted output of the sixth level shift circuit, a drain connected to the ground potential, and a gate connected to the sixth level. The connected source and bulk to the normal output of the shift circuit and a fifth N-channel transistor connected to the drain of the fourth N-channel transistor, the source and the bulk fifth
A sixth N-channel transistor connected to the source and the bulk of the N-channel transistor, the gate is connected to the ground potential, and the drain is connected to the gate of the third N-channel transistor
A voltage switching circuit having a channel transistor is provided.

According to the decoder circuit of the sixth aspect, in addition to the same effects as those of the second aspect, the voltage supply circuit for erasing and reading for handling a positive voltage and the voltage supply circuit for writing for handling a negative high voltage are separated. As a result, even if a positive high voltage is used as the erasing voltage, the voltage at the time of writing is not set so high (for example, about 5 V), so that the speed at the time of reading and the circuit area can be reduced.

According to a seventh aspect of the present invention, there is provided a decoder circuit.
Instead of the third N-channel transistor described, the drain is connected to a word line, the gate is connected to the output of a voltage switching circuit between a positive high voltage and a negative high voltage for writing, and the source and bulk are connected. A P-channel transistor connected to the output of the second driver circuit is provided.

According to the decoder circuit of the seventh aspect, the same effect as that of the sixth aspect is obtained. The decoder circuit according to claim 8 applies a positive high voltage to the word line at the time of writing, instead of the voltage applied to the word line at the time of writing and erasing according to claim 5, 6, or 7. , A high negative voltage is applied to the word line at the time of erasing.

According to the decoder circuit of the eighth aspect, the same effect as that of the fifth, sixth or seventh aspect is obtained.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) A first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a circuit diagram of a circuit according to a first embodiment of the present invention, and the configuration and operation will be described below. The level shift circuit 10
7, 108 are publicly known, and the description is omitted here.

In FIG. 1, a decoder circuit erases and erases a word line 103 of a two-dimensionally arranged memory cell array 101 based on an input address signal 110 which determines selection or non-selection of the word line 103. writing,
And an operating voltage corresponding to reading. The level shift circuit 108 supplies the power supply voltage V according to selection and non-selection.
Input address signal 11 composed of a combination of dd and 0v
0 is input via the transfer gate element 109 (the address signal 110 is selected at 0 V in each of the erase E, write P, and read R modes, and is not selected at the power supply voltage Vdd). The transfer gate element 109 inverts the logic at the time of writing. The transfer gate element 109 prevents selection by the power supply voltage Vdd and non-selection by 0 V only during writing in which a negative voltage is applied to the word line 103. Thus, the same logic (0 V in all modes of erase E, write P, and read R)
, And non-selection with the power supply voltage Vdd). Reference numeral 112 denotes a control signal (negative logic) at the time of writing, which becomes the power supply voltage Vdd at the time of erasing E and reading R, and becomes 0 V at the time of writing P. Reference numeral 113 denotes a write control signal (positive logic), which is 0 at the time of erasing E and at the time of reading R.
V and the power supply voltage Vdd at the time of writing P.

As a result, the output of the level shift circuit 108 is either the power supply voltage Vdd or the output 111 of the negative high voltage generation circuit in accordance with the erase E, write P, and read R.
(Erase E, 0 V at read R, and negative high voltage Vbb at write P. That is, the level shift circuit 108 selects the power supply voltage Vd based on the input address signal.
d and the output 111 of the negative high voltage generating circuit at the time of writing are switched and output.

Upon receiving the output of the level shift circuit 108,
The level shift circuit 107 outputs one of the output 106 of the positive high voltage switching circuit (Vpp2 during erasing, 0v during writing, and Vpr during reading) and the output 111 of the negative high voltage generating circuit in accordance with erasing E, writing P, and reading R. Output voltage. That is, based on the output of the level shift circuit 108, the output 106 of the positive high voltage switching circuit at the time of reading R and erasing E and the output 111 of the negative high voltage generating circuit at the time of writing P are switched and output.

Upon receiving the output of the level shift circuit 107,
The driver circuit 105 outputs the output 10 of the positive high voltage switching circuit.
6 or the output 111 of the negative high voltage generation circuit. The driver circuit 105 has an inverter configuration in which the drains of the high-breakdown-voltage P-channel transistor and the N-channel transistor are connected to each other, and the output 106 of the positive / high-voltage switching circuit is connected to the source and bulk of the P-channel transistor. The output 111 of the negative high voltage generation circuit is connected to the source and the bulk of the N-channel transistor.

According to the above configuration, the output of the level shift circuit 107 is 0 V corresponding to the selected word line at the time of erasing E, so that the P-channel transistor is turned on and the N-channel transistor is turned off to switch the positive high voltage. The positive high voltage Vpp2 of the output 106 of the circuit is output to the word line 103. Conversely, the output of the level shift circuit 107 is changed to the positive high voltage Vpp2 corresponding to the non-selected word line at the time of erasing E.
Therefore, the P-channel transistor is turned off and the N-channel transistor is turned on, and the output 111 (0v) of the negative high voltage generation circuit is output to the word line 103.

The output of the level shift circuit 107 is 0 V corresponding to the selected word line at the time of writing P.
At this time, since the output 106 of the positive high voltage switching circuit is 0V and the output 111 of the negative high voltage generating circuit is the negative high voltage Vbb, the P-channel transistor is turned off and the N-channel transistor is turned on to generate a negative high voltage. The output 111 of the circuit, that is, the negative high voltage Vbb is output to the word line 103. Conversely, the output of the level shift circuit 107 is set to the negative high voltage Vbb corresponding to the non-selected word line at the time of writing P.
Therefore, the P-channel transistor is turned on and the N-channel transistor is turned off, and the output 106 of the positive / high voltage switching circuit, that is, 0 V is output to the word line 103.

Furthermore, since the output of the level shift circuit 107 is 0 V corresponding to the selected word line at the time of reading R, the P-channel transistor is turned on, the N-channel transistor is turned off, and the positive high voltage switching circuit 1
06, that is, the read voltage Vpr is applied to the word line 10
3 is output. Conversely, since the output of the level shift circuit 107 is the read voltage Vpr corresponding to the unselected word line at the time of the read R, the P-channel transistor is turned off, the N-channel transistor is turned on, and the negative high voltage generation circuit Of the word line 103
Is output to

Reference numeral 101 denotes a memory cell array, 102 denotes a memory cell, and 104 denotes an output voltage table of the word line 103 in each mode. As described above, with this circuit configuration,
The output of the driver circuit 105 at the time of erasing is level-shifted to Vpp2 / 0v in accordance with selection / non-selection,
Selective erasure becomes possible. Furthermore, the circuit configuration is simplified,
The circuit area can be reduced.

Although the above is described in the FN writing / FN erasing method, the voltages applied to the word line 103 during writing and erasing are opposite (positive high voltage on the word line during writing, negative high on the word line during erasing). CH to which voltage is applied)
In the case of the E writing / FN erasing method, this circuit can be applied by replacing the above operations of writing and erasing.

(Second Embodiment) A second embodiment of the present invention will be described with reference to FIG. FIG. 2 shows a second embodiment of the present invention.
FIG. 9 is a circuit diagram of a circuit according to the second embodiment, and its configuration and operation will be described below. Since the level shift circuits 201 and 202 are publicly known, the description is omitted here.

In FIG. 2, power supply voltages Vdd and 0V are applied to level shift circuits 201 and 202 according to selection and non-selection.
(The address signal 208 is selected at 0 V in each mode of erase E, write P, and read R, and is not selected at Vdd). As a result, the output of the level shift circuit 201 is either the power supply voltage Vdd according to the erase E, the write P, and the read R, or the output 111 of the negative high voltage generation circuit (erase E, read R at 0 v, write P at Vbb). Will choose. That is, based on the input address signal 208, the power supply voltage Vdd and the output 1 of the negative high voltage
11 and output.

Upon receiving the output of the level shift circuit 201,
The driver circuit 203 selects either the power supply voltage or the output 111 of the negative high voltage generation circuit. The driver circuit 203 includes a high-breakdown-voltage P-channel transistor and an N-channel transistor.
An inverter configuration in which the drains of the channel transistors are connected to each other, and a power supply voltage Vdd is connected to the source and the bulk of the P-channel transistor.
The output 111 of the negative high voltage generation circuit is connected to the source and the bulk of the channel transistor. That is, the inverted output of the level shift circuit 201 is input, and the power supply voltage Vdd and the output 11 of the negative high voltage generation circuit at the time of writing are inverted and output.

In response to the output of the driver circuit 203, the gate and bulk are connected to the ground potential, the source is connected to the output of the driver circuit 203, and the drain is connected to the word line 103.
, The N-channel transistor 205 is turned on only when a negative high voltage Vbb is output from the driver circuit 203 according to the output voltage table 209 of the driver circuit 203, and in other cases. Is turned off. Further, the drain is connected to the word line 103, the source and the bulk are connected to the ground potential, and the gate is connected to the driver circuit 20.
N-channel transistor 20 connected to the output of 3
6 supplies 0 V applied to an unselected word line at the time of writing.

As the output of the level shift circuit 202, the output 210 of the positive high voltage generation circuit or the ground potential is selected according to the erase E, write P and read R. That is, based on the input address signal 208, the output 210 of the positive high voltage
And the ground potential. Upon receiving the output of the level shift circuit 202, the driver circuit 204 selects the output 210 of the positive high voltage generation circuit or the ground potential. The driver circuit 204 has an inverter configuration in which the drains of a high-breakdown-voltage P-channel transistor and an N-channel transistor are connected to each other, and the output 210 of the positive high-voltage generation circuit is connected to the source and bulk of the P-channel transistor. Then, a ground potential is connected to the source and the bulk of the N-channel transistor. That is, the non-inverting output of the fourth level shift circuit 202 is input, and the output 210 of the positive high-voltage switching circuit at the time of reading and erasing and the ground potential are inverted and output. Reference numeral 211 denotes an output voltage table of the driver circuit 204.

In response to the output of the driver circuit 204, the source and bulk are connected to the word line 103, the drain is connected to the output of the driver circuit 204, and the gate is connected to the output 212 of the positive / negative high voltage switching circuit. When writing the negative high voltage Vbb to the word line 103 by the N-channel transistor 207, the negative high voltage Vbb is output as shown by the output 212 of the positive / negative high voltage switching circuit.
Is applied to the gate of the N-channel transistor 207 to turn off the N-channel transistor 207 and apply a positive voltage to the other word lines 103. At the time of reading R, the output 212 of the positive / negative high voltage switching circuit is applied. As shown, the positive high voltage Vpp1 (Vpp1> V
By applying (pp2>Vpr> Vdd) to the gate of the N-channel transistor 207, the voltage Vpp2 / 0v at the time of selection / non-selection at the time of erasing, and the selection / voltage at the time of reading /
The configuration is such that the voltage Vpr (Vpr> Vdd) / 0v when not selected is output to the word line 103. However, the N-channel transistor 207 in FIG. 2 has a triple well configuration because a high negative voltage is applied to the source during writing, and has a configuration in which current leakage due to forward bias is suppressed by short-circuiting the source and the bulk. ing. 213 is an output voltage table of the word line 103.

In the above decoder circuit configuration, the erasing voltages Vpp2 and Vpr are set to, for example, 5 V and 3.5, respectively.
By setting the voltage to a relatively low level of about v, the level shift circuit 202 and the driver circuit 204 in FIG. It is not necessary to use a transistor, and it is possible to use a transistor having a relatively high current supply capability of about 5 V, thereby enabling high-speed access at the time of reading.

Although the above description is made in the FN writing / FN erasing method, the voltages applied to the word lines at the time of writing and erasing are reversed (the positive and high voltages are applied to the word lines at the time of writing) as in the first embodiment. In the case of the CHE writing / FN erasing method in which a negative high voltage is applied to the word line at the time of erasing, this circuit can be applied by replacing the above-mentioned operations of writing and erasing.

(Third Embodiment) A third embodiment of the present invention will be described with reference to FIG. FIG. 3 shows a third embodiment of the present invention.
FIG. 3 shows a circuit diagram of a circuit in the embodiment of the present invention,
First, differences from FIG. 2 showing the second embodiment will be described. In FIG. 3, the source and bulk of the N-channel transistor 207 in FIG.
4, the drain is connected to the word line 103, and the gate is connected to the output 302 of the positive / negative high voltage switching circuit.
Is replaced by the P-channel transistor 301 in FIG. Other configurations are the same as those of the second embodiment.

At the time of writing P in which the negative high voltage Vbb is applied to the word line 103 by the P-channel transistor 301, the positive high voltage Vpp1 (Vpp1>Vpp2>) as shown by the output 302 of the positive / negative high voltage switching circuit.
Vpr> Vdd) to the P-channel transistor 301
To turn off the P-channel transistor 301 by applying a positive voltage to the other word lines 103, and at the time of reading R, the negative high voltage as shown by the output 302 of the positive / negative high voltage switching circuit. Voltage Vbb
Is applied to the gate of the P-channel transistor 301 to select the voltage Vpp at the time of selection / non-selection at the time of erasing E.
2 / 0v, voltage Vpr at the time of selection / non-selection at the time of reading R
(Vpr> Vdd) / 0v is output to the word line 103. However, the P channel in FIG.
Since the transistor 301 is a P-channel transistor unlike the second embodiment, there is no current leakage due to forward bias caused by application of a negative high voltage to the drain at the time of writing, and a triple well configuration is used. The configuration is not used.

With the above-described configuration, it is possible to obtain the same effects as in the second embodiment.
Although the above description is based on the FN writing / FN erasing method, the voltages applied to the word lines at the time of writing and erasing are reversed (positive high voltage at the word line at the time of writing, and at the time of erasing, as in the first embodiment). In the case of the CHE writing / FN erasing method in which a negative high voltage is applied to the word line), this circuit can be applied by replacing the above-mentioned operations of writing and erasing.

(Fourth Embodiment) A fourth embodiment of the present invention will be described with reference to FIG. FIG. 4 shows a fourth embodiment of the present invention.
FIG. 3 shows a circuit diagram of a circuit in the embodiment of the present invention,
The output node 404 of FIG. 4 is connected to the node of the output 106 of the positive high voltage switching circuit in FIG. 1, and the configuration of the circuit for switching the voltage to the node of the output 106 of the positive high voltage switching circuit in FIG. It is intended to provide a method of performing voltage switching output.

The structure and operation will be described below. Since the level shift circuit 401 is publicly known, the description is omitted here. In FIG. 4, the level shift circuit 4
To 01, a signal 405 composed of a combination of the power supply voltage Vdd and 0V is input according to each operation mode of erase E, write P, and read R. As a result, the output of the level shift circuit 401 selects the output 210 of the positive high voltage generation circuit or the ground potential according to the erase E, write P, and read R. Upon receiving the output of the level shift circuit 401, the source and the bulk are connected to the output 210 of the positive high voltage generation circuit, and the drain is connected to the output 106 (404) of the positive high voltage switching circuit of the first embodiment. The gate of the P-channel transistor 402 connected to the non-inverting output terminal of the level shift circuit 401
Gate voltage table 406 of channel transistor 402
As shown in (2), by applying 0 V to the gate of the P-channel transistor 402 at the time of erasing E and reading R, the P-channel transistor 402 is turned on, and at the time of erasing E and reading R, the positive high voltage is switched. The signal is output to the output 106 (404) of the circuit. Also write P
Sometimes, as shown in the gate voltage table 406 of the P-channel transistor 402, the power supply voltage Vdd is applied to the gate of the P-channel transistor 402, turning off the P-channel transistor 402, and at the same time, the gate of the N-channel transistor 403. Voltage is also power supply voltage V
dd, the N-channel transistor 40
3 turns on, and the output 106 (40
4) is configured to output 0v. The N-channel transistor 403 has its source and bulk connected to ground potential, its gate connected to the non-inverting output of the level shift circuit 401, and its drain connected to the output 106 (404) of the positive high voltage switching circuit. .

With the above configuration, the level shift circuit 107 shown in the first embodiment and the output of the positive / high voltage switching circuit at the time of writing to the driver circuit 105 are set to 0.
By setting v, the potential difference from the output 111 of the negative high voltage generation circuit can be reduced, and the effect that the withstand voltage of the transistor is not required to be more than ten and several volts is not required.

(Fifth Embodiment) A fifth embodiment of the present invention will be described with reference to FIG. FIG. 5 shows a fifth embodiment of the present invention.
1 is a circuit diagram of a circuit according to an embodiment. This is to connect the output node 507 of FIG. 5 to the node of the output 212 of the positive / negative high voltage switching circuit in FIG.
The output 212 node of the positive / negative high voltage switching circuit in FIG. 2 requires a circuit for switching and outputting a positive / negative high voltage. Normally, this configuration is complicated and difficult.
This can be realized by adopting the circuit method of (1).

The structure and operation will be described below. Since the level shift circuits 501 and 502 are publicly known, description thereof is omitted here. In FIG. 5, a signal 508 composed of a combination of the power supply voltages Vdd and 0v is input to the level shift circuit 501 in accordance with each operation mode of erasing E, writing P, and reading R. As a result, the output of the level shift circuit 501 selects the output 210 of the positive high voltage generation circuit or the ground potential according to the erase E, write P, and read R. In response to the output of the level shift circuit 501, the source and bulk are connected to the output of the level shift circuit 501, and the drain is connected to the output 212 (50) of the positive / negative high voltage switching circuit of the second embodiment.
7), and a P-channel transistor 503 having a gate connected to the non-inverting output of the level shift circuit 501.
By applying a positive voltage to the positive / negative high voltage switching circuit 212 (507), the P-channel transistor 503 is turned on at the time of erasing E and reading R, and the output 210 of the positive high voltage generating circuit is set to the positive / negative high voltage. Output 21 of switching circuit
2 (507) to turn off the P-channel transistor 503 at the time of writing P.

The level shift circuit 502 has erase E,
A signal 509 composed of a combination of the power supply voltage Vdd and 0 V is input according to each operation mode of the write P and the read R. As a result, the output of the level shift circuit 502 becomes the power supply voltage Vd according to the erase E, the write P, and the read R.
d or the output 111 of the negative high voltage generation circuit will be selected. Upon receiving the output of the level shift circuit 502, the source and the bulk are output to the output 111 of the negative high voltage generation circuit.
, A gate connected to the inverted output of the level shift circuit 502, a drain connected to the source and bulk of the N-channel transistor 505, a drain connected to the ground potential, and a gate connected to the level shift circuit 502. N-channel transistor 505 connected to the non-inverting output of 502; source and bulk connected to the drain of N-channel transistor 504;
(507), the gate of which is connected to the ground potential, the N-channel transistor 506 is used to apply a negative high voltage to the output 212 (507) of the positive / negative high voltage switching circuit.
By turning on 4, the negative high voltage is output to the output 212 (507) of the positive / negative high voltage switching circuit. When a positive voltage is applied during other erasing E and reading R, the gate of the N-channel transistor 506 is at the ground potential, so that the N-channel transistor 506 is turned off.

However, the N-channel transistors 504, 505, and 506 in FIG. 5 have a triple well configuration because a high negative voltage is applied to the source or the drain at the time of writing. The configuration is such that current leakage is suppressed. With the above-described configuration, a positive / negative high voltage (Vpp1 / Vbb) switching circuit can be configured. Further, a positive high voltage supply circuit for erasing E and reading R, and a negative high voltage for writing P Separates the high-voltage supply circuit of Vpp1 + | Vbb | volts, thereby eliminating the need for a transistor having a high breakdown voltage of Vpp1 + | Vbb |
It is possible to configure a transistor with a high breakdown voltage of about + | Vbb | volt.

By changing the combination of the operation mode signals 508 and 509, the output 50 of the positive / negative high-voltage switching circuit described in the third embodiment is output to the output 302.
7, the same effect can be obtained. As a modification of the fifth embodiment, the third embodiment
Embodiment can be applied. The above is FN
Although described in the write / FN erase method, the first
As in the third embodiment, the voltage applied to the word line during writing and erasing is reversed (positive high voltage is applied to the word line during writing and negative high voltage is applied to the word line during erasing).
In the case of the E writing / FN erasing method, this circuit can be applied by replacing the above operations of writing and erasing.

[0049]

According to the decoder circuit of the first aspect,
By using two levels of level shift circuits, the number of voltage switching circuits can be reduced, selective erasing can be performed, circuit area can be reduced, and a transfer gate element for inverting logic at the time of writing to an address input of a decoder circuit can be provided. This allows decoding in the same logic in each of the erase, write, and read modes.

According to the decoder circuit of the second aspect, the same effect as that of the first aspect is obtained. According to the decoder circuit of the third aspect, there is an effect similar to that of the second aspect. According to the decoder circuit of the present invention, even if a positive voltage is used at the time of writing and reading and a negative voltage is used at the time of erasing, the positive voltage handled at the time of writing does not need to be so high. There is an effect similar to that of the second or third aspect.

According to the decoder circuit of the fifth aspect, the same effect as that of the first aspect is obtained. According to the decoder circuit of the sixth aspect, in addition to the same effects as those of the second aspect, by separating the voltage supply circuit for erasing and reading for handling a positive voltage and the voltage supply circuit for writing for handling a negative high voltage, Even if a positive high voltage is used for the erasing voltage, the voltage at the time of writing is not set so high (for example, about 5 V).
It is possible to speed up the reading operation and reduce the circuit area.

According to the decoder circuit of the seventh aspect, the same effect as that of the sixth aspect is obtained. According to the decoder circuit of the eighth aspect, the same effects as those of the fifth, sixth, or seventh aspect are obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a decoder circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a decoder circuit according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram of a decoder circuit according to a third embodiment of the present invention.

FIG. 4 is a circuit diagram of a voltage switching circuit according to a fourth embodiment of the present invention.

FIG. 5 is a circuit diagram of a voltage switching circuit according to a fifth embodiment of the present invention.

FIG. 6 is a circuit diagram of a conventional decoder circuit.

[Explanation of symbols]

101 memory cell array 102 memory cell 103 word line 104, 213 word line (applied voltage in each mode) 105, 203, 204 driver circuit 106, 404 output of positive / high voltage switching circuit 107, 108, 201, 202, 401, 501, 5
02 level shift circuit 109 transfer gate element 110, 208 address signal 111 output of negative high voltage generation circuit 112 write control signal (negative logic) 113 write control signal (positive logic) 205, 206, 207, 403, 504, 505, 5
06 N-channel transistors 209, 211, 406 Internal node 210 Output of positive high voltage generation circuit 212, 302, 507 Output of positive / negative high voltage switching circuit 301, 402, 503 P-channel transistors 405, 508, 509 Operation mode signal

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yoichi Nishida 1006 Kazuma Kadoma, Osaka Pref.Matsushita Electric Industrial Co., Ltd. (72) Inventor Junji Michiyama 1006 Kadoma Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (8)

[Claims] An operating voltage corresponding to erasing, writing, and reading is applied to a word line of a two-dimensionally arranged memory cell array based on an input address signal that determines selection / non-selection of the word line. A first level shift circuit for switching between a power supply voltage and an output of a negative high voltage generation circuit during writing based on the input address signal, and a first level shift circuit; A second level shift circuit for switching and outputting the output of the positive high voltage switching circuit at the time of reading and erasing and the output of the negative high voltage generating circuit at the time of writing based on the output of the second level. At least at the time of reading and erasing based on the output of the shift circuit, read and erase from the high voltage switching circuit which supplies a positive high voltage when turned on. A driver circuit that supplies a potential to the word line and supplies a write voltage to the word line from a voltage switching circuit that is turned on at least during writing based on an output of the second level shift circuit and supplies the negative high voltage; A transfer gate element connected to the input side of the first level shift circuit and receiving the input address signal to invert the logic at the time of writing. 2. An operating voltage corresponding to erasing, writing, and reading is applied to a word line of a two-dimensionally arranged memory cell array based on an input address signal for selecting or unselecting the word line. A third level shift circuit for switching between a power supply voltage and an output of a negative high voltage generation circuit during writing based on the input address signal, and a third level shift circuit; A first driver circuit for receiving an inverted output of the first driver circuit and inverting and outputting a power supply voltage and an output of the negative high voltage generating circuit at the time of writing; a source connected to the output of the first driver circuit; A first N-channel transistor having a gate connected to ground potential and a drain connected to a word line; a source and bulk connected to ground potential; A second N-channel transistor connected to an output of the first driver circuit and having a drain connected to a word line; an output of a positive high voltage generation circuit for reading and erasing based on the input address signal; A fourth level shift circuit for switching and outputting a potential, and a non-inverting output of the fourth level shift circuit being inputted to invert the output of the positive high voltage switching circuit for reading and erasing and the ground potential. A second driver circuit for outputting, a source and a bulk connected to a word line, a gate connected to an output of a voltage switching circuit between a positive high voltage and a negative high voltage for writing, and a drain connected to the second A third N-channel transistor connected to the output of the driver circuit. 3. An output of a voltage switching circuit, wherein the drain is connected to a word line and the gate is switched between a positive high voltage and a negative high voltage during writing, instead of the third N-channel transistor according to claim 2. 3. The decoder circuit according to claim 2, further comprising: a P-channel transistor connected to the second driver circuit and having a source and a bulk connected to an output of the second driver circuit. 4. A positive high voltage is applied to a word line at the time of writing instead of the voltage applied to the word line at the time of writing and erasing according to claim 1, and the word at the time of erasing. Decoder circuit with negative high voltage applied to the line. 5. A level shift circuit for switching between an output of a positive high voltage generating circuit and a ground potential based on each of erasing, writing and reading mode signals, and a source and a bulk for generating said positive high voltage. A P-channel transistor having a gate connected to the output of the circuit, a gate connected to the non-inverting output of the level shift circuit, a drain connected to the output of the positive high-voltage switching circuit, a source and bulk connected to the ground potential, and a gate connected to the ground potential. 2. The decoder circuit according to claim 1, further comprising an N-channel transistor connected to a non-inverting output of said level shift circuit and having a drain connected to an output of said positive high voltage switching circuit. 6. A fifth level shift circuit for switching between an output of a positive high voltage generation circuit and a ground potential based on each of erasing, writing, and reading mode signals, and outputting a source and a bulk to said positive high voltage generating circuit. A first P-channel transistor having a gate connected to the output of the voltage generation circuit, a gate connected to the non-inverting output of the fifth level shift circuit, and a drain connected to the gate of a third N-channel transistor;
A sixth level shift circuit that switches and outputs a power supply voltage and an output of a negative high voltage generation circuit based on each of the mode signals, and a source and a bulk which are connected to the output of the negative high voltage generation circuit and have a gate connected thereto. A fourth N-channel transistor connected to the inverted output of the sixth level shift circuit; a drain connected to the ground potential; a gate connected to the non-inverted output of the sixth level shift circuit; A fifth N-channel transistor connected to a drain of the fourth N-channel transistor; a source and a bulk connected to a source and a bulk of the fifth N-channel transistor; a gate connected to a ground potential; Switching with a sixth N-channel transistor connected to the gate of the third N-channel transistor Decoder circuit according to claim 2, further comprising a circuit. 7. An output of a voltage switching circuit for connecting a drain to a word line and a gate to a positive high voltage and a negative high voltage during writing in place of the third N-channel transistor according to claim 6. 7. The decoder circuit according to claim 6, further comprising a P-channel transistor connected to the second driver circuit and having a source and a bulk connected to an output of the second driver circuit. 8. A positive high voltage is applied to a word line at the time of writing instead of the voltage applied to the word line at the time of writing and erasing according to claim 5, and the word is erased at the time of erasing. Decoder circuit with negative high voltage applied to the line.