JPH11134867A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can realize memory elements capable of reading information at a high speed, without using elements having complicated structures. SOLUTION: A basic constituent element of a semiconductor memory is composed of a memory cell 1 and light emitting diode D. The cell 1 is composed of a flip flop circuit consisting of n-MOS transistors Q1 , Q3 and source-grounded p-channel MOS transistors Q2 , Q4 , and pair of access transistors Q5 , Q6 . A negative power voltage is fed to the sources of the n-channel transistors Q1 , Q3 . The access transistors Q5 , Q6 are connected to memory nodes N1 , N2 . A switching transistor Q7 is connected to the anode of the diode D with a switching line SL connected to the gate electrode to control the continuity noncontinuity state of the transistor Q7 , thereby controlling the emission nonemission state of the diode D disposed above the memory cell 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device suitable for application to a semiconductor memory device.

[0002]

2. Description of the Related Art Conventionally, static RAM (SRAM)
In such a semiconductor memory, an address is given and information of each memory cell of the semiconductor memory is individually read in order to read information written in the semiconductor memory.

[0003]

Therefore, there is a problem that it takes an enormous amount of time to read the information written in the semiconductor memory.

In addition, a conventional optical / electronic integrated circuit (OEI)
In C), an element having a complicated structure such as a semiconductor laser was required.

It is therefore an object of the present invention to provide a semiconductor device capable of realizing a memory element capable of increasing the speed of reading information without using an element having a complicated structure.

[0006]

In order to achieve the above object, the present invention comprises a carrier traveling element and a light emitting element provided above the carrier traveling element, and the light emitting element emits light by the carrier traveling element. The semiconductor device is characterized in that it is configured to be able to perform the operation.

In the present invention, typically, the carrier transit element is made of a MIS or III-V compound semiconductor such as GaAs or a IV semiconductor such as Si.
It is composed of an FET, a MESFET, and the like.

[0008] In the present invention, typically, the light emitting element is made of GaN, InN, AlN, BN, AlGaInAs.
A layer made of a single crystal or polycrystal of a III-V compound semiconductor such as a P-based compound semiconductor, or ZnSe or Be
II such as ZnMgCdHgSSeTe-based compound semiconductor
A single crystal or polycrystalline layer of a group VI compound semiconductor, and preferably a group III-V compound constituting the light emitting element in order to set light emitted from the light emitting element to a predetermined wavelength. La, Ce, Pr, Nd, Pm, Sm, Eu, G
A rare earth element such as d, Tb, Dy, Ho, Er, Tm, Yb, and Lu is doped. Further, in the present invention, the light emitting element can be made of a group IV semiconductor such as porous Si using, for example, a quantum size effect or an oxide. In the present invention, an organic electroluminescence (EL) element made of a polymer compound can be used as the light emitting element.

In the present invention, preferably, the light emitting element has a light output from the light emitting element which is the minimum output that can be observed from the outside, and which consumes less carrier traveling element. It is configured not to exceed the power.

According to the present invention having the above-described structure, by forming a memory cell with a carrier traveling element, a light-emitting element can emit light in accordance with information stored in the memory cell. , Reading can be performed in a short time.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. In all the drawings of the embodiments, the same or corresponding portions are denoted by the same reference numerals.

First, a first embodiment of the present invention will be described. FIG. 1 shows a circuit configuration of a basic component of the semiconductor memory according to the first embodiment.

As shown in FIG. 1, the basic components of the semiconductor memory according to the first embodiment include a memory cell 1 and a light emitting diode D. Memory cell 1
Are an n-channel MOS transistor Q ₁ and a p-channel M
A CMOS inverter comprising an OS transistor Q ₂ ,
A pair of access for and n-channel MOS transistors Q ₃ and p channel MOS transistor Q ₄ Metropolitan flip-flop circuit of the configuration in which one input of the CMOS inverter is connected to the other output consisting of data with the outside cells interact It comprises transistors Q ₅ and Q ₆ . The sources of the p-channel MOS transistors Q ₂ and Q ₄ are grounded, and the sources of the n-channel MOS transistors Q ₁ and Q ₃ are supplied with a predetermined negative power supply voltage. Access transistors Q ₅ and Q ₆ are connected to the storage nodes N ₁ and N ₂ of the memory cell 1, respectively. In addition, the anode of the light emitting diode D, for example a switching transistor Q ₇ consisting of n-channel MOS transistor and is connected, the conduction of switching transistor Q ₇ in response to the voltage supplied to its gate electrode connected to a switch line SL By controlling / non-conduction, light emission / non-light emission of the light emitting diode D is controlled. WL is a word line, BL, B
L 'indicates a bit line.

In the basic constituent element of the semiconductor memory according to the first embodiment configured as described above, information “1” or “0” is written in the memory cell 1 and the information of the storage node N ₁ If the potential is in the low level, when the switching transistor Q ₇ to the conductive state by supplying a high level signal to the switch line SL, and the light emitting diode D voltage is applied in the forward direction to emit light.
Conversely, when the potential of the storage node N ₁ of the memory cell 1 is at a high level, even if the switching transistor Q ₇ to the conductive state by supplying a high level signal to the switch line SL, and the light-emitting diode D No voltage is applied, no light is emitted, and no light is emitted.

FIG. 2 is a plan view of a semiconductor memory in which the basic constituent elements configured as described above are integrated in a two-dimensional array. In this case, the wavelengths of the light emitted from the individual basic constituent elements are the same wavelength.

FIG. 3 shows a main part of the semiconductor memory.
Mainly, n-channel MOS transistor Q of memory cell 1
_1, p indicates a portion of the channel MOS transistors Q ₂ and light-emitting diodes D.

As shown in FIGS. 2 and 3, in the semiconductor memory according to the first embodiment, for example, an n-type S
A field insulating film 3 such as a SiO ₂ film is selectively provided on a surface of a semiconductor substrate 2 such as an i-substrate, thereby separating elements.

[0018] The upper portion of the semiconductor substrate 2 parts of n-channel MOS transistors Q _1, p-type well region 4 is provided. On the surface of the active region surrounded by the field insulating film 3, a gate insulating film 5 such as a SiO ₂ film is provided. G ₁ denotes a gate electrode of the n-channel MOS transistor Q _1. The gate electrode G ₁ is formed by a polycrystalline Si film whose resistance is reduced heavily doped, for example, impurities. Also, n-channel MOS
During active region surrounded by the field insulating film 3 in the transistor Q ₁ is, for example, n ⁺ -type diffusion region 6 and 7 constituting the source / drain region is provided. By the gate electrode G ₁ and the diffusion region 6, 7, n-channel MOS transistor Q ₁ is being configured.

On the other hand, p-channel MOS transistor Q ₂
A gate insulating film 8 such as a SiO ₂ film is provided on the surface of the active region surrounded by the field insulating film 3 in the portion. G ₂ is a p-channel MOS transistor Q ₂
Is shown. The gate electrode G ₂ is an n-channel MO
S transistor similar polycrystalline S and gate electrode G ₁ for Q ₁
It is formed by an i film. Further, in the active region surrounded by the field insulating film 3 in the p-channel MOS transistors Q _2, for example p ⁺ -type diffusion region 9 and 10 constituting the source / drain region is provided. The gate electrode G ₂ and the diffusion regions 9 and 10 form a p-channel MOS transistor Q ₂ .

Reference numeral 11 denotes gate electrodes G ₁ , G ₂
5 shows a wiring 11 having a predetermined shape formed of the same polycrystalline Si film as that of FIG.

On the semiconductor substrate 2 on which the n-channel MOS transistor Q ₁ , the p-channel MOS transistor Q _{2 and the} like are provided, an interlayer insulating film 12 such as a SiO ₂ film is provided. Contact holes C ₁ , C ₂ , C ₃ , and C ₄ are formed in portions of the film 12 above the n ⁺ -type diffusion regions 6 and 7 and above the p ⁺ -type diffusion regions 9 and 10, respectively. I have. An impurity-doped polycrystalline Si film 13 having a predetermined wiring shape is provided so as to fill the insides of these contact holes C _{1 to} C ₄ . Further, an interlayer insulating film 14 such as a SiO ₂ film is provided so as to cover the interlayer insulating film 12 and the polycrystalline Si film 13.

On the interlayer insulating film 14, a polycrystalline Si film 15 of a predetermined shape doped with impurities is provided. Further, the contact hole C ₅ is formed in the portion of the interlayer insulating film 12, 14 on the wire 11. Inside the contact holes C _5, are embedded polycrystalline Si film 15, thereby, the polycrystalline Si film 15 and the wiring 11 are electrically connected.

On the polycrystalline Si film 15, for example, n
A light-emitting layer 16 in which a p-type AlGaN layer, an InGaN layer, and a p-type AlGaN layer are sequentially stacked is provided. On the light emitting layer 16, a polycrystalline Si film 17 doped with impurities and having the same shape as the light emitting layer 16 is provided. The polycrystalline Si film 17 is formed sufficiently thin so as to be transparent to light emitted from the light emitting diode D, and specifically has a thickness of, for example, 10 to 30 nm.
Further, the light emitting layer 16 and the polycrystalline Si film 17
As shown in FIG. 2, it has a rectangular shape, for example.
The light emitting diode D is constituted by the polycrystalline Si films 15 and 17 and the light emitting layer 16.
Are a lower electrode (anode electrode) and an upper electrode (cathode electrode), respectively. Then, these polycrystalline Si films 17
By applying a voltage between the light emitting layer 16 and the polycrystalline Si film 15, light having a predetermined wavelength selected from a range of, for example, about 300 to 800 nm can be emitted from the light emitting layer 16. In general, in a light-emitting element composed of an N-based compound semiconductor, by doping a light-emitting N-based compound semiconductor layer with a rare-earth element, about 300 to 10
The emission wavelength can be changed in the range of 00 nm. Therefore, if necessary, by doping the InGaN layer in the light emitting layer 16 with a rare earth element, light emission of a predetermined wavelength selected from the range of about 300 to 800 nm can be obtained from the light emitting layer 16. Further, by doping the InGaN layer with a rare earth element, light emission having a narrow half width and a sharp spectrum can be obtained. Also, the emission wavelength can be changed by changing the In composition of the InGaN layer.

The entire surface of the polycrystalline Si film 17 and the light emitting layer 16 is covered with an insulating film 18 such as a SiN film.
Covered with. A contact hole C ₆ is formed in the portion of the polycrystalline Si film 13, the interlayer insulating film 14 and the insulating film 18 on the n ⁺ type diffusion layer 7. Inside the contact holes C _6, a polycrystalline Si plug 19
Is embedded, and the polycrystalline Si film 17 and the n ⁺ -type diffusion region 7 are electrically connected via the polycrystalline Si plug 19.

The structure of the n-channel MOS transistor Q ₃ and the p-channel MOS transistor Q _{4 not} shown in FIG.
The configuration is the same as that of transistor Q ₁ and p-channel MOS transistor Q ₂ .

Next, the method for fabricating the semiconductor memory according to the first embodiment will be explained.

In the first embodiment, first, n
The semiconductor substrate 2 is selectively thermally oxidized by, for example, a LOCOS method to form a field insulating film 3 and perform element isolation. Thereafter, a p-type well region 4 is formed by selectively ion-implanting a p-type impurity such as boron (B) into a predetermined portion in the semiconductor substrate 2.

Next, gate insulating films 5 and 8 made of a SiO ₂ film are formed on the surface of the active region surrounded by the field insulating film 3 by, for example, a thermal oxidation method. Next, after a polycrystalline Si film is formed on the entire surface by, for example, a CVD method, an impurity is doped into the polycrystalline Si film by, for example, an ion implantation method or a thermal diffusion method. Thereafter, the gate electrodes G ₁ and G ₂ are formed by patterning the polycrystalline Si film into a predetermined shape, and the wiring 11 is formed. Next, n ⁺ -type diffusion regions 6 and 7 are formed by selectively ion-implanting n-type impurities such as arsenic (As). Next, p ⁺ -type diffusion regions 9 and 10 are formed by selectively implanting, for example, BF ₂ ions into the active region surrounded by the field insulating film 3.

Next, an interlayer insulating film 12 made of, for example, a SiO ₂ film is formed on the entire surface by, eg, CVD. Next, portions of the interlayer insulating film 12 above the n ⁺ -type diffusion regions 6 and 7 and the p ⁺ -type diffusion regions 9 and 10 are etched to form contact holes C ₁ , C ₂ and C ₂ , respectively.
_3, to form a C _4.

Next, by forming a polycrystalline Si film 13 on the entire surface by, for example, the CVD method, the contact holes C _{1 to} C ₄ are filled with polycrystalline Si. Next, impurities are ion-implanted into the polycrystalline Si film 13 to reduce the resistance, and then the polycrystalline Si film 13 is patterned into a predetermined wiring shape.

Next, for example, a CVD method is used to cover the polycrystalline Si film 13 and the interlayer insulating film 12 so as to cover the Si film.
An interlayer insulating film 14 made of an O ₂ film is formed. Next, an interlayer insulating film 12, 14 of the parts on the wiring 11 by etching, to form contact holes C _5. next,
The polycrystalline Si film 15 is formed on the entire surface by the CVD method, to fill the inside of the contact hole C ₅ polycrystalline Si. Next, after the impurity is ion-implanted into the polycrystalline Si film 15 to reduce the resistance, the polycrystalline Si film 15 is patterned into a predetermined shape.

Next, the impurities in all the diffusion regions are activated by heat treatment in an atmosphere of an inert gas such as N ₂ .

Next, for example, metal organic chemical vapor deposition (MO)
The light emitting layer 16 is formed by sequentially growing a p-type AlGaN film, an InGaN film, and an n-type AlGaN film on the polycrystalline Si film 15 by a CVD method, a vacuum deposition method, a sputtering method, or the like. Next, after forming a polycrystalline Si film 17 on the light emitting layer 16 by, for example, a CVD method, the polycrystalline Si film 17 and the light emitting layer 16 are patterned into, for example, a rectangular shape. Next, an insulating film 18 made of, for example, a SiN film is formed on the entire surface by, for example, a plasma CVD method.

Next, a contact hole C ₆ is formed by etching the polycrystalline Si film 13, the interlayer insulating film 14, and the insulating film 18 above the n ⁺ type diffusion region 7, and then the contact hole C ₆ is formed. Polycrystalline S inside C ₆
a polycrystalline Si plug 19 connected to the i-film 17
To form Thereafter, an insulating film 18 is further formed.

Through the above steps, the intended semiconductor memory is manufactured.

FIG. 4 is a plan view showing a package of the semiconductor memory according to the first embodiment configured as described above. As shown in FIG. 4, when the semiconductor memory according to the first embodiment is packaged, a glass window 22 is provided on the top of the package 21, and the basic components of the semiconductor memory are provided through the glass window 22. The light emitted from the light-emitting diode D provided for each device can be observed from the outside.

Next, the write method and read method of the semiconductor memory configured as described above according to the first embodiment will be specifically described. Here, as shown in FIG. 2, the addresses of the basic constituent elements constituting the semiconductor memory are (i, j), where i is the row number and j is the column number.

The writing of information into the semiconductor memory is performed as follows.
As in the case of the conventional SRAM, the process is performed for each basic component by designating the address (i, j). Then, in accordance with the written information, the storage node N ₁ of the individual basic components becomes a low level or high level.

[0039] When reading the information written in the semiconductor memory, first, the switching transistor Q ₇ of all the basic components in a conductive state. At this time, light is emitted from the semiconductor memory according to the information stored in each memory cell 1. Specifically, the light emitting diode D of the basic component memory node N ₁ of the memory cell 1 is at a low level to emit light. On the other hand, the light emitting diode D of the basic component memory node N ₁ of the memory cell 1 is at a high level to maintain the non-emission state, no light.

Then, the row number i of the elementary element emitting light is determined by, for example, using a CCD image pickup element.
Dimensionally detect. Thereby, in the semiconductor memory, a row in which at least one basic component emits light is distinguished from a row in which at least one basic component emits no light. On the other hand, by the storage node N ₁ of the memory cell 1 is detected by an electrical signal a position along the column direction of the basic component is a low level, to distinguish the column number j. As described above, the storage node N ₁ of the memory cell 1 in the address (i, j) detects whether low level or high level, reads the information written in the semiconductor memory. As described above, the distinction based on the electric signal is based on the address (i, j).
Since only column number j is available, information written two-dimensionally in the semiconductor memory can be read out by one-dimensional discrimination based on electric signals.

As described above, according to the semiconductor memory of the first embodiment, the information written in the semiconductor memory is read out by utilizing the light emission from the semiconductor memory. The speed of reading information can be improved as compared with the case of reading information from the SRAM. Further, by using the light emitting diode D as the light emitting element, a semiconductor memory which can emit light can be obtained without using an element having a complicated structure.

Next, a semiconductor memory according to a second embodiment of the present invention will be described.

First, in the semiconductor memory according to the second embodiment, the wavelengths of light emitted from the light emitting diodes D of the individual basic components are different from each other depending on the row number i of the address (i, j). I do. That is, the wavelengths of light emitted from the light emitting diodes D of the plurality of basic constituent elements having the same row number i and different column numbers j are the same. Such basic components are arranged such that, for example, as the row number i increases, the wavelength of light emission increases, and the range of the wavelength of light emitted from the light emitting diode D of the basic component is: 4
It is in the range of 00-800 nm. The address (i,
The wavelengths of the light emitted from the two basic constituent elements having the continuous row number i in j) are set so as to differ from each other by at least 0.01 nm or more. Here, the emission wavelength of the light emitting diode D is controlled by changing the type and amount of the rare earth element doped into the InGaN layer of the light emitting layer 16. Others are the same as in the first embodiment.

Next, a method for writing and reading information to and from the semiconductor memory according to the second embodiment will be described.

The method of writing information to the semiconductor memory according to the second embodiment is the same as that of the first embodiment. Then, each of the storage node N ₁ of the memory cell 1 is at a low level or high level in the individual basic components in the semiconductor memory in accordance with written information.

[0046] When reading the information from a semiconductor memory that this information is written, first, the switching transistor Q ₇ of all the basic components in a conductive state. At this time, light is emitted from the light emitting diode D of the basic constituent element according to the information stored in the memory cell 1 of each basic constituent element. Then, the light emitted from each of the basic constituent elements in the semiconductor memory is separated and detected using, for example, a spectroscope, and the wavelength of the light is measured. As described above, since the wavelength of the light of the basic constituent element is different depending on the row number i, the distribution of the wavelength of the detected light indicates which row of the light emitting diode D of the basic constituent element emits light. Since it can be recognized, the row number i of the basic component in which the storage node N1 of the memory cell ₁ is at the low level is distinguished based on this. At the same time, similarly to the first embodiment, the column number j is distinguished by the electric signal. As described above, the address (i, j) the memory node N ₁ of the memory cell 1 detects whether low level or high level, reads the information written in the semiconductor memory.

As described above, according to the semiconductor memory of the second embodiment, the row number i can be distinguished at a time, so that the signal reading speed is increased and the two-dimensional information is Since the data can be read one-dimensionally only with the column number j, the same effect as in the first embodiment can be obtained.

Next, a semiconductor memory according to a third embodiment of the present invention will be described.

In the semiconductor memory according to the third embodiment, the emission wavelengths of the light emitting diodes D of the basic constituent elements are different from each other depending on the addresses (i, j) of the basic constituent elements. That is, the wavelength of light emitted from the light emitting diode D, which is a basic component in a semiconductor memory, is different for each basic component. Such a basic constituent element is, for example, a row number i in the row direction.
Are arranged so that the wavelength of the light emitted from the light emitting diode D increases as the number increases, and arranged in the column direction such that the wavelength of the light emitted from the light emitting diode D increases as the column number j increases. . Here, the wavelengths of the light emitted from the light emitting diodes D of the two basic constituent elements in which the row number i or the column number j of the address (i, j) are consecutive are set to be different from each other by at least 0.01 nm. Others are the same as in the second embodiment.

Next, a method for writing and reading information from the semiconductor memory according to the third embodiment will be described.

The method of writing information to the semiconductor memory according to the third embodiment is the same as that of the first embodiment. Then, the storage node N ₁ of the memory cell 1 in the individual basic components in accordance with the written information is at a low level or high level, respectively.

[0052] When the read out information from the semiconductor memory that this information is written, first, the switching transistor Q ₇ of all the basic components in a conductive state. Thus, the light emitting diode D of the basic component memory node N ₁ of the memory cell 1 is at a low level and the light-emitting, light-emitting diode D of the basic component memory node N ₁ of the memory cell 1 is at a high level non-emission It does not emit light while maintaining its state. Next, as shown in FIG. 5, the light emitted from the semiconductor memory is passed through the condenser lens 31 and the optical fiber 32
Is condensed at one end and introduced. This optical fiber 32
Is transmitted through the optical fiber 32 and emitted from the other end. The emitted light is supplied to a spectroscope 33 provided near the other end of the optical fiber 32.
And is split by the spectroscope 33. Thereafter, the split light enters a detector 34 provided in proximity to the light exit surface of the spectroscope 33. Since the wavelength of each of the split light beams corresponds to the address (i, j) of the basic component that emits the light beam of that wavelength, those light beams are transmitted to the detector 34 by the basic memory of the semiconductor memory. The light is incident on a predetermined portion corresponding to the address (i, j) of the component. That is, the information written in the semiconductor memory is recognized as the distribution of the wavelength of light, and the address (i, j) of the basic constituent element in which the memory cell 1 is at the low level is collectively recognized. As a result, information in the semiconductor memory is read at once.

As described above, according to the semiconductor memory according to the third embodiment, the reading of the information written in the semiconductor memory can be performed collectively in all the basic constituent elements. The speed can be further improved.

Next, a fourth embodiment of the present invention will be described.

In the fourth embodiment, a plurality of semiconductor memories according to the third embodiment are used to transfer information between the plurality of semiconductor memories.

That is, first, as shown in FIG.
In the same manner as in the first embodiment, the light emitted from the semiconductor memory 40 is made incident on the spectroscope 41 to be separated. The spectroscopic light is detected by the detector 43, and the information written in the semiconductor memory 40 is read by recognizing the wavelength of each light. This information is converted into an electric signal by the detector 42 and written into the semiconductor memory 44 through the signal introducing line 43. Thus, the semiconductor memory 4
Information is transferred from 0 to the semiconductor memory 44.

Next, light is emitted from the semiconductor memory 44 in which this information is written. This light is introduced into one end of an optical fiber (not shown), and transmitted to another spectroscope 45 through the optical fiber. Then, information is written to the semiconductor memory 48 via the spectroscope 45, the detector 46, and the signal introduction line 47 in the same manner as described above. By repeating the above information transfer sequentially using an optical fiber, semiconductor memories 52, 56 having spectrometers 49, 53, 57, detectors 50, 54, 58, and signal introduction lines 51, 55, 59, respectively. , 60 are sequentially transferred.

As described above, according to the fourth embodiment, an optical connection can be formed by transferring information between a plurality of semiconductor memories by optical transmission. .

Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above embodiments, and various modifications based on the technical concept of the present invention are possible.

For example, the materials and laminated structures mentioned in the above embodiments are merely examples, and different materials and laminated structures may be used as needed.

In the first embodiment, for example, the light emitting layer 16 is provided directly on the polycrystalline Si film 15,
The polycrystalline Si film 17 is provided directly on the light emitting layer 16. However, considering the ohmic contact between the polycrystalline Si films 15 and 17 and the light emitting layer 16, the light emitting layer 16 For example, an Au film may be provided between the light emitting layer 16 and the polycrystalline Si film 17 or between the light emitting layer 16 and the polycrystalline Si film 17.

Further, for example, in the first embodiment described above, a polycrystalline Si film is used as the gate electrodes G ₁ and G ₂ , but if necessary, a laminated film such as a WSi film may be used. May be used.

Further, for example, in the above-described first embodiment, a polycrystalline Si film is used as the upper electrode and the lower electrode, but a metal thin film may be used instead of using the polycrystalline Si film. At this time, a metal thin film as an upper electrode is formed so as to be transparent to light emitted from the light emitting layer 16.

In the first embodiment, for example, SiO ₂ or SiN is used as the material of the interlayer insulating film or the insulating film. However, if necessary, tetraethoxysilane (TEOS) or the like may be used. It may be used.

Further, for example, in the first embodiment, the row number i of the address (i, j) of the basic constituent element from which the light emitting diode D emits light is distinguished. The position of the light emitting basic constituent element may be optically read as an image using an element or the like.

Further, for example, the arrangement of the basic constituent elements in the above-described second and third embodiments is merely an example, and is not necessarily limited to the above-described arrangement.

[0067]

As described above, according to the present invention, the memory element is constituted by the carrier traveling element, and the light emitting element can be caused to emit light by the carrier traveling element. A semiconductor device which can realize a memory element which can achieve high-speed reading can be obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a basic constituent element of a semiconductor memory according to a first embodiment of the present invention.

FIG. 2 is a plan view of the semiconductor memory according to the first embodiment of the present invention.

FIG. 3 is a sectional view of a main part of a basic constituent element of the semiconductor memory according to the first embodiment of the present invention;

FIG. 4 shows a plan view of a packaged semiconductor memory according to the first embodiment of the present invention.

FIG. 5 is a schematic diagram for explaining a method of reading information from a semiconductor memory according to a third embodiment of the present invention.

FIG. 6 is a schematic diagram for explaining transfer of information between a plurality of semiconductor memories according to a fourth embodiment of the present invention.

[Explanation of symbols]

1 ... memory cell, 2 ... semiconductor substrate, 16 ...
Light-emitting layer, 21: package, 22: glass window,
Q ₁ , Q ₃ ... N-channel MOS transistors,
Q ₂ , Q ₄ ... P-channel MOS transistors,
Q _5, Q ₆ ··· access transistors, Q ₇ · · · switching transistor, D · · · emitting diode

Claims (8)

[Claims] 1. A light emitting device comprising: a carrier traveling element; and a light emitting element provided above the carrier traveling element, wherein the light emitting element is configured to emit light by the carrier traveling element. Semiconductor device. 2. The semiconductor device according to claim 1, wherein said carrier traveling element forms a memory cell. 3. The semiconductor device according to claim 2, wherein said memory cell comprises a flip-flop circuit. 4. The semiconductor device according to claim 2, wherein light emission of said light emitting element is controlled according to information of said memory cell. 5. The semiconductor device according to claim 1, wherein said light emitting element is a light emitting diode having a stacked structure of a plurality of semiconductor layers. 6. The light emitting device according to claim 1, wherein the light emission of said light emitting element is observable from outside.
13. The semiconductor device according to claim 1. 7. The semiconductor device according to claim 1, wherein said carrier traveling element is made of a group IV semiconductor or a group III-V compound semiconductor. 8. The semiconductor device according to claim 1, wherein said light emitting element is made of a group III-V compound semiconductor, a group II-VI compound semiconductor or a group IV semiconductor.