JPH11134203A - Micro controller, data processing system and control method for task switch - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize high speed task switching in a micro controller for controlling plural hardware engines. SOLUTION: A processor 300, a task management table 310 and a scheduler 330 are incorporated in the micro controller. The processor 300 sequentially executes plural tasks for controlling the allocated hardware engines (cores). The task management table 310 stores task management information containing state information (ST information) showing the respective execution situations of the plural tasks, priority information (PRI information) showing the execution priority of the plural tasks and core ID information (CID information) showing to which cores the plural tasks are allocated. The scheduler 330 causes the processor 300 to switch the task based on task management information when a specified instruction is decoded or the execution of any core terminates.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a microcontroller having a multitasking function and a data processing system in which the microcontroller controls a plurality of hardware engines. The present invention also relates to a method for controlling a task switch.

[0002]

2. Description of the Related Art Microcontrollers having a multitasking function are known. A single processor built into this type of microcontroller performs multiple tasks sequentially. Therefore, the task timer periodically issues a timer interrupt requesting the task switch. Each time the processor receives this timer interrupt, an interrupt processing routine in the operating system (OS) is started, and the interrupt processing routine performs task scheduling and resource saving and restoration.

[0003]

In the above-mentioned conventional microcontroller, task scheduling is performed in an interrupt processing routine. Therefore, there is a problem that overhead in a task switch is large and a substantial operation rate of the microcontroller is reduced. there were. this is,
In particular, this is a serious problem in an application that attaches importance to real-time properties such as encoding of image data.

An object of the present invention is to realize a high-speed task switch in a microcontroller.

It is another object of the present invention to realize a high-speed task switch in a microcontroller in a data processing system in which the microcontroller controls a plurality of hardware engines.

Another object of the present invention is to provide a task switch control method for realizing a high-speed task switch.

[0007]

In order to achieve the above object, a microcontroller according to the present invention does not control a task switch in an interrupt processing routine, but a plurality of tasks are assigned to corresponding hardware engines. Under such an environment, a task switch is controlled by a hardware scheduler based on information indicating the assignment. Some hardware engines perform processing that is time-critical, while others do not. According to the present invention, as a result of such a relationship between the plurality of hardware engines being reflected in the execution priority of each of the plurality of tasks, which of the hardware engines executes the time-critical processing is determined. Can be selected in a short time without re-judgment at the time of task switching. That is, overhead in the task switch is reduced, and a high-speed task switch is realized.

Further, in the microcontroller of the present invention, in consideration of the useless time generated in the time division method in which the task switch is performed in response to an interrupt periodically issued from the task timer, execution of each hardware engine is terminated. An event-driven system that switches tasks immediately in response to an event has been adopted. Each of the plurality of tasks has a first state (READY indicating waiting for execution).
State), and a second state (ACTI)
VE state) and a third state (SLEEP state) indicating the end of execution of the assigned hardware engine. The ACTIVE state is currently
The task is using the microcontroller and controls the hardware engine assigned to the task. The READY state is a state in which a task can use the microcontroller, but the task has not been selected and is waiting to be selected. The SLEEP state is a state where the execution of the assigned hardware engine is awaited, and the microcontroller is not usable. Tasks that have finished running their assigned hardware engines
According to a specific instruction (task_sleep instruction), A
Transition from the CTIVE state to the SLEEP state. When a hardware engine finishes executing, the task assigned to the hardware engine is SLE
The state transitions from the EP state to the READY state, and the task being executed transitions from the ACTIVE state to the READY state. Then, the task having the highest execution priority among the tasks in the READY state is selected as the task to be executed next, and the selected task transits from the READY state to the ACTIVE state.

If a plurality of register files used by each of the plurality of hardware engines as independent work areas are prepared in the microcontroller, only the processor resources such as the program counter need be saved at the time of the task switch. In addition, overhead in task switching is further reduced. A register file for storing setting parameters common to a plurality of hardware engines may be prepared in the microcontroller.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an MPEG (Moving Picture Exper) which is one of the data processing systems according to the present invention.
ts Group) shows an example of the configuration of an image encoder. FIG.
Encoder is a single microcontroller 101
And five hardware engines (hereinafter, referred to as cores) 111 to 11 constituting a macroblock pipeline.
5 and three buffer memories 116 to 118. The five cores are Motion Detector
r: MD) 111, Motion Compensator:
MC) 112, Discrete Cosine Transformer (Discrete Cosine)
Transformer: DCT 113, Quantizer:
Q) 114 and Variable Length Coder (Variable Length Code)
r: VLC) 115, each of which is controlled by a microcontroller 101 having a multitasking function. 121 is image data to be encoded, 1
Reference numeral 22 denotes encoded data representing an encoding result. The microcontroller 101 has five cores 111 to 115
Supply the activation signal 123 to each of the five cores 11
An end signal 124 is received from each of 1 to 115. Further, the microcontroller 101 includes signal lines 131 to 1
35, and individually communicate with the five cores 111 to 115 via the signal line 136.
To give common parameters.

FIG. 2 shows a detailed configuration of the microcontroller 101. The microcontroller 101
A task controller 201 for realizing a multi-tasking function, five core register files 211 to 215 used by each of the five cores 111 to 115 as independent working areas,
To 115, one common register file 216 for storing setting parameters common to at least two cores, one general-purpose register file 217 used as a work area by the task controller 201, and a multiplier 221. , A shifter 222 and an arithmetic and logic unit (Ar
It has an ithmetic and logic unit (ALU) 223 and a data memory 224. 241 is A bus, 242
Is a B bus, 243 is a C bus, 231 is a signal line for connecting these buses and the task controller 201. The task controller 201 sends the start signal 123
And receives the end signal 124. Each of the register files 211 to 216 is interposed between the C bus 243 and the corresponding one of the signal lines 131 to 136, and two outputs of each of the register files 211 to 216 are A buses 241 and B
Each is connected to a bus 242. Each input of the general-purpose register file 217 and the data memory 224 is C
Bus 243 has two outputs on each of A buses 241 and B
Each is connected to a bus 242. A multiplier 221,
The two inputs of each of the shifter 222 and the ALU 223 are connected to the A bus 241 and the B bus 242, and the respective outputs are connected to the C bus 2
43 respectively. Note that the arrangement of the five core register files 211 to 215 and the common register file 216 may be omitted, and the signal lines 131 to 136 may be directly drawn from the C bus 243.

According to the MPEG image encoder of FIG.
Image data processing proceeds in units of macroblocks of 16 × 16 pixels. First, the MD core 111 obtains a motion vector candidate for the input image data 121. The difference data of the image is obtained by the MC core 112 using these motion vectors, and an optimal motion vector is selected. The differential data for the selected motion vector is subjected to discrete cosine transform by the DCT core 113, quantized by the Q core 114, and variable-length coded by the VLC core 115 together with the obtained side information such as the motion vector. It is output as data 122.

More specifically, referring to FIG. 2, the task controller 201 first includes the signal line 231 and the ALU 22
3 and the operation parameters are set in the MD core register file 211 via the C bus 243, and the MD core 111 is activated by the activation signal 123. MD core 111 is MD
The operation parameters are read from the core register file 211 via the signal line 131 and the image data 121 is read.
Enter When the execution of the MD core 111 ends, the obtained motion vector candidate is
Written to the core register file 211, the MD core 1
11 outputs an end signal 124. Upon receiving the end signal 124, the task controller 201
The motion vector candidates are read from the core register file 211, and a multiplier 221, a shifter 222,
The operation parameters for the MC core 112 are calculated using the ALU 223 and the general-purpose register file 217. These operation parameters are set in the MC core register file 212, and the MC core 112 is activated by the activation signal 123. After reading the operation parameters from the MC core register file 212 via the signal line 132, the MC core 112 obtains image difference data. MC core 112
Is completed, the sum of the differential data is
, The difference data of the image is written to the buffer memory 116 in the MC core register file 212, and the end signal 124 is output from the MC core 112.
Upon receiving the end signal 124, the task controller 201 reads out the sum of the difference data from the MC core register file 212, and based on the read sum, the multiplier 221, the shifter 222, the ALU 223, and the general-purpose register file 2
17, the optimal motion vector is selected from the candidates. The address of the difference data corresponding to the obtained motion vector is set in the DCT core register file 213, and the DCT core 113 is activated by the activation signal 123. The DCT core 113 reads the difference data from the buffer memory 116 based on the address set in the DCT core register file 213, and performs a discrete cosine transform. When the execution of the DCT core 113 ends, the result of the discrete cosine transform is written into the buffer memory 117, and the end signal 124 is output from the DCT core 113. Thereafter, the quantization processing is performed in the Q core 114, and the result is written in the buffer memory 118, and the VLC core 1
At 15, the variable-length encoding process is performed, and the result is output as encoded data 122. The above five cores 1
Some of the cores 11 to 115 exchange the start signal 123 and the end signal 124 with the microcontroller 101 a plurality of times while processing one macroblock. The common register file 216 includes MPEG1 and MP
Common parameters for switching to EG2 are supplied in advance to the five cores 111 to 115, and common parameters for specifying the motion evaluation mode are set to MD cores 111 and M.
It is used when supplying to the C core 112 in advance.

FIG. 3 shows a detailed configuration of the task controller 201. The task controller 201 includes a processor 300, a task management table 310, and a scheduler 330. Processor 300
Is a reduced instruction set computer (RISC) that can execute up to eight tasks sequentially.
An r) type processor comprising a program counter (PC) 301 for generating an instruction address and an instruction memory 30 for storing a program consisting of a series of instructions.
2 and an instruction decoder 303 for decoding the instruction. The activation signal 123 to each core is supplied from the instruction decoder 303. Also, the instruction decoder 303
Are connected to the multiplier 221, the shifter 222, the ALU 223, and the like, which are resources for executing instructions, via a signal line 231. The task management table 310 is a circuit block for storing task management information, and includes eight task management register files 320 to 327 corresponding to eight tasks from task 0 to task 7, respectively.
It has. Here, the task management information is state information (ST information) representing the execution status of each of the plurality of tasks.
And priority information (PRI information) indicating the execution priority of each of the plurality of tasks, and a core indicating which of the five cores 111 to 115 each of the plurality of tasks is assigned to ID information (CID information). Further, the task management table 310 has an area for each task for saving the resources of the processor 300, that is, the contents of the PC 301. In this save area, AL
Flags and the like relating to the calculation result of U223 (see FIG. 2) are also saved. The scheduler 330 is a circuit block for causing the processor 300 to perform a task switch based on the task management information stored in the task management table 310, and includes a state controller 331, an end core determination unit 332, and a priority encoder 333.
And a selector 334. The termination core determination unit 332 is a unit that, when receiving the termination signal 124 from any one of the five cores 111 to 115, determines the task assigned to the core that has finished executing. This determination is based on the task management table 310
The task number 362 indicating the determination result is notified to the state controller 331. The priority encoder 333 is a circuit block for selecting a task to be executed next. This selection is performed with reference to the task management table 310, and the task number 361 indicating the selection result is notified to the state controller 331 and the selector 334. State controller 331
Is a circuit block for updating the ST information in the task management table 310. The selector 334 is responsible for returning resources to the processor 300.

FIG. 4 shows the correspondence between cores and tasks in the MPEG image encoder of FIG. The microcontroller 101 now has six tasks 400
405 is executed. The task 400 is a main task (task 0) for controlling the five tasks 401 to 405 in the lower hierarchy and managing the entire encoding process. There is no core to which this main task 400 should be assigned. The task 401 is a motion detection task (task 1) for controlling the assigned MD core 111.
It is. Task 402 is assigned to the assigned MC core 11
2 is a motion compensation task (task 2) for controlling the second task. Task 403 is performed by the assigned DCT core 113
Cosine transform task for controlling the task (task 3)
It is. Task 404 is assigned to the assigned Q core 114
Is a quantization task (task 4) for controlling. Task 405 is a variable-length encoding task (task 5) for controlling the assigned VLC core 115.

Here, it is assumed that task management information on at least six tasks 400 to 405 shown in FIG. 4 is stored in the task management table 310 in FIG. According to FIG. 3, the PRI information is a priority setting signal 34.
2, the CID information is set according to the core setting signal 343. The priority setting signal 342 is set when the instruction decoder 303 decodes the priority setting instruction, and the core setting signal 343 is set when the instruction decoder 303 decodes the priority setting instruction.
Are supplied from the instruction decoder 303 to the task management table 310 when decoding the core setting instruction.

FIG. 5 is a conceptual diagram showing the state transition of each task. The task has a STOP state indicating stop, a READY state indicating waiting for execution, an ACTIVE state indicating executing, and a SLEEP state indicating waiting for completion of execution of the assigned core. However, task 0 has no SLEEP state. The task immediately after the reset is in the STOP state. The task in the STOP state is transited to the READY state by the task_ready instruction (transition 501).
When the task in the READY state is selected by the scheduler 330 when an event requiring a task switch occurs, the task is transitioned to the ACTIVE state (transition 511). At this time, the task that was in the ACTIVE state up to that point
A transition is made to the EADY state (transition 522). A
Tasks in the CTIVE state include the processor 300
Is executed by the task_sleep instruction.
The state is shifted to the EEP state (transition 521), and t
A transition to the STOP state can be made by the ask_stop instruction (transition 523). SLEE
The task in the P state is transited to the READY state when the execution of the assigned core is completed (transition 531).

Here, the task controller 201 shown in FIG.
Will be described in detail. Instruction decoder 303 is task
_Ready instruction, task_sleep instruction or ta
When the sk_stop instruction is decoded, a task switch occurs. For example, in a task being executed, a task that has finished setting operation parameters for a core assigned to the task and activating the core is task_sleep.
A transition is made from the ACTIVE state to the SLEEP state by the p instruction. In addition, five cores 111 to 11
A task switch also occurs when any of the cores 5 has finished executing. The operation sequence of the task controller 201 at the time of task switching includes (1) activation of the scheduler, (2) saving of resources of the task being executed, and (3)
Selection of a task to be executed next, and (4) restoration of the saved resource.

First, a sequence of a task switch based on an instruction will be described.

(A-1) Activation of Scheduler When a task_ready instruction, a task_sleep instruction, or a task_stop instruction is decoded, the instruction decoder 303 outputs a state change signal 341. The state change signal 341 is the state controller 3
31 is input. As a result, the scheduler 330 is activated.

(A-2) Saving Resources of the Running Task The state change signal 341 is also input to the task management table 310, and the ST information is updated. At the same time, the value of the PC 301 of the task executed up to that
The data is saved in the register management table 310 via the register 44.

(A-3) Selection of Next Task to be Executed The priority encoder 333 receives ST information from the task management table 310 via the signal line 351 and PRI information via the signal line 352, respectively.
The task having the highest execution priority among the tasks in the DY state is selected as the task to be executed next. The task number 361 indicating the result of this selection is notified to the state controller 331 and the selector 334.

(A-4) Restoration of Saved Resources The state controller 331 sends a state change signal 364 corresponding to the task number 361 to the task management table 31.
0. As a result, the priority encoder 3
33, the ST information of the task selected by READY
The state is updated to the ACTIVE state. The selector 334 reads the PC of the task specified by the task number 361 from the task management table 310 via the signal line 353, and supplies the PC to the signal line 363. As a result, the value of the PC of the task to be executed next is
00 is set, and the execution of the task starts.

Next, a sequence of task switching based on the completion of execution of the core will be described.

(B-1) Startup of the Scheduler When any of the cores has been executed, the end signal 124 is input to the end core determination unit 332. The end core determination unit 332 determines which core has been executed based on the end signal 124. Further, the terminated core determination unit 332 reads the CID information in the task management table 310 via the signal line 354, and determines which task is assigned to the core whose execution has been completed. The task number 362 representing the result of this determination is ST
When it is confirmed from the information that the task is in the SLEEP state, the state controller 331 is notified. As a result, the scheduler 330 is activated.
The state controller 331 sends a state change signal 364 corresponding to the task number 362 to the task management table 31.
0. As a result, the ST information of the task whose execution has been completed is updated from the SLEEP state to the READY state. If there is no task assigned to the core whose execution has been completed, the scheduler 330 is not activated.

(B-2) Saving the Resources of the Running Task Further, the state controller 331 issues a state change signal so that the ST information of the task being executed up to that point is updated from the ACTIVE state to the READY state. 364 to the task management table 310. PC3 of the task that was being executed up to that point
The value of 01 is saved in the task management table 310.

(B-3) Selection of Task to be Executed Next The priority encoder 333 receives ST information and PRI information from the task management table 310,
The task having the highest execution priority among the tasks in the ADY state is selected as the task to be executed next. The task number 361 indicating the result of this selection is notified to the state controller 331 and the selector 334.

(B-4) Restoring Saved Resources The state controller 331 sends a state change signal 364 corresponding to the task number 361 to the task management table 31.
0. As a result, the priority encoder 3
33, the ST information of the task selected by READY
The state is updated to the ACTIVE state. The selector 334 reads the PC of the task specified by the task number 361 from the task management table 310, and
Is supplied to the processor 300. As a result, the PC value of the task to be executed next is set in the processor 300,
Execution of the task starts.

FIG. 6 shows the five cores 111 to 11 in FIG.
5 shows the macroblock pipeline processing by No. 5. The pipeline pitch is set to the maximum value of the time required for processing one macroblock in each core. Therefore, there is a characteristic that there is a core whose execution ends earlier than other cores in each pipeline pitch period. Here, idle time occurs. Moreover, there is a characteristic that the length of the idle time changes depending on the image data. In the example of FIG.
The G image encoder is realized by employing an event-driven task switch. Note that the number of activations of a core in each pipeline pitch period differs depending on the content of processing performed by the core and data. For example, DC
The T core 113 is activated once in one pipeline pitch period. The MC core 112 is activated a plurality of times according to the data in one pipeline pitch period in order to divide the data of one macroblock into a luminance component and a chrominance component, and to execute the processing in a finely divided manner for each component.

FIG. 7 shows a specific example of the state transition of each of the three tasks in the partial period specified by the broken line in FIG. Task 0 is a main task for managing the entire encoding process, and task 1 is an MD core 1
The task assigned to the MC core 112 is a task assigned to the MC core 112 (see FIG. 4).
Of these three tasks, task 1 has the highest execution priority, task 2 has the second highest execution priority, and task 0 has the highest execution priority.
Has the lowest execution priority. At time t0, task 1 enters the ACTIVE state and task 0
And task 2 are in the READY state.

According to FIG. 7, a task switch occurs at each of the times t1 to t7. Δt in the figure represents the overhead in one task switch.
Explaining in order, the task 1 activates the MD core 111 before time t1. Then, at time t1, tas
Task 1 transitions from the ACTIVE state to the SLEEP state by the k_sleep instruction. At this point, task 0 and task 2 are in the READY state, and the execution priority of task 2 is higher than the execution priority of task 0. Therefore, task 2 transitions from the READY state to the ACTIVE state. Task 2 activates the MC core 112. Then, at time t2, the task 2 transitions from the ACTIVE state to the SLEEP state by the task_sleep instruction. At this point, only task 0 is READ
Since it is in the Y state, task 0 transitions from the READY state to the ACTIVE state. And time t
Task 3 is SLE due to completion of execution of MC core 112
Transition from the EP state to the READY state. Accordingly, task 0, which was in the ACTIVE state up to that point, transitions to the READY state. At this point, task 0 and task 2 are in the READY state, and the execution priority of task 2 is higher than the execution priority of task 0. Therefore, task 2 transitions from the READY state to the ACTIVE state. Task 2 restarts the MC core 112. Then, at time t4, the task 2 transitions from the ACTIVE state to the SLEEP state by the task_sleep instruction. At this point, only task 0 is REA
Since it is in the DY state, task 0 transitions from the READY state to the ACTIVE state. At the time t5, the task 1 is set to the SL
Transition from the EEP state to the READY state. Accordingly, task 0, which was in the ACTIVE state up to that point, transitions to the READY state. At this point, task 0 and task 1 are in the READY state,
Since the execution priority of task 1 is higher than the execution priority of task 0, task 1 is changed from the READY state to ACTIVE.
Transition to the state. Then, at time t6, the MC core 11
Task 2 transitions from the SLEEP state to the READY state upon completion of execution of step 2. As a result, task 1 which was in the ACTIVE state up to that point becomes READ
Transition to the Y state. At this point, task 0, task 1 and task 2 are in the READY state and task 1
Is higher than the execution priority of each of task 0 and task 2, so that task 1 changes from the READY state to A
Return to the CTIVE state. Task 1 is MD core 111
To restart. Then, at a time t7, task_sleep
Task 1 changes from ACTIVE state to SL by p instruction
Transition to the EEP state. At this point, task 0 and task 2 are in the READY state, and the execution priority of task 2 is higher than the execution priority of task 0.
Transitions from the READY state to the ACTIVE state.

Although the overhead of one task switch in the case of employing the time-division type task switch using the conventional interrupt processing routine is as much as ten or more machine cycles, the event-driven type task switch according to the present invention is not used. In the case of adoption, the overhead Δt in FIG. 7 requires only several machine cycles. Considering that a maximum of 20 or more task switches occur in each macro pipeline pitch period in FIG. 6, the difference in overhead between the two methods is further increased. The reduction in overhead according to the present invention also allows for a reduction in pipeline pitch. That is, high-speed encoding of image data can be achieved.

As described above, a high-speed task switch is realized in the MPEG image encoder of FIG. In addition, by setting a high execution priority to a task that executes a time-critical process, a normal image encoding process can be guaranteed. Moreover, when the execution of one of the cores is completed, the state of the task assigned to the core whose execution has been completed and the state of the task being executed up to that point are both changed to the READY state. Since the task having the highest execution priority among all the tasks in the state is selected as the task to be executed next, the internal configuration of the priority encoder 333 is simplified. Furthermore, since a program can be described independently for each task, programming is made more efficient, which is advantageous for debugging.

The present invention can be applied to other data processing systems such as an image decoder. In the above example, one task is assigned to all hardware engines (cores). However, there may be a core to which no task is assigned, or a plurality of tasks may be assigned to one core. One task is not assigned to a plurality of cores at the same time.

[0035]

As described above, according to the present invention, in an environment in which a plurality of tasks are respectively assigned to corresponding hardware engines (cores), a hardware scheduler is used based on information representing the assignment. Since the task switch is controlled, a high-speed task switch can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of an MPEG image encoder according to the present invention.

FIG. 2 is a block diagram showing a detailed configuration of a microcontroller in FIG.

FIG. 3 is a block diagram showing a detailed configuration of a task controller in FIG. 2;

FIG. 4 is a conceptual diagram showing a correspondence between cores and tasks in the encoder of FIG. 1;

FIG. 5 is a conceptual diagram showing a state transition of a task in the encoder of FIG. 1;

FIG. 6 is a timing chart showing macroblock pipeline processing by five cores in FIG. 1;

FIG. 7 is a timing chart showing a specific example of a state transition of each of three tasks in a partial period in FIG. 6;

[Explanation of symbols]

 Reference Signs List 101 Microcontroller 111 Motion detector (MD core) 112 Motion compensator (MC core) 113 Discrete cosine transformer (DCT core) 114 Quantizer (Q core) 115 Variable length encoder (VLC core) 116 to 118 Buffer Memory 201 Task controller 211 to 215 Core register file 216 Common register file 300 Processor 310 Task management table 330 Scheduler 331 State controller 332 End core determination unit 333 Priority encoder

Claims (15)

[Claims] A processor for sequentially executing a plurality of tasks; state information indicating an execution status of each of the plurality of tasks; priority information indicating an execution priority of each of the plurality of tasks; A task management table for storing task management information including assignment information indicating which hardware engine is assigned to each of the plurality of tasks; and causing the processor to perform a task switch based on the task management information. And a scheduler for the microcontroller. 2. The microcontroller according to claim 1, wherein each of the plurality of tasks has a first state indicating a waiting state, a second state indicating an executing state, and execution of an assigned hardware engine. A third state representing a wait for completion. 3. The microcontroller according to claim 2, wherein the processor changes the state of the executing task when the processor decodes a specific instruction after activating a hardware engine assigned to the task. A microcontroller having a function of updating the state information so as to change from a second state to the third state. 4. The microcontroller according to claim 2, wherein the scheduler is configured to execute when one of the hardware engines finishes executing.
A determination unit for determining a task assigned to the hardware engine based on the task management information; and, when activated by the determination unit, change a state of the determined task from the third state to the third state. 1
And a state controller having a function of updating the state information so as to change to the state of the microcontroller. 5. The microcontroller according to claim 4, wherein the state controller, when activated by the determination unit, changes a state of the task being executed to the second state.
A microcontroller further having a function of updating the state information so as to change the state from the first state to the first state. 6. The microcontroller according to claim 2, wherein the scheduler should execute a task having the highest execution priority among tasks in the first state based on the task management information. A microcontroller further comprising a priority encoder for selecting as a task. 7. The microcontroller according to claim 6, wherein the state controller changes the state information so as to change the state of the task selected by the priority encoder from the first state to the second state. A microcontroller further having a function of updating. 8. The microcontroller according to claim 1, wherein the task management table has an area for saving resources of the processor related to a task executed before the time of the task switch. And a microcontroller. 9. The microcontroller according to claim 1, further comprising: a plurality of register files used by each of the plurality of hardware engines as independent work areas. 10. The microcontroller according to claim 1, wherein at least two of the plurality of hardware engines are provided.
A microcontroller further comprising a register file for storing setting parameters common to the hardware engines. 11. A data processing system comprising: a plurality of hardware engines each for executing data processing; and a microcontroller for controlling the plurality of hardware engines, wherein the microcontroller comprises: A processor for sequentially executing the tasks, state information indicating the execution status of each of the plurality of tasks, priority information indicating the execution priority of each of the plurality of tasks, and each of the plurality of tasks A task management table for storing task management information including assignment information indicating which hardware engine is assigned, and a scheduler for causing the processor to perform a task switch based on the task management information. A data processing system. 12. The data processing system according to claim 11, wherein each of the plurality of tasks has a first state indicating a waiting state, a second state indicating a running state, and an assigned hardware engine. A third state indicating execution completion wait. 13. The data processing system according to claim 11, wherein each of the plurality of hardware engines is a partial processing core for encoding MPEG image data. 14. A task switch control method in which at least one task is respectively assigned to a corresponding hardware engine, and the task switch is controlled by a scheduler based on information indicating the assignment, wherein the task is waiting to be executed. , A second state representing execution, and a third state representing the end of execution of the assigned hardware engine. When the hardware engine terminates execution, the hardware A task switch control method, comprising: changing a state of a task assigned to a wear engine from the third state to the first state. 15. The task switch control method according to claim 14, wherein when the execution of the hardware engine ends, the state of the task being executed is changed from the second state to the first state. Task switch control method.