JP3356677B2 - Processor that can execute asynchronous event tasks efficiently even if there are many tasks to be executed asynchronously - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processor which is provided in an AV decoder for reproducing multimedia data having a variable code length such as an MPEG stream, and exclusively controls peripherals of a main processor in the AV decoder.

[0002]

2. Description of the Related Art MPEG stream reproduction technology is also one of the basic technologies of the multimedia society, and the demand for such technology has been remarkable in recent years. Attention has been focused on the new stage of MPEG stream playback technology in the field of consumer electronics that enables interactive video playback and audio playback. Engineers are working hard on research and development of AV decoders that can play MPEG streams at a high level.

There are various types of processing to be performed by the MPEG stream reproduction technology, and these are said to be roughly classified into core processing and asynchronous event processing. Core processing is 16 × H, such as inverse quantization, inverse discrete cosine transform, and motion compensation.
This is a process for a macroblock composed of 16 pixels. Since 4050 macroblocks must be processed per second (4050 = 30 frames × 30 slices × 45 macroblocks), the amount of calculation becomes enormous. Pipeline processing is preferable for executing the core processing. However, if the hardware scale is tolerated, it is preferable to disperse the load of the core processing by using a plurality of decoders and arithmetic units.

[0004] Asynchronous event processing is processing that should be performed intensively during a period in which a specific event is established due to the overlapping of a plurality of factors, or processing that should be performed intermittently at a predetermined cycle. A generic term for processing that cannot be performed in synchronization with processing. In the AV decoder, processing corresponding to such asynchronous event processing includes processing relating to MPEG stream input from a recording medium or a communication medium (1), AV processing.
There are three types, one related to output from the decoder to the video playback device and the audio playback device (2), and the other related to input / output between the AV decoder and an extended memory connected outside the AV decoder (3).

The asynchronous event processing (1) relating to stream input from a recording medium is further performed by extracting an MPEG stream from a recording medium such as an optical disk or a communication medium and extracting an elementary stream (1-1). There is a write process (1-2) for writing the elementary stream to the SDRAM connected as the extended memory. Asynchronous event processing (2) relating to playback output further includes a decoded video stream, audio stream as a video signal,
The process of converting each to an audio signal and outputting it to a display and a speaker (2-1), drawing the sub-video output as a private stream of the MPEG stream, mixing this with video data, and adding subtitles to the video signal Compositing process
(2-2) is included.

Asynchronous event processing (3) relating to input / output to / from the extended memory further monitors whether data subjected to processing such as inverse quantization, inverse discrete cosine transform, and motion compensation is accumulated in an internal buffer. When the accumulated amount reaches a certain amount, SD
Data to be collectively written to RAM (3-1), intermittent replenishment of data to be processed next from the externally connected SDRAM to the internal buffer according to the progress of inverse quantization, inverse discrete cosine transform, and motion compensation (3-2).

[0007] In addition to the above-described processing, processing to be performed in response to an operation from the operator is classified into this asynchronous event processing. More than just asynchronous playback when designing an application system for a playback device that places emphasis on operator interactivity, or when designing a system that assumes synchronization control with the host computer, rather than simply playing back an MPEG stream. It is necessary to have the AV decoder process the event processing.

[0008] Of the above processing, the processing related to audio in the processing (2-1) is called an audio out task.
It has an intermittent cycle of 90 μsec. In the process (2-1), a process related to video is called a video out task, and it is necessary to complete processing of an image for one line in 50 μsec based on an intermittent cycle of a horizontal synchronization signal of a display.

The reason why the execution cycle is given to the video-out task and the audio-out task is that, if the processing of these tasks is not completed, the moving image-sound cannot be smoothly reproduced along the flow of time. That is, the processing of video out task and audio out task is 50μ.
Completion within a cycle of 90 sec and 90 μsec is the maximum requirement to satisfy the real-time performance of moving image reproduction and audio reproduction.

In the conventional MPEG stream reproduction technology, when the above-described asynchronous event processing is performed by a general-purpose processor, the occurrence of the asynchronous event and the arrival of a predetermined period are notified to the general-purpose processor by an interrupt signal. After the notification, the general-purpose processor branches to asynchronous event processing using a branch instruction.

[0011]

However, in the conventional method of causing a general-purpose processor to execute asynchronous event processing using an interrupt signal, an audio-out task,
There is a problem that the optimum lower limit of the number of operation clocks, which indicates how much the operation clock should be determined to complete the video out task processing, cannot be uniquely calculated.

Since the optimum lower limit cannot be calculated, the number of operation clocks must be determined by rough estimation, and the number of operation clocks tends to be set higher. The following describes how the operation clock is calculated in the conventional method. As an asynchronous event task having a different cycle, an audio out task having an execution cycle of 90 μsec and a video out task having an execution cycle of 50 μsec must be executed.
In this case, the audio out task is 0μsec, 90μsec,
180 μsec, 270 μsec, 360 μsec, 450 μsec, etc.
The audio stream must be decoded every μsec, and the video out task is 0 μsec, 50 μsec, 100 μse
c, the decoding of the video stream must be completed every 50 μsec, such as 150 μsec, 200 μsec, 250 μsec, 300 μsec, 350 μsec. The conventional general-purpose processor notifies the arrival of two execution periods by an interrupt signal, and then processes the video-out task and the audio-out task.

When the audio-out task and the video-out task are to be started after the execution time has come to be known from the interrupt signal, the time limit at which each task must complete the processing is an interrupt for starting itself. It is determined from the signal generation timing to the interrupt signal generation timing for activating the next task. FIG.
It is a timing chart assuming a case where these cycles are notified to a general-purpose processor by an interrupt signal and executed. In the figure, how the time limit for completing the processing of the audio out task-video out task appears will be described.

When the rising of the pulse P1 and the rising of the pulse P5 occur and the general-purpose processor is notified that the video-out task and the audio-out task are to be started, the rising of the pulse P2 which is the next interrupt signal is notified. The time period of 50 μsec until the processing is completed is a time limit for completing the processing of the video out task and the audio out task.

On the other hand, when the rising of the pulse P6 occurs,
When the general-purpose processor is notified that the audio-out task is to be activated, the time limit for completing the audio-out task is only 10 μsec until the rise of the pulse P3 as the next interrupt signal is notified. In the method of calculating the operation clock from the time limit, 10
Even in a very short time limit such as μsec, that is, the worst case of the time limit, the number of operation clocks required to complete the audio out task and the video out task is required. Then, the operation clock must be determined to be higher. However, if the operating clock is easily increased, the power consumption will increase significantly,
It is no longer suitable for consumer equipment.

An object of the present invention is to assign an appropriate number of cycles to each asynchronous event task when there are a plurality of asynchronous event processes in which the amount of processing to be completed in a predetermined cycle is predetermined. And a processor capable of uniquely calculating an optimum lower limit value indicating whether or not, and uniquely calculating a lower limit value of the number of operation cycles for operating all tasks from the optimum lower limit value. That is.

[0017]

In order to achieve the above-mentioned object, the present invention provides a processor having n tasks to be executed, wherein the number of task identifiers assigned to the tasks is n. Execution instruction instruction means for outputting the next task identifier when the instruction is executed; instruction designation means for sequentially designating instructions to be executed in the task specified by the output task identifier; Execution means for executing, the execution task instruction means, n
In the number of tasks, a penalty task holding unit that holds an identifier of a penalty task that is a task to which the number of instructions less than the number of instructions assigned to a normal task is assigned, and a penalty task holding unit that outputs a next task identifier. , It is determined whether the task identified by the task identifier is a penalty task. If the task is not a penalty task, the first instruction number is determined. If the task is a penalty task, the second instruction number is smaller than the first instruction number. The number of instructions
Means for selecting the number of instructions to be assigned to the task .

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) Before starting the description of the I / O processor, what kind of internal configuration of the AV decoder is and what role the I / O processor according to the present invention plays in that configuration Explain what is being done. FIG. 1 shows the internal configuration of the AV decoder.

The AV decoder consists of a decoder core unit for performing core processing and an I / O unit for performing a plurality of asynchronous event tasks. The decoder core unit includes a setup unit 104 and a VLD unit 10.
5, including an IQ / IDCT unit 106 and a motion compensation unit 107. The I / O unit includes a stream input unit 101, a buffer memory 102,
Bit stream FIFO 103, video output unit 108, audio output unit 109, I / O processor 113, buffer memory controller 110, RAM controller 11
1, a FIFO controller 112 and a host I / O unit 115. As a bus, a buffer memory bus 121,
An SDRAM bus 122, a bit stream bus 123, and an IOP control bus 124 are provided, and are connected to the SDRAM 300 as an extended memory.

(1.) Outline of MPEG Stream Decoding Process Next, an outline of the MPEG stream decoding process will be briefly described with reference to FIG. In the present embodiment, MPEG
The stream includes a moving picture stream, an audio stream, and a sub-picture stream. The moving image stream is compressed moving image data, and in a decoding process, an image serving as a reference for calculating a difference (hereinafter referred to as a “reference image”) and an image obtained by encoding the calculated difference (hereinafter referred to as a “difference The image is restored to a moving image.

In FIG. 2, the data structure of the moving picture stream in the MPEG stream is expressed hierarchically. The first layer is a layer of an MPEG stream, and the second layer is a layer of a moving image having a length of one second. The third layer is a layer of one frame,
The fourth layer is a layer of one slice. The fifth layer is a macroblock hierarchy. Referring to the correspondence between the first layer and the second layer indicated by the broken line C1, the MPEG (Motion Picture Image
It can be seen that a 1 second long moving image in the NG Experts Group) is composed of 30 frame images in the NTSC system (25 frame images in the PAL system). The images of each frame are composed of an I picture (I0 in the figure) and a P picture (P in the figure).
3) and three types of B pictures (B1, B2 in the figure).

Here, the I picture is compressed image data, but includes one frame of a luminance component and a color difference component. P picture (Predictive-Picture) or B picture (Bidirectionally predictive Picture)
Is called a difference image. Here, the P picture is a difference image including a difference from a frame located in the past direction, and the B picture is a difference image including a difference from a frame located in the past direction and the future direction.

Regarding the unit in which the B picture and the P picture are created, referring to the correspondence between the second layer and the third layer shown by the broken line C2, these images are 30 lines in the NTSC system. PAL
It can be seen that the method is constituted by data of 36 slices. Referring to the correspondence between the third layer and the fourth layer indicated by the broken line C3, it can be seen that each slice is composed of 45 macroblocks. Macro blocks are 16 horizontal
It is composed of a luminance component and a color difference component of pixel × 16 pixels.
Referring to the correspondence between the fourth layer and the fifth layer indicated by the broken line C4, a luminance block composed of 16 × 16 luminance components and a horizontal
It can be seen that the image includes a blue difference block (Cb block) composed of 8 × 8 blue color difference components and a red difference block (Cr block) composed of 8 × 8 red color difference components. This macroblock is one unit of image decoding in the AV decoder.

Below the macroblock is a timing chart showing how to process the luminance block and the chrominance block included in the macroblock between the components of the AV decoder. Decoding is performed on a macroblock. Decoding on a macroblock is performed by performing variable-length decoding (Va
riable Length code Decoding: hereinafter abbreviated as VLD) to obtain six spatial frequency component data, header information, and a motion vector.

Then, an inverse discrete cosine transform (Discrete Cosine Transform: D) is performed on the six spatial frequency component data.
CT) to perform spatial frequency components located in the low frequency band,
This is performed by separating into spatial frequency components located in the high frequency band, discarding the high frequency band, and performing inverse quantization on the spatial frequency components located in the low frequency band. The coded macroblock is subjected to inverse quantization and inverse discrete cosine transform processing, and then displayed as video by motion compensation based on a motion vector. What is a motion vector?
This refers to information indicating a location having the highest correlation as compared with the images of the preceding and following frames. In other words, the motion vector expresses in a block unit how a human image or a building image in the image has moved before and after the frame.

The motion compensation refers to adding (blending) a reference image to be displayed before and after the difference and the difference to obtain one complete display image. Of the above-described MPEG-compliant moving picture coding / decoding techniques, the contents particularly cited in this specification are as described above. For more detailed technical contents, refer to publicly known documents such as ASCII Corporation "Point Illustrated Latest MPEG Textbook".

The timing chart in FIG. 2 shows a setup section 104, a VLD section 105, an IQ / I
It will be referred to when explaining what timing the processing of the DCT unit 106 and the motion compensation unit 107 is performed. This concludes the description of the outline of the MPEG stream decoding process, and then starts the description of the components of the AV decoder.

(2.) Components of AV Decoder The stream input unit 101 transmits an MP
When the EG stream is taken out, the MPEG stream is taken into the AV decoder and output to the buffer memory bus 121 under the control of the I / O processor 113. The buffer memory 102 is a buffer memory controller 11
In accordance with the control of 0, the MPEG stream captured by the stream input unit 101 is held. When the buffer memory controller 110 is instructed to output the MPEG stream, the MPEG stream stored so far is converted to the SDRA format.
Output to the M bus 122.

The bit stream FIFO 103 has an elementary stream included in the MPEG stream that is an SDRA.
When output to the M bus 122, the FIFO controller 112
Captures the elementary stream output under the control of. The bit stream FIFO 103 holds the captured elementary stream in a first-in first-out manner. The elementary stream thus held is output to the bit stream bus 123 under the control of the FIFO controller 112.

The setup unit 104 includes a bit stream FIFO
It waits for an elementary stream to be extracted from the MPEG stream held in 103, and if the elementary stream is a moving image stream or an audio stream, waits for its header to be expanded by decoding by the VLD unit 105. When the header is decompressed, the analyzing process e1 is performed as shown in FIG. If the elementary stream is a video stream, motion vector extraction e2
I do. Thereafter, while the inverse quantization, the inverse discrete cosine transform, the motion compensation, and the like are being performed, the audio stream decoding process e3 is performed.

The VLD unit 105 includes a bit stream FIFO 1
When the elementary stream stored in the macroblock 03 is a moving image stream, and the macroblocks constituting the stream are output to the bit stream bus 123, the four luminance blocks Y0, Y1, Y2, Y3 included in the macroblock are output.
And variable code length decoding t21, t22, t23, t24, t25, t26 for the two color difference blocks Cb, Cr.

The IQ / IDCT unit 106 performs inverse quantization and inverse discrete cosine transform on the four luminance blocks subjected to variable code length decoding and the two chrominance blocks. When the inverse quantization and the inverse discrete cosine transform are performed by the IQ / IDCT unit 106, the motion compensation unit 107 generates a reference image (Y0, Y
1), (Y2, Y3), (Cb.Cr) are connected to the SDRA
Read from M300, blend the luminance block and the chrominance block with the reference image. Then, motion compensation is performed by performing half-pel interpolation on the blend result. After that, the result of the motion compensation is written into the SDRAM 300 by controlling the RAM controller 111.

The video output unit 108 includes a motion compensation unit 107
, A one-frame image blended with a reference image and half-pel interpolation are converted into a video signal, and output to a display device such as a television receiver connected externally.
The audio output unit 109 converts the audio stream decoded by the setup unit 104 into an audio signal and outputs the audio signal to an externally connected speaker device.

A buffer memory controller (BM controller in the figure) 110 includes a buffer memory interface for arbitrating access between the stream input unit 101, the video output unit 108, and the audio output unit 109 around the I / O processor 113, and a buffer memory. 102,
It comprises a DMA controller having a DMA transfer function between the stream input unit 101, the video output unit 108, and the audio output unit 109.

The RAM controller 111 can perform burst read and burst write to the SDRAM 300.
SDRAM interface, between SDRAM 300 and buffer memory 102, motion compensator 107 and buffer memory 102
And a DMA controller having a DMA transfer function between them.
The FIFO controller 112 has a dual port RAM, a controller that controls read / write of the RAM, and a pointer management function that manages a pointer indicating an access address in the bit stream FIFO 103.

The I / O processor 113 executes the asynchronous event task by time division multiplexing by allocating as many as six asynchronous event tasks in the AV decoder to six threads. The thread assigned to each asynchronous event task is represented by the number of clock signal cycles used by all components inside the I / O processor for synchronous control, and the length is 4 cycles in principle. I do.

(3.) What kind of processing is the asynchronous event task whose execution is imposed on the I / O processor? What is the asynchronous event task whose execution is imposed on the I / O processor in the AV decoder? Whether such processing contents are described one by one. -Host I / O task This task is a task related to communication with the host computer and drawing of two-dimensional graphics according to the dialog with the operator. More specifically, the process includes a process of communicating with the host computer via the host I / O unit 115, and a process of drawing two-dimensional graphics in accordance with an operation by the operator and outputting the two-dimensional graphics to the video output unit 108. . Purging Task This task relates to a parsing process of an MPEG stream input to the buffer memory 102 and an extracting process of extracting an elementary stream such as a moving image stream, an audio stream, and a sub-video stream from the MPEG stream.

When a purging task is executed, I / O
The processor 113 outputs the MPEG stream input from the outside to the stream input unit 101 to a buffer memory bus (BM bus in the figure) 121. By controlling the buffer memory controller 110, the MPEG stream output to the buffer memory bus 121 is written to the buffer memory 102. Then I / O processor 113
Controls the buffer memory controller 110 to output an MPEG stream to the buffer memory bus 121, and extracts an elementary stream from the MPEG stream. By controlling the buffer memory controller 110, the extracted elementary stream is written to the buffer memory 102. As a result, the buffer memory 102 stores a bit stream, an audio stream, and a sub-picture stream as elementary streams. -Audio stream transfer control task The audio stream transfer control task is a task composed of all transfer controls related to the audio stream.

In accordance with the audio stream transfer control task, the I / O processor 113 controls the buffer memory controller 110 to
Output an audio stream stored as an elementary stream to the SDRAM bus 122. Then, by controlling the RAM controller 111, the SDR
The audio stream output to the AM bus 122 is
Write to M300. When the setup unit 104 starts decoding an audio stream stored in the bit stream FIFO 103, the progress of the decoding process is monitored, and when the remaining amount of the audio stream becomes equal to or less than a predetermined value, the RAM controller 111 is controlled. And SDRAM3
The audio stream stored in 00 is read and output to the SDRAM bus 122. By controlling the FIFO controller 112, the audio stream thus output is written to the bit stream FIFO 103.

By writing to the bit stream FIFO 103, the audio stream is supplemented according to the progress of the decoding of the audio stream. When decoding is completed, the I / O processor 113
12 to output the decoded audio stream to the SDRAM bus 122. By controlling the buffer memory controller 110, the audio stream output to the SDRAM bus 122 is transferred to the buffer memory 10
2 is written. -Moving image stream transfer control task The moving image stream transfer control task is a task composed of all transfer controls related to the moving image stream.

The I / O processor 113 outputs the moving image stream stored in the buffer memory 102 to the SDRAM bus 122 by controlling the buffer memory controller 110 and outputs the moving image stream to the SDRAM bus 122 by controlling the RAM controller 111. The created moving image stream is written to the SDRAM 300. VLD unit 105, IQ / IDC
T unit 106 and motion compensation unit 107 are bit stream FIFO
When the decoding of the moving image stream stored in the video stream 103 is started, the progress of the decoding of the moving image stream is monitored. The stored moving image stream is read, and the FIFO controller 112 writes the moving image stream to the bit stream FIFO 103.
By writing the bit stream FIFO 103 as described above, a moving image stream is supplemented according to the progress of the decoding process. -Video out task The video out task is a task consisting of output control related to video output.

At the time of execution of this asynchronous event task
The I / O processor 113 controls the RAM controller 111 to output the moving image data stored in the SDRAM 300 after being processed by the VLD unit 105, the IQ / IDCT unit 106, and the motion compensation unit 107 to the SDRAM bus 122, By controlling the buffer memory controller 110, the moving image stream output to the SDRAM bus 122 is stored in the buffer memory 1
02. Buffer memory controller 11
0 to output the video stream written in the SDRAM 300 to the SDRAM bus 122,
8 is converted into a video signal. At the same time, the sub-image obtained by developing the sub-image stream and the two-dimensional graphics are mixed and output to the video output unit 108. The setup I / O task consists of processing to be executed when the setup unit 104 and the I / O processor 113 communicate.

If the command is a command for reading / writing a register provided in the host computer, I / O
The read / write process is controlled by controlling the O-processor 113, and if the command is an initialization command for the VLD unit 105 and the IQ / IDCT unit 106, the VLD unit 105 and the IQ / IDCT unit 106 are reset. The asynchronous event task described above has a light processing load, but requires intermittent activation. In particular, the video out task requires activation every 50 μsec during the horizontal blanking period, and the audio out task requires activation every 90 μsec.

(4.) How the I / O Processor is Configured A first embodiment of the I / O processor will be described with reference to the drawings. As described above, the I / O processor monitors whether or not an event to execute each asynchronous event task has been established, and executes the asynchronous event task in which the event has been established with higher priority. If the procedure of the priority execution is also referred to in the present embodiment, the description becomes complicated. Therefore, the description of the priority execution will be made in the third embodiment. In the first embodiment, a basic configuration of an I / O processor, that is, a configuration in which as many as six asynchronous event tasks in an AV decoder are executed by time division multiplexing will be described.

FIG. 3 is a diagram showing the internal configuration of the I / O processor. As shown in FIG. 3, the I / O processor includes an instruction memory 100, an instruction reading circuit 10, an instruction decoding control unit 11, a register set 12, an operation Execution unit 14 and task management unit 1
5 is comprised. The instruction memory 100 stores instructions constituting the above-mentioned six asynchronous event tasks. FIG. 8 is a diagram showing how the instruction memory 100 stores an instruction sequence. In this figure, each instruction has 0-0,
Identifiers such as 0-1, 0-2 are attached. Among the identifiers, the upper number indicates which of the six asynchronous event tasks the instruction belongs to, and the lower number indicates the order of the instruction in the asynchronous event task to which the instruction belongs. In the following description, the location address of each instruction in the instruction memory 100 will be represented using this identifier.

The instruction format of the instruction stored in the instruction memory 100 is defined so that all operations can be accommodated in one instruction word length. In this embodiment, the instruction word length is defined as 16 bits, and the instruction format is shown in FIGS. FIG. 9 shows an instruction format of an arithmetic operation instruction in which a register is specified as an operand. In this instruction format, the register number to be specified in the first operand can be specified in 2 bits to 4 bits, and 5 bits to 7 bits
Can specify the register number to be specified in the second operand. 8bit to 10bit can specify the register number to be specified as the storage destination of the operation result, 5b from 11bit to 15bit
The operation content is specified in it. The lower table shows the upper 5 bits of the 5 bits for which the operation content can be specified.
It shows a combination of 2 bits and lower 3 bits, and the operation content expressed by the combination. For example, if the upper 2 bits are “00” and the lower 3 bits are “000”, the combination expresses the operation of the addition operation, the upper 2 bits are “01”, and the lower 3 bits are “00”.
If "0", the combination represents a subtraction operation. When the upper 2 bits are “00” and the lower 3 bits are “001”, the combination expresses a left shift operation (<< in the figure means left shift operation), and the upper 2 bits
Is "01" and the lower three bits are "001", the combination represents a right shift operation (>> in the figure means a right shift operation).

FIG. 10 shows a read destination address in a register,
This shows an instruction format of a memory load instruction / memory store instruction specifying a write destination address. In this instruction format, a register number to be specified as the first operand can be specified in 2 bits to 4 bits, and a register number to be specified as a read source or a register number to be specified as a storage destination of an operation result can be specified in 5 bits to 7 bits. The operation content is specified in 3 bits from 10 bits to 12 bits, and 3b from 13 bits to 15 bits
A 3-bit immediate value is specified for it.

The lower table shows a combination of the upper 1 bit and the lower 2 bits in the specification of the operation content by 3 bits, and the operation content expressed by the combination. For example, the upper 1 bit is “1” and the lower 2
If the bit is "10", the value of the register specified by the read source operand src_REG is stored in the memory specified using the combination of the first operand src1 and the 3-bit immediate value im: 3 (src1 + im: 3). Specifies a store instruction to be stored in.

The upper 1 bit is “0” and the lower 2 bits are “1”.
0 ', the combination is the first operand src1
Reads the value from the memory by the addressing mode using the combination with the 3-bit immediate value (src1 + im: 3)
A load instruction to be stored in the register specified by dst_REG is specified. FIG. 11 shows an instruction format of a comparison instruction / operation instruction / branch instruction capable of specifying an 8-bit or 11-bit immediate value. If the immediate value is 8 bits in this instruction format, the register corresponding to the storage of the first operand and the operation result can be specified from 5 bits to 7 bits.
Use from it to 15 bits for storing immediate values. When the immediate value is 11 bits, 5 bits to 15 bits are used for storing the immediate value. The operation content is specified as shown in the table below using 4 bits from 2 bits to 5 bits.

The lower table shows the upper 2 bits of the 4 bits.
And the combination of the lower 2 bits and the operation content expressed by the combination. For example, top
When 2 bits are “10” and the lower 2 bits are “01”, the combination specifies a comparison instruction that compares the value of the register specified by the first operand with the immediate value of the second operand and 8 bits. .

The upper 2 bits are “10” and the lower 2 bits are “1”.
If “0”, the combination specifies a multiplication instruction that multiplies the operand by an 8-bit immediate value. When the upper 2 bits are “11” and the lower 2 bits are “11”, the combination specifies an absolute addressing type branch instruction using an 11-bit immediate value as a branch destination address. In the above description, since the operation content is represented by 16 bits, which is one instruction word length, even when an instruction of any operation content in the instruction memory 100 is read, and when any instruction is decoded and executed, the Reading, decoding, and execution can be uniformly completed within one cycle. That is, the instruction format is defined so that the time required for completing the reading, decoding, and execution of the instruction does not vary between instructions. In particular, in FIG.
The intention of this regulation is greatly expressed in the fact that it and 11 bits are used. That is, if the specified immediate value is lengthened, the instruction word length may be extended to 24 bits or 32 bits.
In order to prevent the expansion, the immediate value length is limited to 8 bits and 11 bits so that the instruction word length is within 16 bits. Expressed in units (called CPI (Cycle Per Instruction)) indicating how many cycles are required to execute one instruction, the CPI of this I / O processor is purely "1", "How many times the instruction has been read" and "how many times the instruction has been decoded and executed" are represented by the number of cycles.

The instruction reading circuit 10 outputs a read destination address in the instruction memory 100 to the instruction memory 100.
The instruction decoding control unit 11 (Decoder 11 in the figure) decodes the instruction output from the instruction memory 100, and controls the instruction reading circuit 10 and the operation execution unit 14 according to the result of the decoding.

The register set 12 stores a general-purpose register (GR) having a length of 32 bits and a general-purpose register having a length of 16 bits.
Have a book. The reason why there are as many as twenty-four registers is to allocate four 32-bit registers and sixteen-bit registers to six asynchronous event tasks. By allocating eight registers to each asynchronous event task in this way, it is not necessary to save and restore the register values when switching tasks.

The arithmetic execution unit 14 includes an ALU, a multiplier, and a barrel shifter, and performs an arithmetic operation using values stored in general-purpose registers in the register set 12 under the control of the instruction decoding control unit 11. When switching from the asynchronous event task to another task, the operation execution unit 14
The task management unit 15, which uses the 32-bit general-purpose registers and the four 16-bit general-purpose registers to perform an operation on the instruction included in the switched task, executes the instruction execution in the instruction decoding control unit 11. When the time length of the thread assigned to each task has elapsed, the instruction reading circuit 10
Output to (4.1) How the Instruction Read Circuit 10 Updates the Read Destination Address The following describes how the instruction read circuit 10 updates the read destination address with reference to FIG. FIG. 4 shows the internal configuration of the instruction reading circuit 10.

As shown in FIG. 4, the instruction reading circuit 10
1 + 1 holding unit 20, increment circuit 21, IF2 holding unit 22, D
ECPC storage unit 23, task-specific PC storage unit 24, selector 25
And a selector 26, and is configured to realize pipeline processing for performing two reading stages before the decoding stage. The respective read destination addresses in these two read stages are referred to as a first read destination address IF1 and a second read destination address IF2.

In FIG. 4, IF1 refers to the address output from the selector 26, and IF2 refers to the address held by the IF2 holding unit 22. FIG. 12 is a timing chart showing the pipeline processing performed in the instruction reading circuit 10. Hereinafter, the timing chart will be referred to when referring to the components of the instruction reading circuit 10. IF1 +
The 1 holding unit 20 is used as a count value register for holding a count value. When any one of the read destination addresses is output from the task-specific PC storage unit 24, the address is set as a count initial value. When the count value is incremented by the increment circuit 21, the incremented address is held as the latest count value.

At this time, when a newly incremented address is output from the increment circuit 21, IF1 +
1 The holding unit 20 outputs the address held up to that time to the selector 25 via a signal line,
Output to The increment circuit 21 increments IF1 output from the selector 26 according to the clock signal. The incremented address is held by the IF1 + 1 holding unit 20. Output by selector 26
Since IF1 is the value held by the IF1 + 1 holding unit 20 until then, the count value held by the IF1 + 1 holding unit 20 is incremented every clock by the increment by the increment circuit 21. .

In the timing chart of FIG. 12, the read destination address of the instructions 0-0 output as the read destination address is incremented by the increment circuit 21 (see inc1, inc2, and inc3 in the figure). As a result, the read destination address held by the IF1 + 1 holding unit 20 is updated to the address of the instruction 0-1, the address of the instruction 0-2, the address of the instruction 0-3, and the like.

The IF2 holding unit 22 holds the address previously output by the IF1 + 1 holding unit 20 in synchronization with the clock signal as a second read destination address from which an instruction is to be read. In the timing chart of FIG. 12, the addresses of the instructions 0-0, the addresses of the instructions 0-1,
It can be seen that the address of the instruction 0-2 and the address of the instruction 0-3 are output. It can be seen that these addresses are one cycle behind the first read destination address. When a new address is output from the IF1 + 1 holding unit 20, the IF2 holding unit 22 outputs the address held so far to the DECPC holding unit 23, and also outputs to the selector 25 via a signal line. After the output, the new address output by the IF1 + 1 holding unit 20 is held.

The DECPC holding unit 23 holds the address previously output from the IF2 holding unit 22. This address coincides with the address of an instruction to be subjected to decoding control by the instruction decoding control unit 11. When the new address is output by the IF2 holding unit 22, the new address is held and the address to be decoded is updated. The address held by the DECPC holding unit 23 is the address held by the IF2 holding unit 22 until then, and the address held by the IF2 holding unit 22 is the address held by the IF1 + 1 holding unit 20 until then. Therefore, when compared with the address held by the IF1 + 1 holding unit 20, the address held by the DECPC holding unit 23 is delayed by two instructions, and when compared with the address held by the IF2 holding unit 22, The address held in the DECPC holding unit 23 is delayed by one instruction.

The task-specific PC storage section 24 is a memory circuit having an area for holding a read destination address for each task therein or an address register provided for each task.
In the internal area or in each address register, a 3-bit task identifier is assigned as an address to a read destination address stored individually. The task
The read destination address of (0) is called IPC0, and the read destination address of task (1) is called IPC1. The same applies to task (2), task (3), task (4), and task (5).

The read / write operation of these read destination addresses in the task-specific PC storage unit 24 is performed by the task management unit 15 to instruct the task switching (task switching signal chg_task_e).
This is performed when (High value of x) is output. When the task switching signal chg_task_ex is at the high value, the task management unit 15 executes the task switching signal chg_task_ex together with the task switching signal chg_task_ex and executes the task with the 3-bit identifier (write address selection signal taskid (wr_adr)) and the next task to be executed. 3-bit identifier (read address selection signal nxt
taskid (rd_adr)) is output, but the task-specific PC storage unit 2
4 reads and writes the internal area according to these signals.
That is, the task-specific PC storage unit 24 uses the write address selection signal.
The taskid (wr_adr) is interpreted as an address in the task-specific PC storage unit 24, and the selector 2 is stored in the internal area designated by the taskid (wr_adr).
5 is stored. In the timing chart of FIG. 12, the task switching signal chg_task_e
At timings a1 and b1 when x rises, writing a2 and b2 of the read destination address are performed.

When the write a2 is performed, the IF2 holding unit 22 holds the address of the instruction 0-3, and the IF1 + 1 holding unit 20 adds "1" to the address of the instruction 0-3. Addresses 0-4 are output to the selector 25 via signal lines. When output in this way, addresses 0-4 are
It is stored in the C storage unit 24. Thus, when the next thread goes around the task (0) in the task-specific PC storage unit 24, the task (0) is read from the address 0-4.

When writing b2 is performed, the IF2 holding unit 22 holds the address of the instruction 1-3, and the IF1 + 1 holding unit 20 adds “1” to the address of the instruction 1-3. The selected address 1-4 is output to the selector 25 via a signal line. When output is performed in this manner, the incremented addresses 1-4 are stored in the task-specific PC storage unit 24. Thus, when the next thread goes around the task (1) in the task-specific PC storage unit 24, the task (1) is read from the address 1-4.

The read address selection signal nxttaskid
When (rd_adr) is given from the task management unit 15, the task-specific PC storage unit 24 stores the identifier in the task-specific PC storage unit 24.
And reads the address of the asynchronous event task from the internal area designated by the address and outputs it to the selector 26. In the timing chart of FIG. 12, the read address selection signal nxttaski
The identifier (1) is given from the task management unit 15 as d, and ch
When g_task_ex rises (see reference symbol a3), the task-specific PC storage unit 24 stores the task designated by the identifier.
It interprets (1) as an address in the task-specific PC storage unit 24, extracts the read destination address (1-0) stored there, and outputs it to the selector 26 (see reference numeral a4).

At the timing when the address of the instruction 2-0 is output as the read destination address IF1, the identifier (2) is given as the read address selection signal nxttaskid from the task management unit 15, and the chg_task_ex rises (see reference numeral a5). Then, the task-specific PC storage unit 24 extracts the read destination address (2-0) as the read destination address of the task (2) specified by the identifier and outputs it to the selector 26 (see reference numeral a6).

When the read destination address is output as described above, only four instructions of task (0) are executed, and subsequently, only four instructions of task (1) are executed. Or later,
Instruction sequences of task (2), task (3), task (4), and task (5) are each executed by four instructions. The selector 25, which is a 4-input-1-output selector, selectively selects one of the addresses transmitted to the signal lines of the task-specific PC.
Output to the storage unit 24. Which one of these is selected is as shown in the output logic table shown in FIG. 5, and the instruction decoding control unit 11 outputs the selpc output according to the decoding result of the instruction.
This is done based on the signal. The signal line here is the output of the IF1 + 1 holding unit 20, and when the task switching signal chg_task_ex is switched to the high value by the task management unit 15, the selector 25 selects this.

The signal lines are connected to the instruction decoding control unit 11 and the operation execution unit 14, respectively. Is
When decoding a branch instruction using absolute addressing,
This is selected to obtain the immediate value of the branch instruction from the instruction decoding control unit 11 as the branch destination address. Is used when decoding a branch instruction using indirect reference designation.
Is selected when the address calculated by the above is used as the branch destination address.

The selector 26 is a 2-input / 1-output selector. The selector 26 selects an address after increment by the increment circuit 21 during a period when the task switching signal chg_task_ex is Low, and outputs the selected address as IF1 to the increment circuit 21 and the IF2 holding unit 22. I do. Task switching signal chg_task_ex is High
The address of the next task to be executed stored in the task-specific PC storage unit 24 during the period of
The signal is output to the circuit 21 and the IF2 holding unit 22.

According to the instruction reading circuit configured as described above, at the time of task switching, the read-out address of the task that has been executed so far is stored in the task-specific PC storage unit 24 by the selector 25, and is replaced with this. Then, the address of the next task stored in the task-specific PC storage unit 24 is output by the selector 26 as IF1. The above switching of the read destination address is performed in one cycle, and the switching of the read destination address does not require the I / O processor to perform extra processing. There is no need to invalidate the address read out earlier, as in the case of branching when an interrupt signal is notified. Therefore, the saving and restoring of the read destination address by the instruction reading circuit 10 are performed without generating overhead. (4.2) How the task management unit 15 determines an asynchronous event task to be executed next The figure shows how the task management unit 15 determines an asynchronous event task to be executed next with an internal configuration. 6 will be described with reference to the internal configuration of the task management unit 15 shown in FIG.

FIG. 6 is a diagram showing the internal configuration of the task management unit 15. As shown in FIG. 6, the task management unit 15 includes a thread manager 61 and a scheduler 62.
The thread manager 61 is a flip-flop 51,
The scheduler 62 includes a counter 52 and a comparator 54. The scheduler 62 includes a task ID storage 71, a task ID storage 72,
It comprises a task round management unit 73 and a priority encoder 74.

The flip-flop 51 holds an integer value indicating the next instruction to be executed (this is called a count value i). The counter 52 is a counter whose initial value is set to “1” and whose upper limit value is set to “4”.
The count value held at 1 is counted up as 1,2,3,4,1,2,3,4.

The comparator 54 compares the value counted up by the counter 52 with the integer value “4”, and if the count value of the counter 52 matches the integer value “4”,
Selector 2 by setting task switching signal chg_task_ex to High value
6 and the task-specific PC storage unit 24. Thus, every time the counter 52 counts “4”, the task switching signal
By setting chg_task_ex to High, the selection of the task-specific PC storage unit 24 by the selector 26 is performed once every four cycles. At this time, the task-specific PC storage unit 2
4 outputs the read destination address of the task to which the thread is to be allocated next to the selector 26, so that the output of the read destination address from the task-specific PC storage unit 24 is performed once every four cycles. .

The task ID holding unit 71 holds an identifier of a task whose instruction execution is counted by the counter 52 (this is called a task identifier taskid). FIG. 7A shows an example of the task identifier. As shown in FIG. 7A, the task identifier uses three bits to indicate any one of the six tasks stored in the instruction memory 100. When the instruction execution count is performed four times, the task identifier of the task to which the next thread is to be assigned from the priority encoder 74 in the scheduler 62
The taskid is output. At this time, the task ID holding unit 71
Outputs the task identifier taskid held so far to the task round management unit 73, and holds the newly output task identifier taskid.

The task round management unit 73 monitors how the task ID has been updated in the task ID holding unit 71, and uses a 6-bit register to assign a thread among the six tasks. Manage. When the counter 52 counts the execution of the four instructions, the task ID holding unit 71 outputs a task identifier taskid, and the task round management unit 73 outputs a numerical value indicating the task to which the thread has been allocated (this numerical value is represented by the round value ta).
skn) is output to the priority encoder 74. An example of the round value taskn is shown in FIG. In this round value taskn, if the first bit is “1”, it indicates that a thread has been allocated to task (1). If the first bit is “0”, it indicates that task (1) is not. Show. If the second bit of the task management register 13 is “1”, it indicates that the thread is allocated to the task (2), and if the second bit is “0”, it indicates that the task (2) is not. .

When the threads are assigned to the tasks (0) and (1), the task round manager 73 outputs “000011” to the priority encoder 74. Also tasks
If the threads are assigned to (0), task (1), and task (2), the task round management unit 73 outputs “000111” to the priority encoder 74, and outputs the tasks (0),
When the threads are assigned to (1), task (2), and task (3), the task round management unit 73 outputs “001111” to the priority encoder 74.

When the thread allocation to tasks (0) to (5) has completed one cycle, "111111" is output to the priority encoder 74, and then the 6-bit register is set to "00000".
Reset to "0". Priority encoder 74
Is the round value ta output from the task round management unit 73.
Receiving the skn, the received task round management unit 73
In the round value taskn, the bit number at which the inversion from “1” to “0” occurs is detected. When the bit inversion to “0” is detected, the task identifier taskid of the task assigned to the bit inversion is output to the task ID holding unit 71. The output task identifier is the address selection signal nxttaskid (rd_adr)
Is output to the task-specific PC storage unit 24.

For example, when “000011” is output as the round value taskn from the task round management unit 73, the priority encoder 74 determines that the inversion of “0” has occurred in the second bit from the lower order in the round value taskn. (Note that the least significant bit is counted as a zero bit). Since the second bit is a bit assigned to the task (2) in FIG. 7B, the priority encoder 74
The task identifier (2) is output to the task ID holding unit 71.

For example, when “000111” is output as the round value taskn from the task round management unit 73, the priority encoder 74 determines that the inversion of “0” has occurred in the third bit from the lower order in the round value taskn. Is detected. Since this third bit is a bit assigned to task (3) in FIG. 7B, the priority encoder 74 outputs the task identifier taskid of task (3) to the task ID holding unit 71. Round value
Since taskn indicates a task to which a thread has already been assigned, a bit inverted to “0” in this round value taskn indicates which task is to be assigned a thread next. When the bit inverted to “0” is converted into the task identifier taskid, the task ID holding unit 7
1 stores a task to which a thread is to be assigned next.

When the priority encoder 74 outputs a new task identifier taskid, the task ID holding unit 72 holds the previously output task identifier taskid as a write address selection signal taskid (wr_adr), and stores the task ID in the PC for each task. Output to the unit 24. FIG. 13 shows how threads are allocated by the I / O processor of the first embodiment configured as described above. FIG.
Indicates a unit called a frame formed by arranging threads assigned to tasks from task (0) to task (5) in chronological order.

Tasks (0) to (5) are each assigned a 4-cycle thread, so that a 24-cycle frame is formed. With this frame, the instruction sequence shown in FIG. 7 is uniformly executed every four instructions. (5.) Calculation of Number of Operation Clocks How the number of operation clocks is calculated in the I / O processor of the first embodiment will be described with reference to FIG. FIG. 55 is a timing chart showing how a moving image stream and an audio stream are processed when a video out task and an audio out task are executed by thread allocation in the first embodiment. Here, in order to guarantee the real-time performance of the video-out task and the audio-out task, the video-out task for converting the video stream into a video signal is 50 μsec based on the cycle of the display horizontal synchronization signal.
In this example, it is assumed that an image for one line must be processed, and that an audio out task for converting an audio stream into an audio signal must process a predetermined audio stream at a period of 90 μsec.

In this case, first, in the above-mentioned cycle, the minimum digestion number of "this number of instructions must be executed at least" is derived. Here, to decode one line of video data, 44
At least eight instructions must be executed, and in order to decode one cycle of audio data, at least 808 instructions in the audio out task must be executed. In this embodiment, CPI = 1 and the number of instructions is equivalent to the number of cycles. Therefore, the number of cycles to be allocated to the video-out task and the audio-out task from the minimum digest number is 448 (= 4 × 112) cycles, 808 (= 4 × 202) cycles.

Each of the tasks (0) to (5) is executed by four cycles. Here, no overhead occurs due to the switching of the program counter by the selector 25 and the selector 26 in the instruction reading circuit 10, so that
The time required for one round of task (0) to task (5) is substantially 24 cycles. 4 instruction cycles and 6 tasks
Therefore, all tasks are executed by four instructions in 24 cycles.

Then, the time required for one cycle S1, S2
Must satisfy the following equation. 50μsec> 6 × 4 × 112 × S1nsec 90μsec> 6 × 4 × 202 × S2nsec S1 <50μsec / 6 × 4 × 112 = 18.6nsec S2 <90μsec / 6 × 4 × 202 = 18.56nsec The number of operation clocks is 1 ÷ S2nsec From calculation, 54MHz = 1 ÷ 18.56nsec. With the above calculations, the optimal number of operation clocks for completing the processing of the video out task and the audio out task can be uniquely derived. As described above, according to the present embodiment, the optimal lower limit of the number of operation clocks is the minimum digestion number of instructions that must be executed in a predetermined cycle,
It can be uniquely derived from the execution cycle and the total number of tasks. Since the optimum lower limit value of the operation clock is determined, the real-time performance of the audio out task and video out task can be guaranteed without setting the operation clock signal to a higher level. In this case, the MPEG stream can be suitably decoded.

Further, by providing an I / O processor for executing a plurality of asynchronous event tasks in a time-division multiplex manner, it is not necessary to process asynchronous event processing by interruption. The IQ / IDCT unit 106 can concentrate on the processes of inverse quantization, inverse discrete cosine transform, and motion compensation. In addition, the I / O processor switches and executes tasks at high speed without the overhead of saving and restoring the value of the program counter. Real-time performance.

In the present embodiment, the number of threads for each task is uniformly set to four, but may be set to different values according to the processing contents of each task.
When the number of cycles is made variable for each task, the thread manager shown in FIG. 6 is configured as shown in FIG.
In this figure, the selector 200 is a task (0) to a task (0).
(Cycle number for cycle number for
It is connected to “task0” to “cycle number for task5”, and outputs the number of cycles corresponding to the nxttaskid output from the scheduler 62 to the comparator 54 as an alternative. In FIG. 26, the next task to be assigned a thread
If (0), selector 200 is "cyclenumber for task0"
Is output to the comparator 54. With this configuration, the optimal number of cycles according to the respective processing loads from task (0) to task (5) can be distributed to each task.
Further, such an optimal number of cycles may be stored in a memory or a register, and may be rewritten later.

Further, in the present embodiment, the task to be executed has been described as being limited to the asynchronous event task, but another task may be used. (Second Embodiment) In the first embodiment, the number of instructions assigned to each task thread is uniformly set to four cycles.
In this embodiment, each task can independently change how many cycles are allocated to one thread. Assignment to thread is Wait_Until_Next
Made by instruction. The Wait_Until_Next instruction is an instruction to abort an instruction in a thread in the middle and to postpone a series of instruction sequences located next to the Wait_Until_Next instruction to the next thread. Note that the destination address is stored when the Wait_Until_Next instruction is decoded. At this time, the 5-input / 1-output selector 25 shown in FIG. Task pc
It is stored in the storage unit 24.

FIG. 14 shows a Wait_Until_Next instruction (W in FIG. 14).
FIG. 16 is a timing chart showing how the asynchronous event task of FIG. 14 is executed. When the Wait_Until_Next instruction is stored as instruction 0-1 as the first instruction of the asynchronous event task as shown in FIG.
When stored in the PC holding unit 23 and decoded by the instruction decoding control unit 11, the selector 25
The read destination address 0-2 is stored in the task-specific PC storage unit 24 (the same applies to FIG. 16). Thereafter, the instruction decoding control unit 11 invalidates the instructions 0-2 and 0-3 ("NOP" in FIG. 16).

Here, the instruction 0-2 is an instruction for reading the value of the address mem1 in the local memory of the I / O processor into the register r0 in the register set 12, and the instruction 0-3 is an instruction for reading the local memory of the I / O processor. Is an instruction to read the value of the address buf1 in the register into the register r1. Instruction 0-4 is an instruction for multiplying the value of register r0 by the value of register r1 and storing the result in register r2.Instruction 0-5 is an instruction for multiplying the value of register r2 by I / O.
This is an instruction to be stored at address mem1 in the local memory of the processor.

In the above four instructions, both the read destination address and the write destination address are local memories of the I / O processor, and the instructions 0-0 are Wait_Until_Next instructions. It can be seen that the instruction of read destination address-write destination address is stored in one thread. FIG. 15 shows an example of the instruction format of the Wait_Until_Next instruction. In FIG. 15, this instruction has the instruction format of the register designation type arithmetic operation instruction shown in FIG. 11bit to 13b of this format
By specifying it as “010”, the I / O processor executes the operation of the Wait_Until_Next instruction.

The I / O of the second embodiment configured as described above
How a thread is allocated by the O processor will be described with reference to FIG. task
Four cycle threads are assigned to (1), task (2), task (3), task (4), and task (5). But the task
Since the wait_until_next instruction exists in (0), the thread assigned to task (0)
This is the position where the instruction is located, and the thread allocated to the task (0) has two cycles.

In the next frame formed after the task (0) to the task (5) make a round, the task (1) is assigned a thread of four cycles like the other tasks. As described above, according to the present embodiment, it is possible to centrally execute a memory access instruction having the same memory as an access destination in one thread. (Third Embodiment) In the first embodiment, regardless of whether or not an event to start an asynchronous event task is established, threads are fairly allocated to the six asynchronous event tasks. Asynchronous event tasks that do not have the same and the asynchronous event tasks that need to do so are substantially equal in time. In the third embodiment, the asynchronous event task checks whether or not an event to start the asynchronous event task is established, and reduces the number of allocated cycles for the task for which the event to be started is not established. Control as follows.

FIG. 18 shows the internal configuration of the I / O processor according to the third embodiment. In FIG. 18, the point that the I / O processor includes the instruction memory 100 and the instruction reading circuit 10 is the same as the first embodiment. What is new in the third embodiment is that the instruction decoding control unit 11 and the operation execution unit 14 are replaced with an instruction decoding control unit 81 and an operation execution unit 84, respectively. Another point is that seven state monitoring registers are added, and a task management register 13 is provided inside the task management unit 15.

Each of the seven status monitoring registers CR1 to CR7 is a 5-bit register, and components located around the I / O processor in the AV decoder, that is, the video output unit 108, the buffer memory controller 110, RAM controller 111, FIFO controller 1
12 and the like, and the success or failure of five events in the peripheral portion of the I / O processor is reflected in each bit (the video output unit 108, the buffer memory controller 110, the RAM controller 111, and the FIFO controller). Since the connection with 112 is complicated, its illustration is omitted.)

As an example, FIG. 2 shows the state monitoring register CR1, the state monitoring register CR2, and the state monitoring register CR3.
3 will be described. FIG. 23 is a diagram showing a bit configuration of the state monitoring register CR1, the state monitoring register CR2, and the state monitoring register CR3. The 0th bit of the status monitor register CR1 is normally set to “0”, and is set to “1” only when data transfer to the buffer memory 102 on the buffer memory bus 121 has been performed a predetermined number of times.

The first bit of the state monitoring register CR1 is normally set to “0”, and is set to “1” only when the start code of the MPEG stream output to the buffer memory bus 121 is detected. The second bit of the status monitor register CR1 is normally set to “0”, and is set to “1” only when the presence of valid data of one byte or more in the MPEG stream output to the buffer memory bus 121 is confirmed. You.

The third bit of the state monitor register CR1 is normally set to “0”, and is set to “1” only when the buffer memory 102 has more than 3 bytes of valid bits in the buffer. This bit is used for communication between the purging task, the audio stream transfer control task, and the moving image stream transfer control task. The 0th bit of the state monitoring register CR2 is normally set to “0”, and is set to “1” when a request to support the transfer to the SDRAM 300 is issued on the buffer memory 102. This bit is used for communication between the purging task, the audio stream transfer control task, and the moving image stream transfer control task.

The first bit of the state monitoring register CR2 is normally set to “0”, and is set to “1” only when the DMA transfer is completed. The second bit of the status monitor register CR2 is normally set to “0”, and the bit stream FIFO1
It is set to "1" only when there is a transfer request to the 03. The third bit of the status monitor register CR2 is normally set to “0”, and is set to “1” when the control register inside the FIFO controller 112 is updated. The 0th bit of the state monitoring register CR3 is normally set to “0”, and is set to “1” when the buffer memory 102 enters the DMA_READY state.

The first bit of the state monitoring register CR3 is normally set to “0”, and is set to “1” when the DMA transfer to the SDRAM 300 is completed. Second of status monitor register CR3
The bit is normally set to "0", and set to "1" at the fall of the horizontal retrace signal in the externally connected display device.

The third bit of the status monitor register CR3 is normally set to “0”, and is set to “1” when the video signal in the externally connected display device enters the horizontal blanking period. The fourth bit of the status monitor register CR3 is normally set to "0", and is set to "1" only when a processing request for the video out task occurs.

As described above, the three state monitoring registers are:
It indicates the control state of each buffer and controller in the AV decoder. The same applies to other status monitoring registers. The seven status monitoring registers enable the I / O processor to monitor each asynchronous event task to determine whether or not various events that cause its activation are established. . The operation execution unit 84 has a configuration having the same function as the operation execution unit 14. The first thing different from the operation execution unit 14 is that the number and immediate value assigned to each status monitoring register such as CR1 to CR7 are received from the instruction decoding control unit 81, and the values held by the designated status monitoring register are received. The point is that subtraction for comparison with the immediate value is performed. The zero flag and the carry flag are turned on / off in accordance with the result of the subtraction, and the instruction decoding control unit 81 is notified of the coincidence, inconsistency, and magnitude of the immediate value with the value held in the state monitoring register.

In the above notification, the instruction decoding control unit 81 can output a signal to invalidate the operation currently being executed, but upon receiving this signal, the operation execution unit 84 interrupts the storage of the value in the general-purpose register. . The instruction decoding control unit 81 has a function similar to that of the instruction decoding control unit 11, but differs from the instruction decoding control unit 11 in that the instruction decoding control unit 81 stores an instruction that can form an event waiting loop in an instruction memory. 100 and read the number and the immediate value assigned to each state monitoring register, such as CR1 to CR7, when decoding it.
Output to The instructions constituting the event waiting loop are as follows:
This is the content of the following {Example 1}. After outputting the designation of the state monitoring register and the immediate value to the operation execution unit 84, the operation execution unit 84 notifies the instruction decoding control unit 81 of the match, mismatch, and magnitude of the held value and the immediate value by the zero flag and the carry flag. The decoding control unit 81 refers to this and, if notified of the mismatch between the held value and the immediate value, outputs a signal indicating that the event is not established to the task management register 13 and invalidates the execution result of the next instruction. To the instruction execution circuit 84 to notify the instruction reading circuit 10 not to advance the value of the read destination address. If a mismatch between the held value and the immediate value is notified, a signal indicating that the event has been established is output to the task management register 13. << Example 1 >> Instruction Whether the establishment of event i is true or false is determined, and if the establishment of event i is false, the read destination address is not advanced.

The mnemonic of this instruction is shown in {Example 2}. {Example 2} cmp_and_wait cr_statei, immediate {cr_statei (i = 0,1,2,
The description of 3, 4,... 7) means that any one of the seven state monitoring registers in the I / O processor can be designated.

By combining the designation of the status monitor register in the first operand and the immediate value designation in the second operand, it is possible to confirm the success or failure of any of the 35 events. The above instruction is referred to as Cmp_And_
This is called a Wait instruction. The event waiting loop described above
It goes without saying that this occurs when the success or failure of the event specified in the first operand and the second operand of the Cmp_And_Wait instruction is determined many times.

FIG. 19 shows the configuration of the instruction reading circuit 10 in the third embodiment in which a change has been made. In FIG. 19, the instruction reading circuit 10 includes an IF1 + 1 holding unit 20, an increment circuit 2
1. There is no difference from the first embodiment in that it includes an IF2 storage unit 22, a DECPC storage unit 23, a task-specific PC storage unit 24, a selector 25, and a selector 26. What is new in the instruction reading circuit 10 is a flip-flop 27 connected to the output stage of the DECPC holding unit 23.

The flip-flop 27 has the Cmp_And_Wait
The instruction decoding control unit 81 holds the value of the DECPC holding unit 23 so that the instruction decoding control unit 81 can output the read destination address of the instruction being decoded to the selector 25 in case the event specified by the instruction is not satisfied. If an instruction to return the program count value is given from the instruction decoding control unit 11, the flip-flop 27 outputs the held value to the selector 25 through the signal line.
And the selector 25 outputs the flip-flop 2
The input source of the task-specific PC storage unit 24 is switched to the signal line so that the held value of 7 is stored in the task-specific PC storage unit 24. FIG. 20 shows an output logic table of the instruction reading circuit according to the third embodiment.

FIG. 26 is a timing chart of the components of the I / O processor in the frame when the Cmp_and_Wait instruction is decoded. The role of the flip-flop 27 in this timing chart will be described. FIG.
In step 6, the flip-flop 27 stores Cmp_a
When the address of the instruction 0-0 corresponding to the address of the nd_Wait instruction is output as indicated by reference numeral a7, the address of the instruction 0-0 is stored in the task-specific PC storage unit 24 as IPC0. As a result, the task-specific PC storage unit 24 stores Cmp_an as IPC0.
The address of the d_Wait instruction will be stored.

FIG. 21 shows the internal configuration of the task management unit 15 in this embodiment. The task management register 13 shown in FIG. 21 is a register to which bits for individually managing tasks that have entered an event waiting loop (hereinafter referred to as a wait state) are assigned. When the task management register 13 receives a signal indicating that the event is not established from the instruction decoding control unit 81,
Task identifier taskid held by the task ID holding unit 72
And switches the bit corresponding to the task identifier taskid to “1”. Conversely, when a signal indicating that the event is established is notified, the task ID holding unit 72 refers to the task identifier taskid held and switches the bit corresponding to the task identifier taskid to “0”.

FIG. 22 shows a bit configuration for managing a wait state task in the task management register 13. In the figure, if the 0th bit is “1”, it indicates that the task (0) is in a wait state, and if the 0th bit is “0”, it indicates that the task (0) is not. In the figure, the first
If the bit is “1”, it indicates that the task (1) is in a wait state, and if the first bit is “0”, it indicates that the task (1) is not. If the second bit of the task management register 13 is “1”, it indicates that the task (2) is in a wait state, and if the second bit is “0”, it indicates that the task (2) is not. By managing the event waiting loop by the task management register 13, it is possible to individually manage the event waiting loops that occurred frequently in a plurality of tasks.

In the timing chart of FIG. 26, assume that instructions 0-0 are decoded as Cmp_and_Wait instructions, and it is determined that the event is not established. In this case, the instruction decoding control unit 81 notifies that the task (0) has entered the event establishment waiting state as indicated by reference numeral a8. Then, the task management register 13 sets the bit corresponding to the task identifier of the task (0) to “1” as indicated by reference numeral a9.

Next, how the bits allocated to the task management register 13 are set in “waiting for event establishment”, “at the time of event establishment”, and “after the event establishment” will be described with reference to a timing chart. explain. FIG. 27 is a timing chart when the event is established, FIG. 28 is a timing chart when the event is established, and FIG. 29 is a timing chart after the event is established.

Assume that the event waiting for the execution of the Cmp_and_Wait instruction in task (0) is established in FIG.
In this case, the instruction decoding control unit 81 notifies that the event has been established, as indicated by reference numeral d1. Then, the task management register 13 sets the bit corresponding to the task identifier of the task (0) to “0” as indicated by reference numeral d2. The internal configuration of the thread manager 61 according to the third embodiment will be described with reference to FIG. There is no difference from the first embodiment in that the thread manager 61 includes a flip-flop 51, a counter 52, and a comparator 54. What is new in FIG. 21 is the ID converter 53.
And the selector 55.

The ID converter 53 includes a task ID holding unit 72
When the identifier of the task to which a thread is to be allocated next is output, it is determined whether the task set in the wait state in the task management register 13 matches the task identifier taskid to which the thread is to be allocated next. If they match, a High value is output to the selector 55, and if they do not match, a Low value is output to the selector 55.

The selector 55 outputs “2” or “4” according to the High value and Low value of the signal output from the ID converter 53.
Is output to the comparator 54 as an alternative. In FIG. 26, if the task to which a thread is to be allocated next is task (0), a low value is output to the selector 55 at reference numeral a10. Output. However, the bit for task (0) is set to "1" at reference numeral a9 in FIG. 26, and as shown by reference numeral g1 in FIG.
, The selector 55 outputs “2” to the comparator 54 as indicated by reference numeral g2.

When the bit for task (0) is set to “0” at reference numeral d2 in FIG. 28 and a High value is output to selector 55 as shown at reference numeral g5 in FIG. "4" as indicated by reference sign g6
Is output to the comparator 54. The selector 55 selectively outputs the numerical value of “2” or “4” to the comparator 54, so that one of a two-cycle thread and a four-cycle thread is assigned to each task. When the selector 55 outputs “2”, the second instruction is invalidated. As a result, a thread of one cycle is allocated.

The operation of the components of the instruction reading circuit 10 and the components of the task management unit 15 shown in the timing charts of FIGS. 26 to 29 will be described along the time axis of the timing chart. Assume that the bits of the task management register 13 are all zero in the initial state. 26, when the reading of the instruction is started from the task (0), the bit for the task (0) is set to “0” in the task management register 13. The selector 55 outputs “4” as the upper limit value of the counter. Since the upper limit value of the counter is set to "4", the task (0) is to be executed for four cycles. 2
Write the read destination address of instructions 0-0 to 4. At the same time, the 0th bit of the task management register 13 is set to “1” when the Cmp_and_Wait instruction is executed, as indicated by reference numerals a8 and a9. With this setting, task (0) waits for the establishment of an event. After setting the bits in this way, the task
It is assumed that execution of (1), task (2), task (3), task (4), and task (5) has been completed and the process has shifted to the next frame.

In the event establishment waiting state, it is assumed that only the task (0) of the task management register 13 is "1" and the other bits are zero. Then, when the reading of the instruction is started from the task (0) in FIG. 27,
The bit for task (0) is stored in task management register 13
Is set to "1", the selector 55 sets the upper limit of the counter to "2" as shown by reference numeral g2.
Is output. Since the upper limit of the counter is set to "2", the task (0) is to be executed for two cycles, but the instruction 0
-0 is the Cmp_and_Wait instruction, so the task-specific PC storage unit 2
Write the read destination address of instructions 0-0 to 4. After such writing, it is assumed that the task (1), the task (2), the task (3), the task (4), and the task (5) have been executed and the process has shifted to the next frame.

It is assumed that an event has occurred in the next frame. In FIG. 28, when the reading of the instruction is started from the task (0), the bit for the task (0) is set to “1” in the task management register 13, so that the selector 55 "2" is output as the upper limit value of the counter. Since the upper limit of the counter has been set to "2", task (0) is to be executed for two cycles.

At the time of execution of the Cmp_and_Wait instruction, which is the instructions 0-0, the establishment of the event is confirmed.
As shown in (1), the 0th bit of the task management register 13 is set to “0” when the Cmp_and_Wait instruction is executed. With this setting, task (0) is released from waiting for event establishment. After setting the bits in this way, it is assumed that the task (1), task (2), task (3), task (4), and task (5) have been executed and the process has shifted to the next frame.

In the frame after the occurrence of the event shown in FIG. 29, the bit for task (0) is set to “0” in the task management register 13, so that the selector 55 "4" is output as the upper limit value. Since the upper limit value of the counter is set to “4”, task (0) is executed for four cycles. FIG. 24 shows how threads are allocated by the I / O processor of the third embodiment configured as described above.
This will be described with reference to FIGS.

In FIG. 24A, task (0), task
(3), task (4), and task (5) are all memory transfer control tasks, and the first instruction is a Cmp_and_Wait instruction. Here, in the state of FIG. 24 (b), assuming that the event waiting for these Cmp_and_Wait instructions has not been established, a two-cycle thread is assigned to task (0), task (3) to task (5). Assigned, the second instruction is invalidated, but a thread of 4 cycles is assigned to task (1) and task (2).

In FIG. 24C, tasks (0) to task
It is assumed that (5) circulates several times, and only the event for which the Cmp_and_Wait instruction of task (0) is waiting has been established. Then, in the frame in which the event is established, the task (3) to the task (5) are still assigned a two-cycle thread, and the second instruction is invalidated.
In (0), the second instruction is executed because the event is established.

In the frame after the occurrence of the event j0 in FIG. 24D, the same 4-cycle thread as the tasks (1) and (2) is assigned to the task (0). FIG. 25 shows an example of an instruction format of the Cmp_and_Wait instruction. In FIG. 25, 3 bits from 5 bits to 7 bits
Can be used to specify any of the seven status monitoring registers, and a 5-bit immediate value can be stored using 11 to 15 bits. The operation content can be specified using 9 to 10 bits of this format. This 2bit is "10"
, The I / O processor executes the operation of the Cmp_and_Wait instruction. In addition, these 2 bits are changed to "0
By specifying "0", the I / O processor executes the operation of the instruction to compare the value of one of the seven state monitoring registers with the 5-bit immediate value.

As described above, according to the present embodiment, by assigning a thread having a short time length to the memory transfer control task waiting for a state in which memory access is possible,
You can improve the progress of other tasks. (Fourth Embodiment) The fourth embodiment relates to a technique of allocating more threads to the video-out task in the horizontal blanking period and the vertical blanking period of the display.

An I / O processor that increases the number of threads is
FIG. 30 shows the configuration of the task management unit 15 in the first embodiment.
31 is realized by adding the changes shown in FIG. The I / O processor according to the fourth embodiment is the same as the third embodiment in that it includes an instruction memory 100, an instruction reading circuit 10, an instruction decoding control unit 81, an operation execution unit 84, and a task management unit 15. What is new in the fourth embodiment is that the task management register 13 monitors the emergency state transition permission signal iexecmode.

FIG. 30 shows the internal configuration of the task management unit 15 in the fourth embodiment. The three bits in the task management register 13 in FIG.
The identifier of the task requiring urgent handling is specified using 3 bits in 3. Which one of the six tasks is treated as urgent in the three bits is appropriately changed according to the content of the emergency state transition permission signal iexecmode. In the present embodiment, the emergency state transition permission signal iexecmode corresponds to a horizontal blanking period, a vertical blanking period, and the like.

Which task is registered in the task management register 13 as a task requiring urgent handling is determined by referring to the task management register 13 which task contains an emergecy instruction. Shall be. When the instruction decoding control unit 81 decodes an instruction to be executed next, if the decoding result is an emergecy instruction, the task management register 13 holds a task including the instruction as an urgent task.

FIG. 31 shows the internal configuration of the scheduler 62 in the fourth embodiment. In FIG. 31, there is no difference from the first embodiment in that the scheduler 62 includes the task ID holding unit 72. What is new in FIG. 31 is that the task round management unit 73 and the priority encoder 74 are replaced with a task round management unit 75 and a priority encoder 80, respectively. Also, the converter 76, the emergency task mask unit 77 and the task ID
The point is that the holding unit 83 is added.

The difference between the task round management unit 75 and the task round management unit 73 is that the task round management unit 73
Monitors how the task identifier has been updated in the task ID holding unit 71, and manages the tasks to which the threads have been allocated among the six tasks using a 6-bit register. Task round management unit 75
The point is that the management of tasks to which threads have been assigned is performed separately in task management in a normal period and management of normal tasks in an emergency period. For example, when the task (1) is executed in the task management register 13 in an interleaved manner, five of the six tasks are task (0), task (2), task (3), task (4), and task (4). (Five)
And so on.

When the five tasks are circulated as described above, the round value indicating the task that has been executed needs to be represented by a value without the emergency task managed in the task management register 13. As described above, the task round management unit 75 outputs the round value taskne without the emergency task to the emergency task mask unit 77 separately from the round value taskn in order to manage the round value without the emergency task. By the way, "ne" in taskne is derived from the initials of "Not" and "Emergency".

The converter 76 has a task management register 1
3 is converted to a 6-bit round value emgcytask. Emergency task mask part 7
7 is a round value emgc converted by the converter 76.
An OR circuit 78 is provided for performing a 6-bit OR operation of ytask and the round value taskne output from the task round management unit 75.

Here, ORing in the OR circuit 78 means calculating a 6-bit length round value including both the round value taskne and the round value indicating the urgent task. For example, the round value taskne is “001101” indicating that a thread has been allocated to task (0), task (2), and task (3), and the round value emgcytask indicates that the urgent task is task (1). In the case of “000010”, the output of the OR circuit 78 is “001111” indicating that a thread has been assigned to the task (0), the task (1), the task (2), and the task (3).

The priority encoder 80 has, in addition to the function of the priority encoder 74, a round value taskne (round value) output from the task round management unit 75.
maskne), and detects at what bit the inversion from “1” to “0” occurs in the received round value taskne (round value maskne) of the task round management unit 73. When a bit that has been inverted to “0” is detected in this way, the task identifier taskid of the task assigned to this inverted bit is individually set to each task.
It is stored in the ID holding unit 83.

For example, the round value maskne “000111” which is the logical sum of the round value of the urgent task and the round value taskne
Is output from the urgent task mask unit 77, the priority encoder 80 detects that the third bit from the lower order is inverted to “0” in the round value maskne. Since this third bit is a bit assigned to task (3) in FIG. 7B, the priority encoder 80 sets the task identifier t of task (3).
The askid is output to the selector 82.

The cstate storage unit 85 stores a flag cstate indicating whether the I / O processor is in a normal state or an emergency state. FIG. 33 is a state transition diagram of the flags stored in the cstate storage unit 85. In the figure, the transition from the normal state to the emergency state is performed when the emergency state transition permission signal iexecmode is set to H.
igh, and the task switching signal chg_task_ex becomes High. Conversely, the transition from the emergency state to the normal state is performed when the task switching signal chg_task_ex has a High value. FIG. 34 shows an emergency state transition permission signal iexe.
6 is a timing chart showing timing between cmode, a task switching signal chg_task_ex, and cstate.

It is assumed that the task switching signal chg_task_ex has a High value at a timing a30 when the iexecmode signal has risen to High as indicated by reference numeral a31. Then c
The state becomes High as indicated by reference numeral a32, and the state transits to the emergency state. The task switching signal chg_task_ex is indicated by reference numeral a33.
When the state becomes high again as shown in (3), the cstate becomes the low value as shown by reference numeral a34 and returns to the normal state. The transition from the emergency state to the normal state and the transition from the normal state to the emergency state are repeated.

When the input emergency state transition permission signal iexecmode is High and the cstate is High as indicated by the reference numeral a32, the selector 82 sets the reference value (the opposite of the cstate to the truth value cstate!). In the case of Low as indicated by a35), the task identifier taskide stored in the task management register 13 is selected and output to the task ID holding unit 72. Otherwise, priority encoder 8
The task identifier taskidne converted from the round value maskne, which is the output of 0, is selected and output to the task ID holding unit 72. FIG. 32 is a diagram showing a truth table of taskide in the selector 82.

The selector 82 switching and outputting the task identifier taskidne converted from the round value maskne and the urgent task identifier in accordance with the High period / Low period of the emergency state transition permission signal iexecmode is an emergency. This means that one of the tasks without the emergency task and the emergency task are switched and stored in the task ID holding unit 72 according to the High period / Low period of the state transition permission signal iexecmode.

For example, if task (1) is an urgent task, task (0), task (2), task (3), task (4), task (5) are used as task identifiers without the urgent task.
Thus, the selector 82 outputs the task identifier.
In the normal state, as shown in FIG.
2 outputs any task without the emergency task, so task (0), task (2), task (3), task (4),
The thread assigned to the task (1), such as the task (5), has 0 cycles.

In the emergency state, as shown in FIG. 35B, the selector 82 selectively outputs any of the tasks without the emergency task and the emergency task.
(0), task (1), task (2), task (1), task (3),
Task (1), Task (4), Task (1), Task (5), Task
As in (1), task (1) is assigned a thread once every two times. In the output of the task identifier in the emergency state by the selector 82, the task execution goes to the task (1) once every two times, which is １ ／ when converted into the probability.

Such a probability of 1/2 is an extremely high probability of three times the normal execution probability, and the urgent task is executed at a very high speed. As described above, according to the present embodiment, only the video out task can be preferentially executed in the horizontal blanking period and the vertical blanking period. If the moving image data is converted into a video signal during this period, the video signal can be suitably processed by the display period of the display.

In the configuration of the fourth embodiment, since the urgent task is executed with priority, the frequency of execution of tasks other than the urgent task is reduced. However, a prevention mechanism for preventing this is provided. Is also good. The prevention mechanism is
The identifier of the restricted task (called an exceptional task) that "the execution speed must be maintained at least this much" is stored in the task management register, and the exceptional task excludes the task switching condition of executing four instructions. A signal to the effect is output to the thread manager 61.

The comparator 54 in the thread manager 61
Receives the signal to that effect, delays the output of the task switching signal for a predetermined time. Here, the time length of the predetermined time is a time length that can recover the delay of each task due to the priority of the urgent task. As described above, by delaying the output of the task switching signal for a predetermined time, it is possible to execute the processing of the exceptional task by four or more instructions and to recover the processing delay accompanying the emergency task insertion.

In the present embodiment, the specific task is executed at high speed in synchronization with a specific signal input from the outside. However, a task to be executed at high speed by a specific instruction may be determined. The third bit of the status monitor register CR2 is normally set to “0”, and is set to “1” when the video signal in the externally connected display device is in the retrace period.
An immediate and an operand are specified in the operand, and a CMP instruction for judging the match / mismatch is placed in the video out task, and only when the execution result of the operation for this instruction is true, the video out task is executed at high speed. May be executed. A task requiring urgent handling may be specified by the operand of the instruction.

Further, although the task to be executed in the normal state is specified by the round value taskne without the emergency task, the emergency task may be executed in the normal state. (Fifth Embodiment) The fifth embodiment is an embodiment intended to improve the task traveling efficiency by cooperation between tasks.

[0146] Here, cooperation between tasks means that a task whose thread allocation is useless unless a specific time has arrived advances into a sleep state by itself and entrusts release of the sleep state to another task. The task entrusted with release means waiting for the time when the sleep state should be released, and if so, releasing the sleep state of the specific task.

Task sleep may occur frequently in a plurality of tasks at the same time, or may not occur at all.
The 5th task so that dormant tasks can be managed individually
In the embodiment, a bit for managing a task that has entered sleep (sleep state) is assigned to the task management register 13. FIG. 36 shows a task management unit 1 according to the fifth embodiment.
FIG. 37 is an explanatory diagram showing the bit configuration of the task management register 13 and what kind of flag these bits function as. In this drawing, if the 0th bit of the task management register 13 is “0”, it indicates that the task (0) is processed as a sleep state, and if the 0th bit is “1”, the task (0) is not. Indicates that

If the first bit of the task management register 13 is "0", it indicates that the task (1) is to be processed in the sleep state, and if the first bit is "1", the task (1) is not. Indicates that If the second bit of the task management register 13 is “0”, it indicates that the task (2) is to be processed as a sleep state, and if the second bit is “1”, the task (2) is processed.
Indicates that (2) is not. The task switches these bits so as to put itself into a sleep state or cancel the sleep state of another task.

The bit operation of the task management register 13 is as follows.
This is performed by an instruction indicating a mnemonic in the following {Example 3} Example 4. ｛Example 3｝ sleep_task ｛Example 4｝ wake_task task (k) In ｛Example 3｝, the “sleep_task instruction” sleeps itself.
This is the instruction to set the state. In "Example 4", "wake_task
The instruction ”can designate any one of the six tasks with the first operand. By arranging such two types of instructions in each task, each task alternately shifts to a sleep state and cancels it. Sleep_ta
In the sk instruction, another task may be specified by the first operand.

FIG. 38 is a diagram showing the internal configuration of the scheduler 62 in the fourth embodiment. 38, there is no difference from the first embodiment in that the scheduler 62 includes a task ID holding unit 71, a task ID holding unit 72, a task round management unit 73, and a priority encoder 74. What is new in this figure is a task skip management circuit 93 including an inverter 94 and an OR circuit 95.

The task skip management circuit 93 is assigned to the sleep state in the task management register 13.
It comprises an inverter 94 for inverting bits, and an OR circuit 95 for performing a logical sum of the inverted 6 bits and the round value taskn output from the task round management unit 73. Here, task (0), task (1), and task (2) have been executed
[00111] The round value taskn of “00111” is output from the task round management unit 73, and the task (3) is set to the sleep state in the task management register 13.
In this case, the sleep bit of the task management register 13 is "110
111 ”, and the inverted value“ 001 ”
000 "is output. The inverted value [001
000 "and the round value taskn" 000111 "are" 00
1111]. When this logical sum is output to the priority encoder 74, it is detected that the inversion from “1” to “0” is performed in the fourth bit, and the task
The identifier of (4) is output to the task ID holding unit 71 and the task ID holding unit 72. When the identifier of the task (4) is output, the task (0), the task (1), the task (2), and the task (4) are executed in this order.

FIG. 39 shows an example of an asynchronous event task having a sleep instruction as instructions 1-1, 2-1 and 3-1. FIG. 41 shows how the asynchronous event task of FIG. It is a timing chart which shows whether it is performed. sl
When the eep instruction is stored as the first instruction of the asynchronous event task as the instruction 1-1 as shown in FIG. 41, the instruction 1-1 is stored in the DECPC holding unit 23, and the instruction decoding control unit 11 Once decrypted, the selector 25
The read address of instructions 1-2 via task line P
It is stored in the C storage unit 24. After that, the instruction decoding control unit 11
Invalidates the instructions 1-2 and 1-3 ("NOP" in FIG. 16).

FIG. 40 shows an example of the command format of the sleep command and the wake command. In FIG. 40, this instruction has the instruction format of the register designation type arithmetic operation instruction shown in FIG. By designating 11 bits to 13 bits of this format as “010”, the I / O processor executes the operation of the sleep instruction. Also, by specifying 11 bits to 13 bits of this format to “011”, wak
The I / O processor performs the operation of the e-instruction.

The I / O of the fifth embodiment configured as described above
How the O processor allocates threads will be described with reference to FIGS. 42 (a) to 42 (d). Task (1) is a purging task, task (3) is a host I / O task, and the first instruction of task (1), task (2), and task (3) is a sleep instruction.
Task (0), task (4), and task (5) are assigned four-cycle threads.
Since (1), task (2), and task (3) store a sleep instruction as the first instruction, a two-cycle thread is allocated.

After the execution of the sleep instruction, in the next frame, as shown in FIG.
(2) The thread assigned to the task (3) has 0 cycles. Task (0) is a bit stream transfer control task with a longer activation period, and it is assumed that task (0) stores a wake instruction for task (3) first. Then, as shown in FIG. 42 (c), this wake instruction is decoded in the next frame, so that a thread of 4 cycles is allocated to the task (3).

It is assumed that the task (0) stores a wake instruction for the task (1) fourteenth. Then, as shown in FIG. 42 (d), by decoding this wake instruction in the next frame, a thread of 4 cycles is allocated to the task (1). As described above, according to the present embodiment, a task having a limited period to be started, such as a purging task or a host I / O task, goes into a sleep state by itself, and sleeps in a transfer control task having a longer startup period. By leaving the release of the state, the throughput of the task patrol can be improved. (Sixth Embodiment) The sixth embodiment relates to a technique in which the wait state control in the third embodiment, the emergency task control in the fourth embodiment, and the sleep task control in the fifth embodiment coexist.

FIG. 43 shows the management of the wait state, the emgcy state, and the sleep state in each bit of the task management register 13. The thread manager 61 and the scheduler 62 determine the next task and increase or decrease the number of instructions assigned to the next thread of the task with reference to the wait state, the emgcy state, and the sleep state integrated in the task management register 13 as described above. .

FIG. 44 is a configuration diagram of the scheduler 62 configured so that emergency task control and sleep state task control can coexist. In FIG. 44, the scheduler 62
Is a task ID storage unit 72, a task round management unit 75, a converter 76, an emergency task mask unit 77, a priority encoder 80, a selector 82, and a task ID storage unit 83.
Is not different from the fourth and fifth embodiments. In the figure, the output of the task round management unit 75 and the round value taskne inverted by the inverter 94 are shown.
An OR circuit 96 for calculating the logical sum with the round value of is newly added, and the result is output to the priority encoder 80.

The priority encoder 80 converts the round value output from the OR circuit 96 into a task identifier,
Output to the task ID holding unit 72 and the task ID holding unit 83. As described above, according to the present embodiment, the emergency task control in the fourth embodiment and the sleep task control in the fifth embodiment
By coexisting with state task control, more flexible task scheduling can be realized. (Description of Overall Control in Each Embodiment)
The overall control of the I / O processor shown in the first to fifth embodiments will be described with reference to flowcharts.

FIG. 45 is a flowchart showing the overall control of the I / O processor in the first embodiment. In the figure, “variable k” is a variable for indicating six asynchronous event tasks stored in the instruction memory 100, and is a task ID holding unit 71 and a task ID holding unit 72.
Corresponds to the task identifier taskid held by. "Variable i"
Is a variable for indicating the order in which the instruction is executed in the thread when executing the instruction included in each task, and corresponds to the count value counted by the counter 52. The “variable adr” is a variable indicating a read destination address of each task stored in the task-specific PC storage unit 24.

FIG. 50 is a diagram showing transition between threads according to the flowchart of FIG. In FIG. 50, the downward direction in the vertical direction is the time axis, and the square surrounded by a thick frame including four rectangles is a thread. It is individually designated by a variable k in the flowchart of FIG. Each square in the bold frame represents a cycle of executing one instruction, and these instructions are indicated by a variable i. In step S1, the task ID holding unit 71 sets the task identifier to zero.
Output taskid. As a result, the variable k is cleared to zero, and the routine goes to Step S2. A step S2 initializes the variable i to 1 by initializing the counter 52. In step S3, the task ID holding unit 72 reads the task-specific PC storage unit 24 with the read address selection signal nxttaskid.
By outputting (rd_adr), the read destination address of the task (k) is read from the task-specific PC storage unit 24. Step S
In step 4, the instruction is fetched from the instruction memory 100 using the read destination address of the task (k). In step S5, the instruction decoding control unit 11 decodes and executes the extracted instruction.

In step S6, the comparator 54 compares the variable i with the upper limit 4. In this case, since i = 1, the process proceeds to step S7. Step S7 stores the variable in the counter 52
This is a step in which i is incremented and the increment circuit 21 can increment the read destination address. This increment means switching from execution of one instruction in task k to execution of another instruction. In this case, since i = 2, the execution of the instruction in the thread is switched to the execution of the second instruction.

The variable i is incremented in step S7, and the process proceeds to step S4. Since i = 2 from the increment of the variable i and the read destination address has advanced by one instruction, the instruction reading circuit 10 reads the instruction indicated by the read destination address (adr + 1) in the instruction memory 100 in step S4. In step S5, the command decoding control section 11 decodes the command and executes it.

By repeatedly performing the above-described series of steps S4 to S7, the variable i is incremented one after another, and adr + 0, adr + 1,
The instructions stored in the areas of adr + 2 and adr + 3 are sequentially read. The above steps S4 and S5 are repeated until the result of step S6 becomes Yes. Step S6
Is YES, the process proceeds from step S6 to step S8. In the above procedure, steps S4, S5, S6, and S7 are repeated as long as the variable i is 1, 2, and 3. Only when the variable i becomes 4, the steps from S6 to S8 are performed. The transition means that the execution of the instruction for task (0) is repeated four times (the arrangement of the four squares at the top in FIG. 50 indicates the four times in the first thread of task (0)). Illustration of instruction execution.) By the way, from step S8
Since the procedure of step S10 is to switch from task to task, the “variable i
= 4 "means that four repetitions of instruction execution are imposed on the condition of task switching.

If it is determined in step S6 that the variable i is equal to the upper limit value, the variable i is incremented by the increment circuit 21 in step S8,
In step 9, the task (k) read destination address (adr + i-1) is stored in the task-specific PC storage unit 24 as the read destination address (adr), and then the process proceeds to step S10. In step S10, the task round management unit 73 and the priority encoder 74 determine a task to be executed next. At this time, the round value taskn of “000000” is output by the task round management unit 73 and the priority encoder 74
As a result, a task identifier taskid of “001” is output.
Since the task identifier taskid of “001”, that is, k = 1, switching from task (0) to task (1) is performed. After the task is switched, when the process proceeds to step S2, the variable i is initialized, and the repetition of steps S3 to S7 is started again.

As in the previous case, in step S4, one instruction included in task (1) is fetched from the read destination address in the instruction memory 100, and the fetched instruction is decoded and executed in step S5. Step S6 is a variable
The comparison between i and upper limit 4 is performed again. In this case, since i = 1, the process proceeds to step S7. The variable i is incremented in step S7, and the process proceeds to step S4.
Since i = 2 from the increment of the variable i, step S
In step 4, the area in the instruction memory 100 designated by the read destination address (adr + 1) is accessed.
At 0, the instruction stored in the area designated by the read destination address (adr + 1) is read, and it is decoded and executed at step S5.

By repeatedly performing the above-described series of steps S4 to S7, the variable i is incremented one after another, and adr + 0, adr + 1,
The instructions stored in the areas of adr + 2 and adr + 3 are sequentially read. The above steps S4 and S5 are repeated until the result of step S6 becomes Yes. Step S6
Is YES, the process proceeds from step S6 to step S8. In the above procedure, steps S4, S5, S6, and S7 are repeated as long as the variable i is 1, 2, and 3. Only when the variable i becomes 4, the steps from S6 to S8 are performed. The transition is performed (by the operation described above, in FIG. 50, four instructions in task (1) (four instructions for task (1)) have been advanced.) In step S8, the variable i is incremented. In step S9, the read destination address (adr + i-1) of the task (k) is stored as the read destination address (adr), and then the process proceeds to step S10. In step S10, the task round management unit 73 and the priority encoder 74 determine the variable k again, and set the variable k to k = 2.
Then, the task (1) is switched to the task (2). After the task is switched, the process proceeds to step S2.
Initialization of the variable i is performed and steps S3 to S
The repetition of 7 is started again.

By repeating the above, in FIG.
Task (1), Task (2), Task (3), Task (4), Task
The execution of (5) is performed four instructions at a time, and each task is sequentially consumed. (Description of Overall Control in Second Embodiment) Overall control of the I / O processor in the second embodiment is performed according to the procedure shown in the flowchart of FIG. The flowchart of FIG. 46 is composed of steps S1 to S10 in FIG.
Is created based on the flowchart of FIG. Here, what is new in FIG. 46 is that step S12 is inserted between steps S4 and S5.

In step S12, the instruction read from the instruction memory 100 in step S4 is Wait_Until_Nex
Determine whether the instruction is a t instruction. If it is a Wait_Until_Next instruction, the process proceeds to step S8 to increment the variable i, and in step S9, the read address (adr + i-1) of the task (k) is stored as the read address (adr).

It should be noted here that, in step S12, regardless of the value of the variable i, the flow shifts to step S8 when the Wait_Until_Next instruction is executed, and stores the read destination address. As described above, since step S8 is executed after decoding in step S12 regardless of the value of the variable i, switching from task to task is performed without waiting for four instructions.

FIG. 51 is a diagram showing transition between threads according to the second embodiment. In the sequence in FIG. 51, the vertical direction is the time axis as in FIG. 50, and the square surrounded by a thick frame including four rectangles is a thread. Each square in the bold frame represents a cycle for executing one instruction. Among these rectangles, those with “” indicate a Wait_Until_Next instruction. Also, which instruction in the instruction memory 100 the task (0) executes in each thread is indicated by “PC” “PC + 1” on the right side of the square.
It is expressed by a program count value such as "PC + 2" or "PC + 3" and a relative value from the program count. (Note that this figure shows the program count when reading the first instruction of the first thread of task (0). Based on the value.)

In FIG. 47, steps S1 to S
By performing the procedure of No. 4, the first instruction of the first thread of the task (0) is read. The decoding result of the read instruction is determined in step S12. However, since the first thread-first instruction of the task (0) is not the Wait_Until_Next instruction, the process proceeds to step S5. Step S5
As a result, the execution of the first thread and the first instruction of the task (0) is performed, and one task is advanced.

By performing steps S1 to S4 again, the second thread of the first thread of task (0) is
The instruction is read. The decoding result of the read instruction is determined in step S12. The first thread-second instruction of the task (0) is a Wait_Until_Next instruction, and the process proceeds to step S8. In step S8, the variable i is incremented by 1 to "3". In step S9, the read destination address (adr + 2) is stored in the task-specific PC storage unit 110 as the read destination address of the task (0).

After the storage, the variable k is incremented in step S10, and the flow shifts to step S2. By incrementing the variable k in step S10,
Switching from task (0) to task (1) is performed without waiting for execution of the third and fourth instructions of the first thread. Execution of the first thread of task (1) is performed by executing four instructions, and similarly, task (2), task (3), task (4), task
Execution of (5) is performed, and the first thread to the fourth thread of the task (5) are executed.
Suppose you have advanced to the order. In step S10, the variable k
Is determined, the variable i is initialized to “1” in step S2, and the read destination address of the task (0) is read from the task-specific PC storage unit 110 in step S3. Note that the second thread of the first thread of task (0)
When the instruction (Wait_Until_Next instruction) is executed, PC + 2 (“P
"C" indicates the program count value of the first instruction. ) Is stored in the task-specific PC storage unit 110 as the read destination address of the task (0). In this way, the PC storage unit for each task
Since (PC + 2) is stored in 110, the instruction execution of the second thread of the task (1) is started from PC + 2.

(Description of Overall Control in Third Embodiment)
FIG. 47 is a flow chart of the I / O processor according to the third embodiment.
It is a chart. 45, steps having the same processing contents in FIGS. 45 and 46 are denoted by the same reference numerals as in FIGS. 45 and 46, and description thereof is omitted. In the figure, "Variable Tota
“l” indicates a numerical value output by the selector 55 based on the contents of the task management register 13 and is used to specify the upper limit of the number of executed instructions. In the initial state, the variable Total is initialized to “4”, which is the total number of instructions in the thread, but can be updated to “2”.

FIG. 52 is a diagram showing transition between threads according to the flowchart of the third embodiment. In the following description, in FIG. 52, the first instruction and the second instruction of the first thread of the task (0) have been executed, and the third instruction is about to be read from this. Step S93 is for the above variable
Clear k to zero and set the variable Total to 4. A step S2 clears the variable i to zero. In step S3, the read destination address of the variable k that has been cleared to zero, that is, the read destination address of task (0) is stored in the task-specific PC storage unit 110.
Read from In step S4, the instruction memory 100
The instruction is taken out from the address where the read destination address of the task read in step 2 is an absolute address and the variable i is an offset value.

It is determined whether the instruction fetched in step S81 is a Cmp_And_Wait instruction. Step S8
In 2, the instruction decoding control unit 81 and the operation execution unit 84 perform Cmp_And_
With reference to the designation of the state monitoring register j described in the first operand of the Wait instruction and the immediate value described in the second operand, it is determined whether the event presented by the Cmp_And_Wait instruction is true or false. If the value held in the state monitoring register j and the immediate value do not match, and it is determined that the event is not satisfied, the flow shifts to step S83, sets the task k to the wait state, and shifts to step S84. In step S84, the flip-flop 27 and the selector 25 are caused to set the read destination address to the address of the Cmp_And_Wait instruction so that the program count does not advance, and the flow proceeds to step S87.

Step S87 is a flow chart of FIG.
In this step, as in step S6 of FIG. The determination of “variable i = 4” in step S6 is as follows:
Four repetitions of instruction execution were imposed on the conditions for task switching. On the other hand, the determination of “variable i = variable Total” in step S87 imposes on the task switching condition that the number of repetitions of instruction execution is equal to the variable Total. Since the variable Total here has not been updated,
“Variable i = Variable Total” is actually a determination of “Variable i = 4”. The Cmp_And_Wait instruction is included in the third instruction in the first thread of the task (0). On the other hand, since the variable i = 2, the process proceeds from step S87 to step S7. When the variable i is incremented in step S7, Cmp_And_Wait is read by reading the instruction in step S4.
The instruction next to the instruction is read out by the instruction decoding control unit 81. When the instruction is read, step S81 is No, and in step S85, the instruction decoding control unit 11 determines that the state is not established in the immediately preceding instruction, and the read destination address is Cmp_And_Wait.
Was set to instruction address (whether PC return occurred)
Is determined.

Here, the instruction immediately before the instruction stored at the address (adr + i) corresponds to the Cmp_And_Wait instruction.
When the Cmp_And_Wait instruction was decoded, a PC return occurred.
Therefore, step S85 becomes Yes and the process moves to step S86. In step S86, the instruction decoding control unit 11 discards the instruction at the read address (adr + i).
The notification that the stored value of the general-purpose register is invalidated is performed, and the instruction stored at the address (adr + i) as shown in task (0) -fourth instruction of the first thread in the task sequence of FIG. Is invalidated, and the routine goes to Step S87. Since the value of the variable i is 4, if the determination of “variable i = variable Total” is made in step S87, the result becomes Yes,
The process moves to step S88.

When the determination in step S87 is Yes, it means that the instruction execution for one thread has been completed. In step S88, it is determined whether or not the PC return has occurred in the minus thread. To make such a decision
This is because when a PC return occurs, it is necessary to store the return destination in the task-specific PC storage unit 110. Task (0)
In the case of (4), the fourth instruction is discarded, and a PC return occurs in the third instruction. In step S89, the flip-flop 27 and the selector 25 store the return destination PC value as the read destination address (adr), and then, in step S10 Move to In step S10, the task round management unit 73
After the next task is determined by the priority encoder 74, the variable k is incremented, and the process proceeds to step S90.

Steps S90 to S92 determine whether the task designated by the incremented variable k, that is, the task to be executed next is in a wait state, and determine the number of instructions in the next thread. It has an important implication of switching. In step S90, the ID converter 53 refers to the bit corresponding to the task (k) in the task management register 13 and determines whether the task (k) is in a wait state. If so, the selector 55 sets 4 to the variable Total in step S91, and if different, 2 to the variable Total.
Set.

Since the task (1) is not in the wait state, the variable Total is set to 4 in step S91, and the flow shifts to step S2. Here, task (1) has Cmp_And_Wait
Assuming that no instruction is included, the execution of the instruction in step S5 is repeated four times to switch to the next task (the above procedure is the same as that described in the first embodiment). We will not repeat the explanation.)

A task that does not include the Cmp_And_Wait instruction
As for (2), task (3), and task (4), the execution of the four instructions is sequentially performed, and the tasks are sequentially switched. task
It is assumed that the execution of the four instructions of (5) is completed, and the process proceeds to step S10. Step S90
Then, it is determined whether the bit k assigned to the task k in the task management register 13 is “1” or “0”. This determination means determining whether the task k is in the wait state. Here, the variable k = 0, and the task (0)
Has been set to the wait state earlier, so step S91
Set the variable Total to "2". It should be noted here that the variable Total has the meaning of the number of instructions allocated to the thread. Updating this from “4” to “2” in step S91 means reducing the number of instructions mapped to a thread from “4” to “2”. Therefore, in the second thread of the task (0), only while the variable i is incremented to 1,2,
That is, steps S81 to S85, step S5
Is repeated only twice. At this time, the task
The read destination address of the Cmp_And_Wait instruction is stored in the task-specific PC storage unit 110 as the read destination address of (0). When the Cmp_And_Wait instruction is read from the address of the read destination address, the success or failure of the event is determined in step S82 as in the first thread. In this case, assuming that the event ends in failure, the same processing as in the first thread is performed, the read destination address is returned to the Cmp_And_Wait instruction, and the second thread is terminated.

Task that does not include Cmp_And_Wait instruction
As for (1), task (2), task (3), and task (4), the four instructions are executed sequentially, and the tasks are sequentially switched. Tasks that have been executed
The third thread at (0) is about to start. Here, a change occurs in an event in the I / O processor, and Cmp_A of task (0) is changed.
Assume that the event specified in the nd_Wait instruction has been established. Therefore, in the third thread of the task (0), the instruction decoding control unit 81 determines in step S82 that the event has been established, and the process proceeds to step S80 where the wait state of the task k in the task management register 13 is released. When the wait state is released in this way, step S8
0, the process proceeds to step S87, and step S8 is performed.
In step 7, the variable i is compared with the variable Total. In step S7, the variable i is incremented. In step S4, the instruction is read from the read destination address (adr + 1). It is determined whether the instruction read in step S81 is a Cmp_And_Wait instruction.
Since the instruction is not the p_And_Wait instruction, the flow shifts to step S85. In step S85, it is determined whether the state has not been established in the immediately preceding instruction and a return to the PC has occurred. Cmp_An
Since the event specified by the d_Wait instruction has been established, step S85 is No, and the next order instruction of the Cmp_And_Wait instruction is executed in step S5 only after waiting for the establishment of the event twice. After execution of the next instruction in step S5,
The process proceeds from step S5 to step S87, and the magnitude comparison between the variable i and the variable Total is performed. However, since the variable Total is set to 2 in the second thread, the task
The third thread of (0) ends only after being executed twice. After shifting to step S87, in step S88, it is determined whether the return of the PC is true or false.
No, in step S89, the read destination address (adr + i-1) of the task (k) is stored as the read destination address (adr), and the flow advances to step S10. Tasks in this way
When the third thread of (0) is finished, tasks (1), (2), (3), and (4) that do not include the Cmp_And_Wait instruction
Also, the execution of the four instructions is performed sequentially, and the tasks are sequentially switched. Assume that the execution of the four instructions for the task (5) is completed, the variable k is cleared to zero, and the process proceeds to step S90.

In step S 90, by referring to the bit corresponding to task (k) in task management register 13,
It is determined whether the task (k) is in a wait state. In this case, since the wait state of task (0) has been released, step S92
In step 4, the variable Total is set to 4, and the process proceeds to step S2. Since the variable Total returned to 4 in this way, the task
Threads after (0) are executed by four instructions as usual.

(Explanation of Overall Control in Fourth Embodiment)
FIG. 48 is a flowchart showing the overall control of the I / O processor in the fourth embodiment. The procedure of steps S1 to S9 in the flowchart of FIG.
6 is the same as the flowchart. What is new in FIG. 48 is the step S3 to which reference numerals in the thirties are assigned.
0, step S31, and step S32. A step S30 decides whether or not the emergency state transition permission signal has a low value. If the emergency state transition permission signal has a high value, the process shifts to the step S31 to determine the emergency task as a task to be executed next in the step S31.

On the other hand, if the emergency state transition permission signal is low, the flow goes to step S32 to cause the priority encoder 80 to determine the next task to be executed from the normal tasks based on the round value taskne. FIG. 53 is a diagram showing transition between threads in the fourth embodiment.
In this drawing, at the beginning of the normal state, the processing of step S31 is skipped, and the first thread of task (0), the first thread of task (2), the first thread of task (3), and the task of FIG. The first thread of (4) and the first thread of task (5) are sequentially performed.

Assuming that a high period of the emergency state transition permission signal occurs when the execution of taskne has completed one cycle, after one task is executed in steps S2 to S9, the branch from step S30 to step S31 is executed. Will be After the branch, the cstate shown in the cstate storage unit 85
The emergency task is executed according to the High value and Low value. (Overall Control in Fifth Embodiment) FIG. 49 is a flowchart of a multitask procedure in the fifth embodiment.
This figure shows the flow of the multitask procedure in the first embodiment.
The difference from the chart is that steps S41 to S44, S46, S4 are performed between steps S4 and S6.
7 is inserted.

A step S41 decides whether or not the command read from the command memory 100 is a sleep command. If it is a sleep command, the process proceeds to step S42.
In step S42, the task management register 13 stores the task
Invert the bit corresponding to (k) to 0. Then, in step S43, the variable i is incremented by one, and in step S44, the read destination address (adr + i-1) of the task (k) is stored as the read destination address (adr).
Go to 5. After the shift, in step S45, the inverter 94 and the OR circuit 95 generate a round value without bits in which the sleep state is designated in the task management register 13, and outputs the round value to the priority encoder 74, and the task to be executed next (k) is determined. Here, it should be noted that, as described above, the “variable k” is a variable for indicating each of the six tasks stored in the instruction memory 100, and the determination thereof is made by the task to the task. Means switching.

The difference between step S45 and step S10 is that step S10 is executed when the variable i becomes 4, whereas step S45 is executed when the sleep instruction is decoded regardless of the value of the variable i. It is the point that is executed at the time when it is done. As described above, since step S45 is executed after decoding the sleep instruction irrespective of the value of the variable i, switching from task to task is performed without waiting for four instructions.

In step S46, the read destination address (adr
It is determined whether the instruction read from (+1) is a wake instruction for any bit in the task management register. If not, the instruction read in step S5 is decoded and executed. If so, step S47 is executed.
Then, the sleep state of the task j is released by operating the j bit specified in the wake instruction, and the process proceeds to step S6.

FIG. 54 is a diagram showing transition between threads in the fifth embodiment. In the drawing, the mark in the first thread of the task (1) indicates that the second instruction of the first thread of the task (1) is a sleep_task instruction. During execution of the sleep_task instruction, similarly to the execution of the Cmp_And_Wait instruction in the second embodiment, in decoding the second instruction, steps S41 to S44 are executed, and task switching is performed after task (1) is set to the sleep state. , The third instruction and the fourth instruction will be effectively discarded.

The switching between tasks as described in the first embodiment is sequentially performed, and tasks (2), (3), and
It is assumed that the task is circulated as in (4) and task (5), and the process proceeds to step S45. In step S45, the priority encoder 74 determines a task to be executed next based on the round value taskn in which bits of the task in the sleep state are masked. Here, the bit assigned to the task (1) in the task management register 13 is set to the sleep state in the task (1) -the second instruction of the first thread. Therefore, the execution of task (1) is skipped, and the second thread of task (2) is subsequently executed.

It is assumed that the switching between the similar tasks is sequentially performed, the tasks are circulated in the order of task (2), task (3), task (4), and task (5), and the process proceeds to step S45. I do. In this tour, the third instruction of the second thread of task (5) has specified the release of the sleep state of task (1).
The wake_task instruction is assumed to have been read from the instruction memory 100. When the wake_task instruction is read from the instruction memory 100, the determination in step S46 is Yes.
And the process moves to step S47. In step S47, the sleep state of the task (1) is released by turning off the bit assigned to the task (1) in the task management register 13. After the release, the remaining instructions are similarly executed, and the processing for the second thread is completed.

After the task (5) ends, it is assumed that the task has been switched to the task (0). It is also assumed that the third thread of the task (0) is executed, and the process proceeds to step S45. In step S45, it is determined whether the bit assigned to the task (1) in the task management register 13 is off. In the second thread of the task (5), since the assignment bit of the task (1) is set to ON as described above, the process proceeds from step S45 to steps S2 and S3, and the task is executed. Execution of (1) is resumed.

[0196]

As described above, according to the present invention, n
For the task identifier, the number of tasks assigned to the task
An execution module that outputs the next task identifier when an instruction is executed.
Specified by the task instructing means and the output task identifier
Instruction specifying means for sequentially specifying instructions to be executed in a task
And execution means for executing a specified instruction,
The execution task instructing means is a normal task in n tasks.
The number of instructions less than the number of instructions assigned to the task
The identifier of the penalty task to be assigned
The penalty task holding unit to be held and the next task identifier
Is output, the penalty task holding unit is referred to.
The task identified by the task identifier
Judge whether the task is a task or not.
1 instruction number is the first instruction number for a penalty task
Less second instructions are assigned to the task
The present processor does not wait for the issuance of an interrupt signal, but executes n tasks including the audio-out task and the video-out task by a predetermined number of instructions. Execute sequentially.

Since execution is sequentially performed in this manner, the optimum lower limit of the number of operation clocks for completing the processing of the audio out task and the video out task is determined by the minimum digest number of instructions that must be executed in a predetermined cycle. , And the total number of tasks, the optimum lower limit of the number of operation cycles for operating all tasks can be uniquely calculated from the optimum lower limit.

Since the optimum lower limit value of the number of operation clocks is unambiguously calculated, the real-time property of the audio out task and the video out task can be guaranteed without setting the operation clock signal to a higher level, and the operation clock is low The MPEG stream can be suitably decoded even when it is installed in consumer devices with many different types .

[0199]

[0200]

[0201]

[0202]

[0203]

[0204]

[0205]

[0206]

[0207]

[0208]

[0209]

[0210]

[0211]

[Brief description of the drawings]

FIG. 1 is a diagram showing an internal configuration of an AV decoder.

FIG. 2 is a timing chart showing a hierarchical structure of an MPEG stream and operation timings between components of an AV decoder.

FIG. 3 is a diagram illustrating an internal configuration of an I / O processor according to the first embodiment.

FIG. 4 is a diagram showing an internal configuration of an instruction reading circuit 10 according to the first embodiment.

FIG. 5 is a diagram showing an output logic table of a selector 25 in the instruction reading circuit 10;

FIG. 6 is a diagram illustrating an internal configuration of a task management unit 15 according to the first embodiment.

FIG. 7A is a diagram illustrating a bit configuration of a task identifier taskid. FIG. 4B is a diagram illustrating a bit configuration of a round value.

FIG. 8 is a diagram showing how the asynchronous event task stored in the instruction memory 100 is configured in the first embodiment.

FIG. 9 shows an instruction format of an arithmetic operation instruction in which a register is specified as an operand.

FIG. 10 shows an instruction format of a memory load instruction / memory store instruction in which a read destination address and a write destination address are specified by a register.

FIG. 11 shows an instruction format of a comparison instruction / operation instruction / branch instruction capable of specifying an 8-bit or 11-bit immediate value.

FIG. 12 is a diagram showing a configuration of the first embodiment, where IPC, IF1, IF2, and DECPC are used.
7 is a timing chart showing how is updated.

FIG. 13 is a diagram showing how threads are allocated from task (0) to task (5).

FIG. 14 is a diagram showing what kind of instruction the asynchronous event task stored in the instruction memory 100 is configured in the second embodiment.

FIG. 15 shows an example of an instruction format of a wait_until_next instruction.

FIG. 16 shows a second embodiment in which IPC, IF1, IF2, DECPC
7 is a timing chart showing how is updated.

FIG. 17 shows tasks from task (0) to task in the second embodiment.
FIG. 14 is a diagram showing how threads are allocated by (5).

FIG. 18 is a diagram illustrating an internal configuration of an AV decoder according to a third embodiment.

FIG. 19 is a diagram showing an internal configuration of an instruction reading circuit 10 according to a third embodiment.

FIG. 20 is a diagram illustrating an output logic table of a selector 25 in the instruction reading circuit 10 according to the third embodiment.

FIG. 21 is a diagram illustrating an internal configuration of a thread manager 61 according to the third embodiment.

FIG. 22 is a diagram showing a bit configuration of 6 bits allocated for wait state management in the task management register 13;

FIG. 23 is a diagram illustrating a bit configuration of a state monitoring register according to the third embodiment.

FIG. 24 (a) shows which task is Cm in the third embodiment.
FIG. 11 is a diagram showing whether a p_and_Wait instruction is included. (B) In the state where the events j0, j3, j4, j5 are not satisfied,
FIG. 25 is a diagram showing how threads are allocated to the respective tasks shown in FIG. (C) In the frame where only event j0 is established, FIG.
It is a figure which shows how a thread is allocated to each task shown to (a). (D) After the frame in which event j0 is established, FIG.
It is a figure which shows how a thread is allocated to each task shown to (a).

FIG. 25 shows an example of an instruction format of a Cmp_and_Wait instruction.

FIG. 26: IPC, IF1, IF when decoding the Cmp_and_Wait instruction
2, How DECPC is updated, Task Management Register 1
6 is a timing chart showing how the upper limit value of the bit 3 and the counter is set.

FIG. 27 shows how IPC, IF1, IF2, and DECPC are updated in a frame when an event waiting for the Cmp_and_Wait instruction is not established, and how the upper limit value of the bit of the task management register 13 and the counter are set. FIG.

FIG. 28 illustrates how the IPC, IF1, IF2, and DECPC are updated and how the bits of the task management register 13 and the upper limit of the counter are set in a frame at the time of establishment of an event for which the Cmp_and_Wait instruction has been waiting. It is a timing chart shown.

FIG. 29: In the frame after the event is established, the IPC,
6 is a timing chart showing how IF1, IF2, and DECPC are updated, and how the upper bits of the bits and the counter of the task management register 13 are set.

FIG. 30 is a diagram illustrating an internal configuration of a task management unit 15 according to the third embodiment.

FIG. 31 is a diagram illustrating an internal configuration of a scheduler 62 according to the third embodiment.

FIG. 32 is a diagram showing conditions under which the selector outputs an identifier of an emergency task.

33 is a state transition diagram of a mode stored in a cstate storage unit 85. FIG.

FIG. 34 shows an emergency state transition permission signal and a task switching signal chg_.
9 is a timing chart showing the timing of which task identifier is output according to transition of task_ex and cstate.

FIG. 35 (a) is a diagram showing how threads are allocated to each task in a normal state. (B) is a diagram showing how threads are assigned to each task in an emergency state.

FIG. 36 is a diagram illustrating an internal configuration of a task management unit 15 according to the fourth embodiment.

FIG. 37 is a diagram showing assignment of bits assigned to a sleep state in the task management register 13;

FIG. 38 is a diagram illustrating an internal configuration of a scheduler 62 according to the fourth embodiment.

FIG. 39 shows a sleep command and a wake command in the fourth embodiment.
FIG. 4 is a diagram showing how instructions are arranged in each task.

FIG. 40 shows an example of a command format of a sleep command and a wake command.

FIG. 41 is a timing chart showing how IPC, IF1, IF2, and DECPC are updated in the fourth embodiment.

FIGS. 42A to 42D are diagrams illustrating how threads are assigned to respective tasks in the fourth embodiment.

FIG. 43 is a diagram illustrating an internal configuration of a task management unit 15 according to the fifth embodiment.

FIG. 44 is a diagram illustrating an internal configuration of a scheduler 62 according to the fifth embodiment.

FIG. 45 is a flowchart showing overall control of the I / O processor in the first embodiment.

FIG. 46 is a flowchart showing overall control of the I / O processor in the second embodiment.

FIG. 47 is a flowchart showing overall control of the I / O processor in the third embodiment.

FIG. 48 is a flowchart showing overall control of the I / O processor in the fourth embodiment.

FIG. 49 is a flowchart showing overall control of the I / O processor in the fifth embodiment.

FIG. 50 is a diagram showing how thread allocation progresses in the first embodiment.

FIG. 51 is a diagram showing how thread assignment progresses in the second embodiment.

FIG. 52 is a diagram showing how thread assignment progresses in the third embodiment.

FIG. 53 is a diagram showing how thread assignment progresses in the fourth embodiment.

FIG. 54 is a diagram showing how thread assignment progresses in the fifth embodiment.

FIG. 55 is a timing chart showing how a moving image stream and an audio stream are processed when a video out task and an audio out task are executed by thread allocation in the first embodiment.

FIG. 56 is a configuration diagram of a thread manager when the number of cycles is variable for each task.

FIG. 57 is a timing chart showing by what time processing of a moving image stream and an audio stream must be completed when executing an audio-out task and a video-out task with an interrupt signal.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Instruction readout circuit 11 Instruction decoding control part 12 Register set 13 Task management register 14 Operation execution part 15 Task management part 20 IF1 + 1 holding part 21 increment circuit 22 IF2 holding part 23 DECPC holding part 24 PC storage part for each task 25 4 inputs -1 output selector 26 2-input-1 output selector 52 counter 53 converter 54 comparator 55 selector 61 slot manager 62 scheduler 71 task ID holding unit 72 task ID holding unit 73 task round management unit 74 priority encoder 75 task round management unit 76 converter 77 Emergency task mask unit 80 Priority encoder 81 Instruction decoding control unit 82 Selector 83 Task ID holding unit 84 Operation execution unit 85 CSTATE storage unit 93 Task skip management circuit 94 Inverter 100 Instruction memory 101 Stream input unit 102 Buffer memory 104 Setup unit 105 VLD unit 106 IQ / IDCT unit 107 Motion compensation unit 108 Video output unit 109 Audio output unit 110 BM buffer memory controller 111 RAM controller 112 FIFO controller 113 Processor 115 Host I / O unit 121 Buffer Memory bus 122 SD-RAM bus 123 Bit stream bus 124 Control bus

──────────────────────────────────────────────────の Continued on the front page (72) Inventor Makoto Hirai 1006 Kadoma Kadoma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. In-house (56) References JP-A-1-99132 (JP, A) JP-A-6-202887 (JP, A) JP-A-8-249194 (JP, A) JP-A-6-187170 (JP, A) JP-A-1-154237 (JP, A) JP-A-7-110773 (JP, A) Shigeki Fujii, 4 others, Embedded OS for media processing, IPSJ Research Report, Japan, Information Processing Society of Japan, February 26, 1998, Vol. 98, No. 15, (98-OS-77), p. 61-66 Yukio Kikuta and 1 other, Digital Satellite Broadcasting Perfectec! Receiver CSRR-P1, Toshiba Review, Japan, Toshiba Corporation, February 1, 1997, Vol. 52, No. 2, p. 63-66 (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 9/46-9/54 G06F 9/30-9/355 G06F 9/40-9/42 H04N 7/12 H04N 7 / 24-7/68

Claims (4)

(57) [Claims] 1. An execution task which outputs n task identifiers when the number of instructions assigned to the task is executed for n task identifiers, wherein the processor outputs n task identifiers. Instruction means; instruction designation means for sequentially designating instructions to be executed in the task specified by the output task identifier; and execution means for executing the designated instructions. In the number of tasks, a penalty task holding unit that holds an identifier of a penalty task that is a task to which the number of instructions less than the number of instructions assigned to a normal task is assigned; and when the next task identifier is output, the penalty task holding unit To determine whether the task identified by the task identifier is a penalty task, And a second instruction number which is smaller than the first instruction number in the case of a penalty task. . 2. A processor having n tasks as execution target tasks, wherein, for n task identifiers, an execution task that outputs a next task identifier when the number of instructions assigned to the task is executed. Instruction means; instruction designating means for sequentially designating an instruction to be executed in the task specified by the output task identifier; and execution means for executing the designated instruction. A counter for counting the number of instructions executed, a comparator for comparing the count value of the counter with the number of instructions assigned to the task being executed, outputting a task switching signal when the values match, and resetting the counter; and a task switching signal. A task identifier output unit for generating and outputting a task identifier of the next order each time a is issued, a first instruction number, and a second instruction number less than the first instruction number An instruction number holding unit that holds the number of instructions, a penalty task holding unit that holds an identifier of a penalty task that is a task to which the second instruction number is to be assigned in n tasks, and a task identifier output unit that outputs a task identifier. A determining unit that determines whether the task identifier is an identifier of a penalty task; and, if it is determined that the task identifier indicates a penalty task, indicates a second instruction number held by the instruction number holding unit to indicate the penalty task. And determining that the first number of instructions is the number of instructions assigned to the task, and outputting the first number of instructions to the comparator. 3. Any of the tasks includes an event monitoring instruction including designation of a true / false condition of establishment of an event, wherein the execution unit includes a decoding unit that decodes the instruction designated by the instruction designation unit. If the result of the decoding by the decoding means is an event monitoring instruction, the arithmetic means for executing an operation to confirm whether the event specified in the event monitoring instruction is true or false is provided. 3. The processor according to claim 1, wherein if the calculation result indicates that the event is not established, the task identifier of the task including the event monitoring instruction is held as a penalty task identifier. 4. The processor according to claim 1, wherein the processor is provided in an information processing system having a buffer and a memory therein, wherein the processor has a plurality of state registers indicating states in the internal buffer and the memory, Has a designation for any one of a plurality of status registers and an immediate designation, and when the result of decoding by the decoding means is an event monitoring instruction, the arithmetic means 4. The processor according to claim 3, wherein an operation is performed using the held value and an immediate value specified in the instruction.