JPH11126868A - Production of base board for multichip module - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a production method for a base board for MCM in which a semiconductor bare chip, or the like is embedded. SOLUTION: A base board is produced by a two stage machining method which combines etching and pressing. A resist mask 12 is formed on a board 11 and subjected to chemical etching o form protruding connection posts 13. The board provided with the connection posts is then inserted between dies 14, 14' and pressed by gradually applying a load 16 to form a recessed marker 17 tapered at 45 deg.C.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-chip module having a bare semiconductor chip and a conductive post mounted on a substrate, and more particularly to a multi-chip module for embedding a bare semiconductor chip or the like in a base substrate. It relates to a manufacturing method.

[0002]

2. Description of the Related Art As one means for reducing the size and improving the performance of electronic devices, there is a so-called multi-chip module in which a plurality of bare semiconductor chips and passive elements are interconnected to form a single module.

An example of a conventional method for mounting a bare semiconductor chip is disclosed in Japanese Patent Application Laid-Open No. 3-155144, in which an insulating film having a predetermined thickness larger than the thickness of the bare semiconductor IC chip is previously provided with a hole larger than the outer dimension of the semiconductor bare IC chip by a predetermined amount. Is formed, the insulating film is bonded to the support plate with an adhesive, the bare semiconductor IC chip is bonded to the hole of the bonded insulating film with the adhesive, the gap between the bare semiconductor chip and the insulating film and After applying the surface of the bare semiconductor IC chip with the same kind of liquid resin as the insulating film so as to have a uniform height with the insulating film layer, heat-curing, and removing the resin on the bare semiconductor IC chip pad by a photolithographic method. Then, a conductor film is formed on the entire surface, and a predetermined conductor wiring is formed by a photolithography method.

An example of a conventional semiconductor device (especially a multi-chip module) and a method of manufacturing the same are disclosed in Japanese Patent Laid-Open No. 5-4.
As shown at 7856, a chip is mounted on at least one stage provided in the package, an insulating film is applied to the package and the chip, and conduction is established between connection pads on the package and pads on the chip. Via holes are provided in the insulating film, and the via holes are connected by a wiring pattern.

[0005]

SUMMARY OF THE INVENTION Japanese Patent Laid-Open No. 3-15514
4 and JP-A-5-47856, the supporting plate or the package is made of an insulating substrate. Generally, the material of the insulating substrate has a heat conductivity lower by one digit or more than the conductive material and the semiconductor material. It is not suitable for mounting a large power amplifier or the like.

Further, in the embodiment of Japanese Patent Application Laid-Open No. 5-47856, a mounting conductor layer (for example, Au-Si
There is no electrical connection between the eutectic or conductive adhesive) and the conductor wiring on the insulating film, and the circuit operation in a high frequency region lacks stability.

Further, in an example of a conventional method for mounting a bare semiconductor chip disclosed in Japanese Patent Application Laid-Open No. 3-155144, the gap between the bare semiconductor IC chip and the insulating film and the surface of the bare semiconductor IC chip are made of a liquid resin of the same kind as the insulating film. In the step of thermosetting after coating so that the height is uniform with the insulating film layer, dents are likely to occur in the gap between the bare semiconductor IC chip and the insulating film due to contraction of the liquid resin during thermosetting. When a dent occurs in the gap,
A defect such as a short circuit or disconnection occurs in the conductor wiring in the gap.

Further, in an example of a semiconductor device and a method of manufacturing the same as disclosed in Japanese Patent Application Laid-Open No. 5-47856, an insulating film in a gap between a package and a chip due to shrinkage of the liquid resin during the heat curing in the liquid resin thermosetting step. The wiring pattern in the gap is liable to cause a defect such as a short circuit or disconnection, and there are many problems in reliability.

As one means for solving this problem, there is a chip-embedded matching chip module. This method
A plurality of irregularities are provided in advance on the metal base substrate, and then covered with a resin-like insulating film so as to embed the bare semiconductor chip, and the insulating film and the bump electrode on the bare semiconductor chip have a predetermined height. Then, a flattening process is performed by grinding or the like, and a multi-layer wiring is provided thereon by a metal layer and an insulating film together with a thin-film passive component. However, a problem with this method is that desired irregularities cannot be easily formed on the base substrate.

For example, in the etching process, a process for producing a plurality of uneven portions is complicated and lacks reproducibility. On the other hand, in press working, there are many problems in working to collectively produce a plurality of uneven portions having different heights.

[0011]

According to the present invention, in order to solve the above-mentioned problems, a base substrate is manufactured by a two-step processing method using both etching and pressing. First, by a first-stage etching process, a convex conductive post, which is a part of the base substrate, and an enclosure wall separating the module are formed.

Next, after positioning between the through-hole marker provided on the base substrate and the die marker in advance, the second
By the pressing process using the convex mold at the stage, a marker for positioning the bare semiconductor chip mounting portion is produced. At this time, the alignment marker portion is concave, and its side surface is provided with a taper of 15 to 60 degrees. In particular, if there is a taper, the chip slides down into the marker when the chip is mounted, and positioning by self-alignment becomes easy.

That is, the feature of the two-step processing method of the present invention is that
In the first etching process, the surface of the metal base substrate is greatly dug down, and a concave portion for burying a plurality of bare semiconductor chips and a convex portion of the connection post are simultaneously produced. Further, in the second-stage press working, a metal surface roughened by etching is flattened, and a multi-stage concave portion having a taper by a convex mold is easily produced.

After the base substrate is formed, a bare chip component composed of a semiconductor element or an IC chip having a metal bump is bonded to the chip mounting marker. Next, the bare chip component is covered with a resin-like first insulating film so as to be embedded, and the insulating film and the bump on the bare chip are planarized by grinding or polishing so as to have a predetermined height. Then, a multilayer wiring pattern is formed thereon by a metal layer and an insulating film together with the thin-film passive components, and a thin and small multi-chip module is completed.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 Hereinafter, the present invention will be described in detail with reference to embodiments.

FIG. 1 shows a basic manufacturing process of a base substrate of the present invention. First, as a first step, in FIG. 1A, a resist mask 12 for etching is formed on a base substrate 11 made of Cu by photolithography. Next, in FIG. 1 (b), the metal base substrate 11 was etched to a depth of 180 μm with a chemical etching solution comprising ferric chloride.
The convex connection post 13 is manufactured by m-etching. Next, in FIG. 1 (c), the process enters the second stage of press working. A connection post 13 is provided between the molds 14 and 14 '.
After that, the metal base substrate 11 on which is manufactured is inserted, and thereafter, the weight 16 is gradually applied, and the press is started (the circle indicates the tapered mold convex portion 15). Then, FIG.
In (d), the final weight is applied to complete the press.

Next, in FIG. 1E, a concave marker 17 having a depth of 20 μm and a taper angle of 45 degrees is formed at a position where the bare semiconductor chip is mounted and bonded on the base substrate 11 taken out of the mold. Fabrication of the base substrate by two-stage processing is completed.

As described above, the feature of the two-stage processing is that the base substrate surface is largely dug down in the first-stage etching process to provide a concave and convex portion for burying the bare semiconductor chip, and the second-stage press process is tapered. The present invention is to provide a concave marker by flattening a metal surface roughened by etching with a convex mold provided with a low load.

Embodiment 2 FIG. 2 shows a manufacturing process of a single module base substrate according to the present invention.

Cu was used as the metal base substrate.
The module size formed on the substrate is 10 mm square. First, as a first step, in FIG. 2A, a connection post having a width of 200 μm and a connection post having a width of 600 μm are formed on a base substrate 21.
A resist mask 22 for etching is formed by a photolithography method to form a grid-shaped enclosure wall separating the m modules. Next, in FIG. 2B, the metal base substrate 21 is etched by a depth of about 180 μm with a ferric chloride-based chemical etching solution to form an enclosure wall 24 separating the connection post 23 and the module.

Next, in FIG. 2 (c), the second stage press working is started. After positioning is performed with the pilot marker formed on the base substrate 21 and the marker of the mold 25 in advance, the metal base substrate 2 between the molds 25 and 25 ′ is formed.
Pressing is started by gradually applying a load 26 to 1 (the circled portion indicates a mold convex portion 27 having a taper). At this time, it is necessary to make the die relatively large for the connection post 23 and the surrounding wall 24 and to design it so that the shape of the connection post 23 and the like does not deform during pressing. FIG.
In (d), 28 is the base substrate 21 after the press working.
3 is a concave marker for mounting a bare semiconductor chip formed on the etched surface of FIG. Through this two-stage processing step, the connection post 23 and the double-girder-shaped enclosure wall 2 separating the module
4 is formed in the base substrate by etching, and the concave marker 28 for mounting the bare semiconductor chip is formed in the base substrate by pressing.

Embodiment 3 FIG. 3 is a layout view of an enclosure wall provided between a pilot marker and a module provided on a base substrate according to the present invention in a grid pattern.

FIG. 3A shows a base substrate having a diameter of 75 mm.
It is a top view when using Cu of mmφ, thickness 700 μm, module size 10 mm square. Pilot marker 3
As 1, through-holes having a diameter of 3 mm are provided at four locations around the substrate, and alignment with a die marker is performed before pressing. Further, a grid-shaped enclosure wall 32 is provided between the modules, which is used as a warp prevention in an insulating film backfilling step after the mounting of the bare chip and as a shielding side wall when cut out as a unit module.
FIG. 3B shows a cross-sectional view. The marker 34 of the chip mounting portion formed by press working has a taper of 45 degrees on the side surface.

Embodiment 4 FIG. 4 shows a process for manufacturing a multi-chip module using the present invention.

First, in FIG. 4A, a connection post 4 previously formed by two-stage processing of etching and pressing.
2. A plurality of semiconductors in which metallic (for example, Au or Al) bumps 46 are placed on the electrodes on a base substrate 41 provided with an enclosure wall 43, an electrode 44, and a chip mounting marker 45 separating the modules. A bare chip component 47 composed of an element or an IC chip was bonded and mounted with Au-Sn eutectic solder. Next, in FIG. 2B, embedding using an epoxy resin 48 as a first insulating film of the unevenness on the base substrate 41 and the bare chip component 47 was performed.
Next, in FIG. 2C, the surface of the thermally cured epoxy resin 48 was flattened by grinding or polishing to expose the connection posts 42, the surrounding wall 43, and the metal bumps 46 on the bare chip components 47. Next, in FIG. 2D, a second insulating film 49, a third insulating film 50, and a metal layer formed of a metal layer on the planarized insulating film 48 for forming a thin-film passive component and multilayer wiring. 1 wiring pattern 51, first
A capacitor 52 formed on the wiring pattern, a second wiring pattern 53 formed of a metal layer thereon, and a conductive through-hole 54 penetrating the second and third insulating films were sequentially laminated and formed. Thereafter, the back surface of the multi-chip module was ground or etched until the insulating film 48 was exposed at both ends of the electrode 44. Furthermore, the module was cut in the middle of the surrounding wall 43 to make a unit multi-chip module.

The conductive post 44 is held by an embedded resin 48 filled in the groove, and is separated and independent from the base substrate. Therefore, since the electrodes can be directly taken out from the back surface of the base, the multichip module can be directly soldered to the motherboard, and the mounting area is reduced as compared with the case where the leads are electrically connected.

Embodiment 5 FIG. 5 shows a method of manufacturing a base substrate according to another embodiment of the present invention. In the present embodiment, when pressing the base on which the conductive posts and the surrounding wall are formed by etching, a set of dies having concave portions provided in the lower die corresponding to the convex portions of the upper die is used. .

As shown in FIG. 5A, the substrate 60 having the conductive posts 61 and the enclosing wall 65 formed by etching is aligned with the upper mold 70a and the lower mold 70b. A resin embedding groove 62 around the conductive post 61 and a concave marker 63 for chip mounting are formed by processing.

In the case of the present embodiment, since the concave portion is formed in the lower die 70b corresponding to the convex portion of the upper die 70a, the base pushed out by the convex portion of the upper die 70a is the lower die 70b. It can escape to the recess of the mold 70b. Therefore, compared to the case of using a flat lower mold, deformation such as warpage is less likely to occur on the base after press working.

In addition, on the substrate after the press working, a convex portion is formed on the back surface of the substrate as shown in FIG. 5B, but is removed in a grinding step of the back surface of the substrate performed to expose the conductive posts.

[0031]

According to the two-step processing of the present invention using both etching and pressing, it is possible to form a concave and convex portion having a predetermined depth on a predetermined portion of the base substrate with good reproducibility. In addition, the etching and the collective press forming technology can simplify the process and shorten the process time.

Further, the enclosure wall formed at the time of etching suppresses the warpage of the base substrate at the time of backfilling the insulating film, so that the process can be stabilized.

Further, the metal surface roughened by the etching by the press working is flattened, and the margin of the bonding condition at the time of mounting the bare chip can be expanded. That is, no bubbles are generated at the interface between the chip and the substrate and good adhesiveness is realized. Further, since the adhesiveness is improved, the heat dissipation of the chip is also improved.

Further, a leadless structure in which electrodes are taken out from the back surface of the module can be realized.

[Brief description of the drawings]

FIG. 1 is a basic manufacturing process diagram of a base substrate of the present invention.

FIG. 2 is a manufacturing process diagram of a base substrate of the present invention.

FIG. 3 is a layout diagram of a pilot marker and an enclosure wall on the board of the present invention.

FIG. 4 is a manufacturing process diagram of a multichip module using the present invention.

FIG. 5 is a manufacturing process diagram of a base substrate of the present invention.

[Explanation of symbols]

11, 21, 41, 60 ... base substrate, 12, 22 ... resist mask, 13, 23, 33, 34, 42, 61 ...
Conductive post, 14, 14 ', 25, 25' ... mold, 1
5, 27 ... convex part, 17, 28, 34, 45, 63 ... chip mounting position marker, 24, 32, 43, 65 ... surrounding wall, 46 ... bump, 47 ... bare semiconductor chip, 48 ...
First insulating film, 49: second insulating film, 50: third insulating film, 4
4 ... electrode, 51 ... first wiring pattern, 53 ... second wiring pattern, 52 ... capacitor, 54 ... through hole, 62
... embedding groove, 70a ... upper mold, 70b ... lower mold.

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Osamu Kagaya 1-280 Higashi Koigakubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. Inside the Central Research Laboratory

Claims (4)

[Claims] 1. A method of manufacturing a base substrate of a multi-chip module (MCM) comprising a plurality of bare chip components mounted on one side of a conductive base substrate made of metal or the like. A first step of etching a predetermined portion to a predetermined depth by etching, and further, pressing a predetermined portion of the recess formed in the first step by press working using a mold of metal or the like to a predetermined depth. A method of manufacturing a base substrate for an MCM, comprising: forming a multi-level uneven portion on the base substrate. 2. A method of manufacturing a base substrate for an MCM according to claim 1, wherein at least before said second step, a pilot marker comprising at least two through holes for positioning said mold is formed. A method for manufacturing a base substrate for MCM, comprising: 3. The method for manufacturing an MCM base substrate according to claim 1, wherein the first step forms a convex enclosure wall in which a plurality of modules are separated by a grid. Method for manufacturing base substrate. 4. The method of manufacturing a base substrate for an MCM according to claim 1, wherein the concave portion formed in the second step is a mounting position of the bare chip component, and a side surface of the concave portion is 15 to 60 degrees. A method for manufacturing an MCM base substrate, characterized by having a taper angle.