JPH11126866A - Semiconductor device with part-mounting pad - Google Patents
Semiconductor device with part-mounting padInfo
- Publication number
- JPH11126866A JPH11126866A JP28994797A JP28994797A JPH11126866A JP H11126866 A JPH11126866 A JP H11126866A JP 28994797 A JP28994797 A JP 28994797A JP 28994797 A JP28994797 A JP 28994797A JP H11126866 A JPH11126866 A JP H11126866A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- pad
- package
- pads
- bare chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は部品実装パット付半
導体装置、特に、パッケージの上面を外付け部品のため
に利用できる部品実装パット付半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device with a component mounting pad, and more particularly to a semiconductor device with a component mounting pad that can use the upper surface of a package for external components.
【0002】[0002]
【従来の技術】従来の部品実装パット付半導体装置につ
いて図面を参照して詳細に説明する。2. Description of the Related Art A conventional semiconductor device with a component mounting pad will be described in detail with reference to the drawings.
【0003】図2は従来の一例を示す上面図である。図
2に示す半導体装置は、パッケージ101の中央にベア
チップ2がマウントされ四辺にリード6a,6b,12
等を有する。ノイズ対策用のコンデンサ(以下パスコン
という)7や波形整形用のダンピング抵抗13は、パッ
ケージ101の外部である印刷配線板の上にパット10
2a,102b,103aを設け、其処に実装されてい
た。FIG. 2 is a top view showing an example of the prior art. In the semiconductor device shown in FIG. 2, a bare chip 2 is mounted at the center of a package 101, and leads 6a, 6b, 12
Etc. A capacitor 7 for noise suppression (hereinafter referred to as a bypass capacitor) and a damping resistor 13 for waveform shaping are provided on a printed wiring board outside the package 101 by a pad 10.
2a, 102b and 103a are provided and mounted there.
【0004】[0004]
【発明が解決しようとする課題】上述した従来の半導体
装置は、集積回路装置の外部に外付部品を取り付けるの
で、印刷配線板の実装面積が大きくなり、ベアチップと
外付部品との距離が長くなるため外付部品の目的とする
実装効果が減少されるという欠点があった。In the above-mentioned conventional semiconductor device, since external parts are attached to the outside of the integrated circuit device, the mounting area of the printed wiring board becomes large, and the distance between the bare chip and the external parts becomes long. Therefore, there is a disadvantage that the intended mounting effect of the external component is reduced.
【0005】[0005]
【課題を解決するための手段】第1の発明の部品実装パ
ット付半導体装置は、半導体装置の上面に外付部品実装
用の複数のパットを備える。According to a first aspect of the present invention, a semiconductor device with a component mounting pad includes a plurality of pads for mounting external components on an upper surface of the semiconductor device.
【0006】第2の発明の部品実装パット付半導体装置
は、ベアチップがマウントされたパッケージの上面に設
けられた複数のパットと、ベアチップとパットとを接続
するリードと、パッケージの出力ピンとパットとを接続
するリードとを含んで構成される。According to a second aspect of the present invention, there is provided a semiconductor device with a component mounting pad, comprising a plurality of pads provided on an upper surface of a package on which a bare chip is mounted, leads for connecting the bare chip and the pad, output pins and the pad of the package. And a lead to be connected.
【0007】[0007]
【発明の実施の形態】次に、本発明について図面を参照
して詳細に説明する。Next, the present invention will be described in detail with reference to the drawings.
【0008】図1は本発明の一実施形態を示す上面図で
ある。図1に示す部品実装パット付半導体装置は、ベア
チップ2がマウントされたパッケージ1の上面に設けら
れた複数のパット4a,4b,9a,9bと、ベアチッ
プ2とパット4a,4bとを接続するリード3と、パッ
ケージ1の出力ピン6a,6bとパット4a,4bとを
接続するリード5と、ベアチップ2とパット9aとを接
続するリード8と、パット9bとパッケージ1の出力ピ
ン12とを接続するリード11とを含んで構成される。FIG. 1 is a top view showing an embodiment of the present invention. The semiconductor device with a component mounting pad shown in FIG. 1 has a plurality of pads 4a, 4b, 9a, 9b provided on the upper surface of a package 1 on which a bare chip 2 is mounted, and leads for connecting the bare chip 2 and the pads 4a, 4b. 3, a lead 5 connecting the output pins 6a, 6b of the package 1 to the pads 4a, 4b, a lead 8 connecting the bare chip 2 and the pad 9a, and connecting the pad 9b to the output pin 12 of the package 1. It is configured to include the lead 11.
【0009】パット4a,4bにはパスコンデンサ7が
実装され、パット9a,9bにはダンピング抵抗13が
実装される。A pass capacitor 7 is mounted on the pads 4a and 4b, and a damping resistor 13 is mounted on the pads 9a and 9b.
【0010】[0010]
【発明の効果】本発明の部品実装パット付半導体装置
は、部品実装用のパットを集積回路装置のパッケージの
上部に設けたので、印刷配線板側に部品実装用のパット
を配置する必要かないため、印刷配線基板の小型化を図
ることができ、ベアチップに接近して外付部品を配置で
きるので、実装部品に期待される作用が増大できるとい
う効果がある。According to the semiconductor device with the component mounting pad of the present invention, since the component mounting pad is provided on the upper part of the package of the integrated circuit device, it is not necessary to dispose the component mounting pad on the printed wiring board side. In addition, the size of the printed wiring board can be reduced, and the external component can be arranged close to the bare chip, so that the effect expected for the mounted component can be increased.
【図1】本発明の一実施形態を示す上面図である。FIG. 1 is a top view showing an embodiment of the present invention.
【図2】従来の一例を示す上面図である。FIG. 2 is a top view showing an example of the related art.
1 パッケージ 2 ベアチップ 3 リード 4a パット 4b パット 5 リード 6a 出力ピン 6b 出力ピン 7 パスコンデンサ 8 リード 9a パット 9b パット 11 リード 12 出力ピン 13 ダンピング抵抗 101 パッケージ 102a パット 102b パット 103a パット 103b パット Reference Signs List 1 package 2 bare chip 3 lead 4a pad 4b pad 5 lead 6a output pin 6b output pin 7 pass capacitor 8 lead 9a pad 9b pad 11 lead 12 output pin 13 damping resistor 101 package 102a pad 102b pad 103a pad 103b pad
Claims (2)
数のパットを備えることを特徴とする部品実装パット付
半導体装置。1. A semiconductor device with a component mounting pad, comprising a plurality of pads for mounting external components on an upper surface of the semiconductor device.
の上面に設けられた複数のパットと、ベアチップとパッ
トとを接続するリードと、パッケージの出力ピンとパッ
トとを接続するリードとを含むことを特徴とする部品実
装パット付半導体装置。2. A semiconductor device comprising: a plurality of pads provided on an upper surface of a package on which a bare chip is mounted; leads for connecting the bare chips to the pads; and leads for connecting output pins of the package to the pads. Semiconductor device with component mounting pad.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP28994797A JPH11126866A (en) | 1997-10-22 | 1997-10-22 | Semiconductor device with part-mounting pad |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP28994797A JPH11126866A (en) | 1997-10-22 | 1997-10-22 | Semiconductor device with part-mounting pad |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH11126866A true JPH11126866A (en) | 1999-05-11 |
Family
ID=17749805
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP28994797A Pending JPH11126866A (en) | 1997-10-22 | 1997-10-22 | Semiconductor device with part-mounting pad |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH11126866A (en) |
-
1997
- 1997-10-22 JP JP28994797A patent/JPH11126866A/en active Pending
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP2001102512A (en) | Capacitor mounting structure and method therefor | |
JPH11126866A (en) | Semiconductor device with part-mounting pad | |
JP2002299568A (en) | Ic chip | |
JP3942495B2 (en) | Semiconductor device | |
JPS59130453A (en) | Package of semiconductor integrated circuit | |
JP2788899B2 (en) | Integrated circuits for surface mounting | |
JP2783075B2 (en) | Integrated circuit package assembly | |
KR19980056452U (en) | Heat dissipation device for high micro integrated circuit | |
KR200161172Y1 (en) | Semiconductor chip | |
JPH0645494A (en) | Package for semiconductor integrated circuit | |
KR0117716Y1 (en) | Semiconductor package | |
JPH06349981A (en) | Resin-sealed semiconductor device | |
JPH0433283A (en) | Socket | |
JPH05114694A (en) | Integrated circuit | |
JPH03101188A (en) | Method of mounting electronic circuit component | |
JPH0242755A (en) | Package of semiconductor integrated circuit | |
JPH04277693A (en) | Mounting method for semiconductor device | |
JPH02180062A (en) | Package for semiconductor integrated circuit | |
JPH05226561A (en) | Semiconductor device | |
JP2002365331A (en) | Device evaluation holder | |
JP2002329560A (en) | Conversion spacer for surface mounting,and method for surface mounting of through-hole mounted type electronic component on electronic board using this | |
JPH01316948A (en) | Semiconductor integrated circuit | |
JPH10270648A (en) | Semiconductor package | |
JPH01296654A (en) | Semiconductor device | |
JPH04346286A (en) | Semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19991012 |