JPH11126181A - Information transfer device with arithmetic function - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an information transfer device with arithmetic function capable of performing plural kinds of arithmetic processings in the case of transferring data between devices. SOLUTION: The information transfer device 2 is interposed between an input/output unit 4 and a main storage device 8. A transfer program 10 in the main storage device 8 contains a compound function command instructing for plural kinds of arithmetic processing. The information transfer device 2 has an arithmetic processing part 12 for performing the arithmetic processing based on the analyzed compound function command for every arithmetic processing and outputting each arithmetic processing result, memory 26 for respectively storing the respective arithmetic processing results at respective prescribed positions, memory control part 30 for transferring each arithmetic processing result between the arithmetic processing part 12 and the memory 26 and successively performing every arithmetic processing and storage, and transfer part 16 for transferring the said arithmetic processing result to the main storage device 8 when the arithmetic processing results of all the arithmetic processing based on the compound function command are stored in the memory 26.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information transfer device connected to a data transfer bus in an electronic computer system or the like, and more particularly to an information transfer device with an arithmetic function for performing arithmetic processing during data transfer.

[0002]

2. Description of the Related Art In recent information processing systems, there is a demand for efficiently performing a large amount of data (information). Generally, when it is desired to perform arithmetic processing on predetermined data in a storage device storing a large amount of data, the arithmetic processing has been performed as follows. That is, the predetermined data stored in the storage device is transferred to the main storage device. On the other hand, each operation instruction instructing each operation process is transferred from the main storage device to the CPU. And the CPU:
After decoding each operation instruction, data necessary for the decoded operation instruction is taken out from the main storage device. And the CPU:
Each calculation process is performed, and the calculation result is transferred to the main storage device. However, the above-described method has a problem in that the load on the CPU for data calculation processing increases.
As a result, other processes to be performed by the CPU have been delayed.

Therefore, there is an information transfer device with an arithmetic function described in Japanese Patent Application Laid-Open No. 64-32367. This device is interposed between the storage device and the main storage device, and when transferring data between these storage devices and the main storage device,
Performs the arithmetic processing that was performed by the CPU. Thereby, the CP
The load on the arithmetic processing of U is reduced.

FIG. 4 is a block diagram showing a data transfer system including the above-mentioned conventional information transfer device with an arithmetic function. In the above system, the device A84 is connected to one side of the information transfer device with arithmetic function 82 via the input / output bus 80a. The other side of the transfer device with arithmetic function 82 is connected to the device B86 via the system bus 80b.
Is connected to

[0005] Data is stored in the device A84. The device A84 is a device for sending data at the time of data transfer. The device B86 is a device that receives the transferred data. A transfer program 94 consisting of a series of commands is stored in the device B86. As this series of commands, a function command for instructing a predetermined calculation process and the device A84
And a transfer command instructing the device B86 to transfer data. The device B86 transfers the data and the device A84
By receiving the transferred data, it is possible to change the direction in which the data is transferred.

[0006] The information transfer device 82 with an arithmetic function is a device A
It intervenes between the device 84 and the device B86, performs predetermined arithmetic processing on the data transferred from the device A84, and then transfers the data to the device B86. This information transfer device with arithmetic function 8
2 has an arithmetic processing unit 88, an analysis unit 90, and a transfer unit 92. The analysis unit 90 analyzes each command of the transfer program 94. The arithmetic processing unit 88 performs arithmetic processing based on the function command analyzed by the analysis unit 90. Transfer unit 92
Represents the result of the arithmetic processing by the arithmetic processing unit 88 in the device B8.
Transfer to 6. At this time, the transfer unit 92 transfers based on the transfer command analyzed by the analysis unit 90.

The transfer command is a command for transferring data from the device A84 to the device B86, as described above. Normally, the data transferred from the device A84 is directly transferred to the device B86. However, from device A84 to device B
When the information transfer device 82 performs arithmetic processing on the data while transferring the data to the data 86, a transfer command is stored in the transfer program 94 following the function command, and the following operation is performed. That is, the function command is analyzed by the analysis unit 90. Then, the arithmetic processing unit 88 is set so as to perform arithmetic processing indicated by the analyzed function command.
Thereafter, the transfer command is analyzed by the analysis unit 90. According to the analyzed transfer command, data is transferred from the device A. This data is once transferred to the arithmetic processing unit 88 and subjected to predetermined arithmetic processing. Then, the data on which the predetermined arithmetic processing has been performed is sent to the device B86 by the transfer unit 92 as needed.

The operation of transferring data from the device A 84 to the device B 86 using the information transfer device with arithmetic function 82 configured as described above will be described.

First, a data transfer command is issued from a CPU (not shown) or the like, and the command is transferred to the information transfer device 8 having an arithmetic function.
2 receives. Then, this device 82 becomes the device B 86
Is read from the transfer program 94 stored in. The analysis unit 90 analyzes each command of the read transfer program 94. When the analyzed command is a function command, the arithmetic processing unit 88 is set so as to perform a calculation process specified by the function command. Then, the arithmetic processing unit 88 waits until the data to be subjected to the arithmetic processing is transferred.

Next, when the command analyzed by the analysis unit 90 is a transfer command, the analysis unit 90 instructs the transfer unit 92 to transfer predetermined data from the device A84. In addition, the analysis unit 90 instructs the transfer unit 92 to transfer the calculation processing result to the device B86 as needed.

Subsequently, the arithmetic processing unit 88 performs an arithmetic process on the data transferred from the device A84 to the arithmetic processing unit 88. Then, the transfer unit 92 includes an arithmetic processing unit 88
The result of the arithmetic processing by the device B is arbitrarily determined based on the transfer command.
Transfer to 86.

In this way, the information transfer device with arithmetic function 82 transmits the data transferred from the device A84 to the data transferred from the device A84.
Since the arithmetic processing is performed, there is no need for the CPU or the like to perform the arithmetic processing on the device B86 or the data transferred from the device B86, and the load of the arithmetic processing of the CPU or the like can be reduced. Further, the information transfer device with arithmetic function 82 stores not the data from the device A84 but the result of the arithmetic processing such as search in the device B, so that the data transfer from the information transfer device with arithmetic function 82 to the device B86 Can be reduced.

[0013]

However, the above-mentioned prior art has the following problems. The conventional information transfer device with arithmetic function 82 was able to perform simple arithmetic processing such as retrieval on data transferred from the device A84. However, the information transfer device with arithmetic function 82 has only a register or the like for storing a small amount of data as a means for storing the result of the arithmetic processing, and a storage means such as a memory for organizing and storing a large amount of data. Did not. For this reason, only the result of performing one simple operation on the transferred data could be stored in the information transfer device with operation function 82. As a result, in the prior art, it was not possible to perform a plurality of types of arithmetic processing on the transferred data.

For example, a conventional information transfer device with an arithmetic function performs a search process matching predetermined conditions on data transferred from the device A, and then obtains a search process result obtained by the search process. On the other hand, the secondary arithmetic processing of adding the predetermined data could not be performed.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide an information transfer with an arithmetic function capable of performing a plurality of types of arithmetic processing when transferring data between apparatuses. It is to provide a device.

[0016]

In order to achieve the above object, an information transfer apparatus with an arithmetic function according to a first aspect of the present invention analyzes a program including an arithmetic instruction for instructing arithmetic processing, and analyzes the program. The data transferred from the device A is subjected to a calculation process based on the calculation command
In the information transfer device with an arithmetic function for transferring to the computer, the program includes a multi-function instruction instructing a plurality of types of arithmetic processing, and based on the analyzed multi-function instruction, performs each arithmetic processing for each arithmetic processing. A processing means for outputting each calculation processing result to each other, a storage means for storing each calculation processing result at each predetermined position, and a storage means for storing each calculation processing result between the calculation processing means and the storage means. A control means for transferring and sequentially performing each arithmetic processing and storage; and when the arithmetic processing result obtained by performing all arithmetic processing of the composite function command is stored in the storage means, the arithmetic processing result is stored in the device B. Transfer means for transferring the data from the apparatus A to the data transferred from the apparatus A based on the composite function command, and transferring the result of the calculation processing to the apparatus B. is there.

According to a second aspect of the present invention, there is provided an information transfer device with an arithmetic function, wherein the multifunction instruction according to the first aspect is a multifunction start instruction for instructing the start of a plurality of types of arithmetic processing, And a multifunction termination instruction for instructing termination.
The control unit according to claim 1, after transferring the data transferred from the device A to the storage unit, causes the calculation processing unit to perform each calculation process based on the analyzed composite function start command. In the case where a predetermined amount of the data is stored in the storage unit based on the analyzed composite function end command, the transfer of the data transferred from the device A to the storage unit is terminated, 2. The transfer according to claim 1, wherein when all of the arithmetic processing instructed by the multifunction instruction have been performed on the data, the arithmetic processing means ends the arithmetic processing based on the multifunction start instruction, and the transfer according to claim 1. The means transfers, based on the analyzed multifunction termination command, a calculation processing result obtained by performing all the calculation processes specified by the multifunction start command to the device B. That.

According to a third aspect of the present invention, in the information transfer device with an arithmetic function, the multifunction start command according to the second aspect includes a flag for determining whether data transferred from the storage means matches a predetermined condition. The control means according to claim 2 has:
After storing the data transferred from the device A in the storage means, the data is transferred to the arithmetic processing means. If the data does not match a predetermined condition indicated by the flag, the data is transferred from the arithmetic processing means to the storage means. Along with transferring an arithmetic processing result, causing the storage means to transfer subsequent data from the data to the arithmetic processing means, wherein the data is
When the predetermined condition is met, the transfer of data following the data from the storage means to the arithmetic processing means is stopped.

According to a fourth aspect of the present invention, there is provided an information transfer apparatus with an arithmetic function, wherein the multifunction start command according to the second aspect further comprises a flag for determining whether data transferred from the storage means matches a predetermined condition. And a count indicating the amount of data to be sent to the storage means without performing any arithmetic processing on the data transferred from the storage means. The control means according to claim 2, wherein After the stored data is stored in the storage unit, the data is transferred to the arithmetic processing unit.If the data matches the predetermined condition indicated by the flag, the data is transferred to the arithmetic processing unit subsequently. And transferring the amount of data indicated by the count to the storage unit without performing the arithmetic processing.

According to a fifth aspect of the present invention, there is provided an information transfer apparatus with an arithmetic function, wherein the multifunction start command according to the third or fourth aspect is such that the data transferred from the storage means is applied only to a predetermined portion of the data. 5. An arithmetic processing unit according to claim 3, further comprising an operand instruction for performing an arithmetic process, wherein the arithmetic processing unit according to claim 3 or 4 adds the complex function to a predetermined portion of the data transferred from the storage unit based on the operand instruction. It is characterized by performing arithmetic processing specified by the start command.

According to a sixth aspect of the present invention, an information transfer device with an arithmetic function analyzes a program including an operation instruction for instructing an arithmetic process, and, based on the analyzed operation instruction, n (n is an integer) devices An In the information transfer device with an arithmetic function for performing an arithmetic process on the data transferred from the device and transferring the data to the device B, the program includes a composite function command for instructing a plurality of types of arithmetic processes, The compound function command includes a device identification address for identifying each device An, and performs each calculation process for each calculation process based on the analyzed compound function command, and outputs each calculation process result. (N is an integer) arithmetic processing means Cn, n (n is an integer) storage means Dn for storing each arithmetic processing result at each predetermined position, and the arithmetic processing means Cn And said memory N (n is an integer) control means En for transferring the data to and from the stage Dn to sequentially perform the respective arithmetic processing and storage; When stored in the means Dn,
Transfer means for transferring the result of the arithmetic processing to the device B, wherein the arithmetic processing means Cn, the storage means Dn, and the control means En are determined based on the analyzed composite function command, and The device An is determined, and each operation is performed on the data transferred from the device An based on the multifunction command, and the result of the operation is output to the device B.
It is characterized by being transferred to

[0022]

Preferred embodiments of the present invention will be described below with reference to the drawings.

Embodiment 1 (1) Configuration of Information Transfer Apparatus with Arithmetic Function FIG. 1 shows a data transfer system including an information transfer apparatus with an arithmetic function according to the first embodiment (hereinafter, referred to as information transfer apparatus 2). FIG. One side of the information transfer device 2 is connected to the input / output device 4 via the input / output bus 3a, and the other side is connected to the C /
It is connected to the PU 6 and the main storage device 8.

The CPU 6 issues a data transfer command to the information transfer device 2.

The input / output device 4 stores data to be transferred.

The main storage device 8 stores a transfer program 10 including a composite function command and a transfer command. This composite function command is a command for instructing a plurality of types of arithmetic processing, and the transfer command is a command for instructing data transfer from the input / output device 4 to the main storage device 8. The main storage device 8 stores the results of the respective arithmetic processings transferred from the information transfer device 2.

FIGS. 3A-1 and 3A-2 show the types of the transfer command 51 and the composite function command 52 included in the transfer program 10. FIG. The transfer command 51 has a command code part, a data address part, a flag part, and a byte count part. The command code section instructs to read data from the input / output device 4, and the command code section describes, for example, a command called READ. The data address part indicates the head address of the data to be transferred among the data stored in the input / output device 4. The flag section instructs that data transfer be continued until a predetermined condition is met. The byte count unit indicates the amount of data transferred from the input / output device 4.

The composite function command 52 is a command having a command code part, a result storage address part, and a comparison operand address part, and instructing a plurality of types of arithmetic processing. The command code section indicates a plurality of types of arithmetic processing instructions. The command code section includes, for example, SEAR when searching for the transferred data and finding the maximum value among them.
A command called CH MAX is described. The result storage address portion indicates an address in the main storage device 8 when the operation processing result output after performing all the operation processes specified by the command code portion is stored in the main storage device 8. is there. The comparison operand address portion indicates an address at which comparison data to be searched is stored when a search process is performed on the transferred data.

Then, in the transfer program 10,
A transfer command 51 and a multifunction command 52 are included, and the multifunction command 52 is arranged before the transfer command 51.

The information transfer device 2 analyzes the transfer command 51 in the transfer program 10 and, based on the analyzed transfer command 51, transmits the data designated by the transfer command 51 to the input / output device 4.
To the main storage device 8. At this time, if the composite function command 52 is analyzed before the transfer command 51, the information transfer device 2 performs, based on the analyzed composite function command 52, data for the data transferred from the input / output device 4. After performing a plurality of types of arithmetic processing, the data is transferred to the main storage device 8.

The information transfer device 2 has an arithmetic processing unit 12, an analysis unit 14, a storage unit 18, and a transfer unit 16. Analysis unit 1
4 are each command of the transfer program 10 (transfer command 5
1, multifunction command 52, etc.) are analyzed.

The analysis unit 14 includes the arithmetic processing unit 12 and the storage unit 1
8 is connected. When the analyzed command is a multifunction command or a function command, the analysis unit 14 converts these commands and operand data such as comparison data into the arithmetic processing unit 1.
2 and the storage unit 18 (a memory control unit 30 described later). The analyzing unit 14 is connected to the transfer unit 16, and transfers the command to the transfer unit 16 when the analyzed command is a transfer command.

The arithmetic processing section 12 performs each arithmetic processing for each arithmetic processing based on the composite function command 52 analyzed by the analyzing section 14, and outputs each arithmetic processing result. The processing unit 12 is connected to the storage unit 18.

The transfer unit 16 takes in data from the input / output device 4 based on the transfer command 51 analyzed by the analysis unit 14. Then, when instructed to perform arithmetic processing on these data, the transfer unit 16 temporarily transfers the data to the storage unit 18. On the other hand, when the transfer unit 16 has not been instructed to perform the arithmetic processing on the data, the transfer unit 16 transfers the data to the main storage device 8 as it is. And
The transfer unit 16 transfers the result of performing all the arithmetic processing indicated by the multifunction instruction 52 in the arithmetic processing unit 12 to the transfer instruction 51.
Is transferred to the main storage device 8 based on.

The transfer unit 16 includes an I / F circuit 20 and an I / F
It has a circuit 22 and a buffer 24. I / F circuit 2
0 is connected to the input / output device 4 via the input / output bus 3a. The I / F circuit 22 is connected to the main storage device 8 via the system bus 3b. These I / F circuits 20 and 22 perform the following operations. That is, I / F
The circuits 20 and 22 issue a request for acquiring the bus to the bus, and when acquiring the bus right, issue commands, addresses, and the like according to the bus protocol, and start writing and reading data. Also, the I / F circuit 2
0 and 22 start writing and reading data to and from the device in response to a request from the device that has acquired the bus right.

The I / F circuit 20 starts reading data from the input / output device 4 according to the instruction of the transfer command 51 analyzed by the analysis unit 14.

When the transfer program 10 is received, the I / F circuit 22 transmits each command to the analyzing unit 14 and does not receive data from the buffer 24 according to an instruction from the analyzing unit 14. Then, the I / F circuit 22
In the case where the result of the arithmetic processing performed by all the arithmetic processing specified by the composite function command 52 is stored in the memory 26, the result of the arithmetic processing is stored in the main storage device 8 based on the transfer instruction 51.
Transfer to

The buffer 24 is interposed between the I / F circuit 20 and the I / F circuit 22. This buffer 24 adjusts the difference in data width between the input / output bus 3a and the system bus 3b.

The storage unit 18 has a memory 26 (storage unit), a storage address instruction register group unit 28, and a memory control unit 30. In the storage unit 18, the memory control unit 30
The memory 26 and the storage address instruction register group 28
Is connected. The memory control unit 30 includes the arithmetic processing unit 1
2 are also connected. Also, the memory control unit 30
/ F circuit 22 and to buffer 24.

The transfer of transfer data and the result of arithmetic processing in the storage unit 18 will be described below. The data transferred from the input / output device 4 and the calculation processing result are stored in the memory control unit 3.
0 is stored in the memory 26. At this time, the memory control unit 30 sets the storage location of the data in the storage address instruction register group unit 28. The storage address instruction register group 28 stores a storage address indicating the storage location of the data in the memory 26 and an operation result storage address indicating the storage location of the operation result in the memory 26. These addresses are stored in the memory controller 3
According to the instruction of 0, the data is read from the storage address instruction register group 28 as necessary. Also, the memory control unit 3
0 indicates that when performing a plurality of types of arithmetic processing, each arithmetic processing result is transferred between the arithmetic processing unit 12 and the memory 26 to sequentially perform each arithmetic processing and storage.

As described in the background art, the transfer command 51 is a command for transferring data from the input / output device 4 to the main storage device 8. However, when the transfer command 51 follows the multifunction command 52, a plurality of types of arithmetic processing indicated by the multifunction command 72 are performed when data is transferred from the input / output device 4 to the main storage device 8. . For this reason, the data specified by the transfer command 51 and transferred from the input / output device 4 is once transferred to the memory control unit 30. And
Based on the composite function command 52, the arithmetic processing unit 12 performs each arithmetic processing. Then, when the result of the arithmetic processing on which all the arithmetic processing has been performed is stored in the memory 26, the transfer command 5
The result of the arithmetic processing is transferred to a predetermined position in the main storage device 8 (the address specified by the result storage address section) by the I / F circuit 22 set based on the number 1.

(2) Operation of Information Transfer Apparatus The information transfer apparatus 2 configured as described above performs a plurality of types of arithmetic processing on data transferred from the input / output device 4 (hereinafter referred to as transfer data). After the application, the main storage device 8
The operation of transferring to the server will be described below.

First, the CPU 6 issues a data transfer command to the information transfer device 2. Then, the information transfer device 2 transmits the transfer program 10 from the main storage device 8 to the I / O device.
The data is read out via the F circuit 22 and the transfer program 10 is analyzed by the analysis unit 14.

In the transfer program 10, a composite function command is arranged before the transfer command.

Next, the analyzing unit 14 analyzes the composite function command 52. Then, the analysis unit 14 makes the calculation processing unit 12
Then, the multi-function command designated by the command code section and the comparison data stored at the comparison operand address designated by the comparison operand address section are transferred to the memory control section 30. At the same time, the analysis unit 14
It instructs the I / F circuit 22 to stop data transfer to the main storage device 8.

Subsequently, based on the analyzed composite function command 52, the arithmetic processing section 12 identifies the arithmetic processing specified by the command code section, makes preparations for setting a plurality of types of arithmetic processing, and Waiting for the to be transferred. The memory control unit 30 sets a storage address and an operation processing result storage address, and stores these addresses in the storage address instruction register group unit 28.

When the transfer command 51 is analyzed by the analyzer 14, the transfer command 51 is transferred from the analyzer 14 to the I / F circuit 20. According to the instruction of the transfer command 51, I
The / F circuit 20 starts reading the amount of transfer data specified by the byte count unit from the input / output device 4 from the address in the input / output device 4 specified by the data address unit. At this time, the buffer 24 adjusts the data width of the read transfer data. Then, the I / F circuit 20 transfers the transfer data to the memory control unit 30 via the buffer 24. The memory control unit 30 reads the storage address from the storage address instruction register group unit 28, and transfers the transfer data to the memory 2 according to the storage address.
6 is stored. At this time, after reading the storage address, the memory control unit 30 increments the storage address by the data transfer amount. Then, the memory control unit 30
The transfer data is sequentially stored in the memory 26 in accordance with the incremented storage address.

When the amount of transfer data specified by the byte count unit is stored in the memory 26, the memory control unit 30 reads the transfer data from the memory 26 and transfers the read data to the arithmetic processing unit 12. The arithmetic processing unit 12 to which the transfer data has been transferred is a predetermined arithmetic processing (primary arithmetic processing)
Is performed on the transfer data, and the result (hereinafter, referred to as an operation processing result) is output to the memory control unit 30. As this arithmetic processing, for example, there is a search processing. In this case,
The arithmetic processing unit 12 outputs only transfer data that matches the comparison data as an arithmetic processing result. This comparison data
This is the data stored at the address of the comparison operand address section.

Then, in response to the output operation processing result, the memory control unit 30 reads the operation processing result storage address from the storage address instruction register group unit 28 and stores the operation processing result in the operation processing result address of the memory 30. I do. At this time, after reading the operation processing result storage address from the storage address instruction register group unit 28, the memory control unit 30 increments this address by the transfer amount of the operation processing result. Then, the memory control unit 30 sequentially stores the result of the arithmetic processing in the memory 26 according to the address.

Then, when the transfer data which has not been subjected to the arithmetic processing no longer exists in the memory 26, the memory control unit 30
Instructs the arithmetic processing unit 12 to prepare for the next arithmetic processing (hereinafter referred to as secondary arithmetic processing). At the same time, the memory control unit 26 sets a secondary operation processing result storage address, which is a location (position) for storing a secondary operation result obtained by performing a secondary operation on the operation result, and sets this address. The data is stored in the storage address instruction register group 28.

When the preparation for the secondary operation is completed, the memory control unit 30 reads out the operation results stored in the operation result address in the memory 26 and sequentially transfers them to the operation unit 12. The arithmetic processing unit 12 to which the arithmetic processing result has been transferred performs a secondary arithmetic processing, and outputs a secondary arithmetic processing result. The memory control unit 30 reads the secondary operation processing result storage address from the storage address instruction register group unit 28 and stores the secondary operation processing result in the secondary operation processing result storage address of the memory 26. At this time, after reading the secondary operation processing result storage address, the memory control unit 30 increments this address by the transfer amount of the secondary operation processing result. Then, the memory control unit 30 sequentially stores the result of the secondary operation processing in the memory 26 according to the incremented address.

When the arithmetic processing section 12 completes the secondary arithmetic processing, the memory control section 30 notifies the I / F circuit 22 of the completion of the secondary arithmetic processing. The result of the secondary operation processing is transferred to the main storage device 8 based on the result. At this time, the memory control unit 30 identifies the secondary operation processing result storage address from the address stored in the storage address instruction register group unit 28, and sequentially stores the secondary operation processing result from the secondary operation processing result storage address in the memory 26. The data is read and transferred to the I / F circuit 22. Then, the I / F circuit 22 transfers the secondary operation processing result to the result storage address of the main storage device 8 based on the transfer command.

In the information transfer device 2 according to the present embodiment,
A memory 26 is provided. Therefore, this memory 2
6 can store a large amount of data. And
The information transfer device 2 according to the present embodiment converts the data
The data can be stored in the memory 26 in accordance with each address (predetermined position) designated by the storage address designation register group 28. For this reason, the information transfer apparatus 2 according to the present embodiment can store the arithmetic processing results in the memory 26 even if a plurality of types of arithmetic processing are performed on the transfer data, organized for each arithmetic processing. Further, the information transfer device of the present embodiment has a memory control unit 30.
Performs an arithmetic operation on the transferred data,
After storing the arithmetic processing result in the arithmetic processing unit 12, the arithmetic processing result is transferred between the arithmetic processing unit 12 and the memory 26 a plurality of times.
Each operation processing and storage can be sequentially performed. Then, when all of the arithmetic processing specified by the multifunction command have been performed, the transfer unit 16 stores the arithmetic processing result in the main storage device 8.
Transfer to As a result, the information transfer device 2 of the present embodiment
Can perform a plurality of types of arithmetic processing on the data transferred from the input / output device 4 and then transfer the data to the main storage device 8.

The information transfer apparatus 2 according to the present embodiment can also search for data matching predetermined conditions and process the data. For this reason, the information transfer device 2 according to the present embodiment can perform the same level of arithmetic processing as the CPU 6, so that the load on the CPU 6 can be further reduced as compared with the related art. Further, the information transfer device 2 according to the present embodiment transfers only the calculated result to the system bus 3b, so that the load on the system bus 3b can be reduced.

When the transfer data transferred from the input / output device 4 is transferred directly to the main storage device 8, only the transfer command 51 is stored in the transfer program 10. Then, the transfer command analyzed by the analysis unit 14 is notified to the I / F circuit 20. Then, the I / F circuit 20 causes the input / output device 4 to transfer the transfer data based on the transfer command 51, and transfers the transfer data to the main storage device 8 via the I / F circuit 22.

Embodiment 2 The system including the information transfer apparatus according to the second embodiment is different from the system according to the first embodiment shown in FIG. 1 in that the configuration of the multifunction command stored in the transfer program 10 and the memory control unit 3
0, the function of the arithmetic processing unit 12, and the function of the transfer unit 16. Hereinafter, in the system including the information transfer device according to the second embodiment, the configuration of the multifunction command and functions different from those of the information transfer device according to the first embodiment will be described in detail.

The multifunction command according to the second embodiment has a multifunction start command and a multifunction end command. The types of the composite function start command and the composite function end command are shown in FIGS. 3 (b-1) and (b-2), respectively. The composite function start command 53 is a command for instructing the start of a plurality of types of arithmetic processing. The composite function start command 53 has a command code part, a comparison operand address part, and a flag part.
The command code portion and the comparison operand address portion are the same as those shown in FIG. For example, the flag processing unit 1 performs an arithmetic operation using comparison data and performs an arithmetic operation until a predetermined condition is met.
2 is instructed to the arithmetic processing unit 12 for a condition for performing arithmetic processing on transfer data.

The composite function termination command 54 is a command for instructing termination of a plurality of types of arithmetic processing, and has a command code part and a result storage address part. The command code part is for instructing the termination of a plurality of types of arithmetic processing.
The command ND is issued. The result storage address part is the same as that shown in FIG.

Note that the composite function termination command 54 is
Even if it is analyzed by, each calculation process is not completed until all the calculation processes specified by the composite function start command are performed by the calculation processing unit 12.

After transferring the transfer data transferred from the input / output device 4 to the memory 26, the memory control unit 30 performs each calculation process on the calculation processing unit 12 based on the analyzed composite function start command 53. Let Also, the memory control unit 30
Means that a predetermined amount of transfer data from the input / output device 4 is stored in the memory 26
If the stored multi-function end command is stored in the
4, the transfer of the transfer data to the memory 26 is terminated. When the memory control unit 30 has performed all the arithmetic processing based on the composite function start command 53 for the arithmetic processing unit 12, the memory control unit 30 performs the arithmetic processing based on the composite function start instruction 53 based on the composite function end instruction 54. To end.

When the I / F circuit 22 (transfer unit) recognizes that all the arithmetic processing specified by the composite function start command 53 has been completed based on the composite function end command 54,
The transfer specified in advance by the transfer command 51 is performed. That is, based on the transfer command 51, the I / F circuit 22 transfers the result of the arithmetic processing on which all the arithmetic processing has been performed to the main storage device 8.

The operation of using the information transfer device 2 according to the second embodiment to perform arithmetic processing on data transferred from the input / output device 4 and then transfer the data to the main storage device 8 will be described below. I do.

CPU 6 issues a data transfer command to information transfer device 2. Then, the information transfer device 2 transmits the transfer program 1 from the main storage device 8 via the I / F circuit 22.
Read 0. Then, the transfer program 10 is analyzed by the analysis unit 14. In the transfer program 10, for example, a multifunction start command 53, a transfer command 51, and a multifunction end command 54 are stored in the above order.

First, the analysis section 14 sets a composite function start command 5
3 is analyzed. Then, based on the analyzed composite function start command 53, the arithmetic processing unit 12 is set so that each arithmetic processing can be performed. Also, the memory control unit 30
Each address such as a storage address is set, and these are stored in the storage address instruction register group 28.

Next, the information transfer device 2 sequentially stores the transfer data transferred from the device A at the storage address in the memory 26 based on the analyzed transfer command 51.

Subsequently, when a predetermined amount of transfer data specified by the transfer command 51 is stored in the memory 26, the memory control unit 30 reads the transfer data from the memory 26 and transfers the read data to the arithmetic processing unit 12. The operation processing unit 12 to which the transfer data has been transferred performs an operation process (primary operation process) specified by the analyzed composite function start command, and outputs the operation process result to the memory control unit 30.

The memory control unit 30 sequentially reads the operation processing result storage addresses from the storage address instruction register group unit 28 in response to the output operation processing results, and
The operation processing results are stored in the respective operation processing result storage addresses.

Then, similarly to the first embodiment, the arithmetic processing unit 12 and the like prepare for the secondary arithmetic processing. And
The arithmetic processing unit 12 performs secondary arithmetic processing on all arithmetic processing results. Then, the multifunction termination command 54 in the transfer program 10 is read into the information transfer device 2, and the multifunction termination command 54 is analyzed by the analysis unit 14. Based on the analyzed composite function end instruction 54, the memory control unit 30 causes the arithmetic processing unit 12 to terminate the arithmetic processing based on the composite function start instruction 53. That is, in the arithmetic processing unit 12, the setting instructed to perform the arithmetic processing by the composite function start command 53 is released. Further, based on the composite function termination command 54, the memory control unit 30 terminates the transfer of the transfer data transferred from the input / output device 4 to the memory 26. That is, the composite function end command 54
, The setting instructed to take in the transfer data is canceled in the memory control unit 30.

The memory control unit 30 notifies the I / F circuit 22 that all arithmetic processing has been completed, based on the composite function termination command 54. The I / F circuit 22 recognizes that all the arithmetic processing is completed, and performs the transfer specified by the transfer command 51. That is, the arithmetic processing result (secondary arithmetic processing result) subjected to all the arithmetic processing is transferred to the main storage device 8.

In this embodiment, when one transfer command and one multifunction command are arranged in the transfer program 10, the operation is the same as that of the first embodiment. However, when a plurality of transfer commands and a plurality of multifunction commands are stored in one transfer program 10, the operation is different. For example, when a plurality of mutually different multifunction commands are stored in the transfer program 10, that is, a first multifunction command, a first transfer instructing the transfer of the operation target data indicated by the first multifunction command In the case where a command, a second multifunction command, and a second transfer command for instructing the transfer of the data to be operated specified by the second multifunction command are arranged, the multifunction command according to the second embodiment will be described below. The model is preferred.

The arithmetic processing unit 12 receives the instruction to start each arithmetic processing indicated by the composite function command, and finally receives the instruction to end the composite function instruction, and then executes the arithmetic processing of the set composite function instruction. Can not be terminated. And
The multifunction command according to the first embodiment does not include a command to end the multifunction command. For this reason, in the first embodiment, when the first multifunction instruction is set in the arithmetic processing unit 12, the arithmetic processing unit 12 can perform only the arithmetic processing of the first multifunction instruction. As a result, in the first embodiment, even if data is transferred based on the second transfer command, the second
The arithmetic processing specified by the composite function command cannot be performed.

On the other hand, in the second embodiment,
Each composite function command has a composite function start command and a composite function end command. Then, based on the composite function start command,
The arithmetic processing unit 12 is set so that each arithmetic processing indicated by the composite function start command can be performed. Then, when the arithmetic processing unit 12 has performed all the arithmetic processing indicated by the composite function start command, the setting is released based on the composite function end command 54. Thereby, the information transfer apparatus 2 of the second embodiment can change the arithmetic processing performed by the arithmetic processing unit 12 for each multifunction command.

In the second embodiment, based on the composite function end command 54, the memory control unit 30 ends storing the transfer data in the memory 26. For this reason, when the subsequent transfer data is transferred to the main storage device 8 as it is after performing the arithmetic processing according to the composite function start command 53 on certain transfer data, the subsequent transfer data is not stored in the memory 26. . Thus, the information transfer device according to the second embodiment can perform data transfer without performing the arithmetic processing after data transfer after performing the arithmetic processing of the composite function start command.

Embodiment 3 The system including the information transfer device according to the third embodiment differs from the system according to the second embodiment in that the function of the memory control unit 30 is different. Hereinafter, in the system including the information transfer device according to the third embodiment, functions different from those of the information transfer device according to the second embodiment will be described in detail.

After storing the transfer data transferred from the input / output device 4 in the memory 26, the memory control unit 30 transfers the transfer data to the arithmetic processing unit 12. If the transfer data does not match the predetermined condition specified by the flag unit, the memory control unit 30
6 and transfer the subsequent transfer data from the transfer data from the memory 26 to the arithmetic processing unit 12. Then, when the transfer data matches the predetermined condition, the memory control unit 30 stops transferring the transfer data subsequent to the transfer data from the memory 26 to the arithmetic processing unit 12.

Using the information transfer device 2 according to the third embodiment, data transferred from the input / output device 4
The operation of performing the arithmetic processing and transferring the data to the main storage device 8 will be described below.

The information transfer device 2 sends the I / O
The operation from the operation of reading the transfer program 10 via the F circuit 22 to the storage of the transfer data transferred from the input / output device 4 by a predetermined amount (the amount specified by the transfer command) in the memory 26 is as follows. This is the same as in the second embodiment. Less than,
The continuation will be described.

The memory control 30 reads the transfer data from the memory 26 and transfers the transfer data to the arithmetic processing unit 12. The arithmetic processing unit 12 to which the transfer data has been transferred performs the arithmetic processing indicated by the analyzed composite function start command 53, and outputs the arithmetic processing result to the memory control unit 30.

At this time, for example, if the arithmetic process indicated by the multifunction start command is a search process, the multifunction start command 5
The following instruction is described in the flag section of No.3. That is, the flag section indicates that the arithmetic processing section 12 is instructed to transfer the transfer data to the memory 26 as an arithmetic processing result until the transfer data transferred from the memory 26 matches the predetermined condition. I have. Arithmetic processing unit 12
Performs a search process on the transfer data transferred from the memory 26 based on a predetermined condition specified by the flag unit. For example, the arithmetic processing unit 12 performs a search process to determine whether or not the transfer data transferred from the memory 26 matches the comparison data. As a result of this search processing, if each transfer data does not match the predetermined condition, the memory control unit 3
A value of 0 causes the arithmetic processing unit 12 to transfer the arithmetic processing result to the memory 26 and to transfer the transfer data from the memory 26 to the arithmetic processing unit 12. Then, when the transfer data matches the predetermined condition, the arithmetic processing unit 12 notifies the memory control unit 30 of the match. Then, the memory control unit 3
0 stops transfer of transfer data following the transfer data from the memory 26 to the arithmetic processing unit 12. Note that the memory control unit 30 outputs the calculation processing result from the calculation processing unit 12 to the memory 26 until the transfer data matches the predetermined condition.

In response to the output arithmetic processing result, the memory control unit 30 stores the address instruction register group 28
From the memory 2 is read from the memory 2
The result of the arithmetic processing is stored in the above-mentioned address in 6.

Then, the arithmetic processing section 12 performs the search processing (1
When the next operation process is completed, the second operation process is prepared. When the arithmetic processing unit 12 performs the secondary arithmetic processing on all the arithmetic processing results, the composite function end command 54
Is analyzed by the analysis unit 14. Based on the analyzed composite function end instruction 54, the memory control unit 30 causes the arithmetic processing unit 12 to terminate the arithmetic processing based on the composite function start instruction 53. Further, the memory control unit 30 ends transferring the transfer data transferred from the input / output device 4 to the memory 26. Then, based on the composite function termination command 54, the memory control unit 30 notifies the I / F circuit 22 that all the arithmetic processing has been completed. I / F circuit 2
2 recognizes that all the arithmetic processing has been completed, and transfers the secondary arithmetic processing result stored in the memory 26 to the main storage device 8 based on the transfer command 51.

In the third embodiment, for example, when the data stored in the input / output device 4 is sorted, the arithmetic processing unit 12 sets a predetermined condition in the flag unit during the primary arithmetic processing such as the search processing. Transfer data that satisfies the condition can be searched, and only the searched transfer data can be subjected to the secondary arithmetic processing. Therefore, the information transfer device 2 according to the third embodiment
In the arithmetic processing of a large amount of transfer data, the data to be subjected to the arithmetic processing can be limited to data satisfying a predetermined condition, so that the arithmetic amount of the arithmetic processing unit 12 can be reduced.

Embodiment 4 The system including the information transfer device according to the fourth embodiment is different from the system according to the second embodiment in the configuration of the multifunction start command stored in the transfer program 10 and the function of the memory control unit 30. On the point. Hereinafter, in the system including the information transfer apparatus according to the fourth embodiment, the configuration of the multifunction start command and functions different from those of the information transfer apparatus according to the second embodiment will be described in detail.

FIG. 3C-1 is a diagram showing a model of the composite function start command according to the fourth embodiment. At this time, FIG.
The detailed description of the same components as in 1) is omitted. The composite function start command 55 has a count section in addition to a command code section, a comparison operand address section, and a flag section. This counting unit indicates the amount of data to be transferred to the memory 26 without performing any arithmetic processing on the transfer data transferred from the memory 26.

After storing the data transferred from the input / output device 4 in the memory 26, the memory control unit 30 transfers the transferred data to the arithmetic processing unit 12. And the transfer data is
When the predetermined condition specified by the flag section is satisfied, the memory control section 30 calculates the amount of transfer data specified by the counting section with respect to the transfer data subsequently transferred from the transfer data to the arithmetic processing means. Is transferred to the memory 26 as it is.

The operation of using the information transfer device 2 according to the fourth embodiment to perform an arithmetic process on the data transferred from the input / output device 4 and then transfer it to the main storage device 8 will be described below. I do.

The information transfer device 2 sends an I / F from the main storage device 8
The operation from the operation of reading the transfer program 10 via the circuit 22 to the storage of a predetermined amount of transfer data transferred from the input / output device 4 in the memory 26 is the same as in the third embodiment. Hereinafter, the continuation will be described.

Then, a predetermined amount of transfer data specified by the transfer command 51 is stored in the memory 26. Then, the memory control unit 30 reads the transfer data from the memory 26 and transfers the read data to the arithmetic processing unit 12. For example, in the flag section,
If the transfer data matches the predetermined condition, and if it is described to instruct the arithmetic processing unit 12 to transfer the transfer data to the memory, the arithmetic processing unit 12 sends the transfer data transferred from the memory 26 Then, a search process is performed for a predetermined condition specified by the flag unit. As a result of the search processing, if the transfer data does not match the predetermined condition, the arithmetic processing unit 12 does not output anything to the memory control unit 30. If the transfer data matches the predetermined condition, the arithmetic processing unit 12
Notifies the memory control unit 30 that they match. Upon receiving this notification, the memory control unit 30 does not cause the arithmetic processing unit 12 to perform the arithmetic processing on the amount of transfer data specified by the counting unit with respect to the transfer data subsequent to the matched transfer data. Is stored in the operation result address. The memory control unit 30 has a counter, and can count the amount of transferred data. And
The arithmetic processing unit 12 performs a search process on all the transfer data stored in the memory 26 using the flag unit as described above.

When the primary processing (search processing) is completed, the arithmetic processing unit 12 prepares for the secondary processing. The arithmetic processing unit 12 calculates 2 for all the arithmetic processing results.
When the next operation processing is performed, the composite function end command 54 is
Analyzed at 4. Based on the analyzed composite function end instruction 54, the memory control unit 30 causes the arithmetic processing unit 12 to terminate the arithmetic processing based on the composite function start instruction. Further, the memory control unit 30 ends transferring the transfer data transferred from the input / output device 4 to the memory 26. Then, based on the composite function termination command 54, the memory control unit 30 notifies the I / F circuit 22 that all the arithmetic processing has been completed. The I / F circuit 22 recognizes that all the arithmetic processing has been completed, and transfers the result of the secondary arithmetic processing stored in the memory 26 to the main storage device 8 based on the transfer command 51.

The information transfer apparatus 2 according to the fourth embodiment searches the transfer data transferred to the memory 26 to see if it matches a predetermined condition. When certain transfer data matches the predetermined condition, the memory control unit 30 causes the arithmetic processing unit 12 to perform a predetermined amount of data (instructed by the counter unit) without performing the arithmetic processing on the transfer data subsequent to the transfer data. ) Is transferred to the memory 26. For this reason, when a large amount of data having one record consisting of a plurality of fields is stored in the input / output device 4 in large quantities, if the transfer data is searched using a predetermined field as a key, for example, The respective transfer data can be stored in the memory 26. As a result, the information transfer device 2
Can be stored in the memory 26 without searching for the other fields as long as only the predetermined field is searched without performing the searching for all the fields of the record of the transfer data. This makes it possible to reduce the amount of calculation in the calculation processing unit 12.

Embodiment 5 The system including the information transfer apparatus according to the fifth embodiment is different from the system according to the fourth embodiment in the configuration of the composite function start command stored in the transfer program 10 and the function of the arithmetic processing unit 12. On the point. Hereinafter, in the system including the information transfer apparatus according to the fifth embodiment, the configuration of the multifunction start command, functions different from those of the information transfer apparatus according to the fourth embodiment,
Will be described in detail.

The multifunction start command according to the fifth embodiment is
In addition to a start command 55 shown in FIG. 3 (c-1) (hereinafter, in the present embodiment, a combined function start command is a combination of the start command 55 and an operand command 56 to be described later is referred to as a combined function start command). , Operand instructions 56. The operand instruction 56 is an instruction for instructing the arithmetic processing unit 12 to perform an arithmetic operation on only the predetermined part of the transfer data transferred from the memory 26. FIG. 3C-2 is a diagram showing a model of the operand command 56. Operand instruction 56 has a comparison operand data address portion and an operation mask portion. The operation mask unit indicates a portion to be subjected to an operation process on the transfer data. The comparison operand data address portion is the same as that of FIG. 3 (c-1).

The arithmetic processing unit 12 performs an arithmetic operation specified by the start instruction 55 on a predetermined portion of the transfer data transferred from the memory 26 based on the operand instruction 56. The predetermined portion is specified by an operation mask unit.

The operation of using the information transfer device 2 according to the fifth embodiment to perform arithmetic processing on data transferred from the input / output device 4 and then transfer the data to the main storage device 8 will be described below. I do.

Since the information transfer device 2 according to the fifth embodiment reads the transfer program 10 from the main storage device 8 via the I / F circuit 22, the transfer data transferred from the input / output device 4 is stored in the memory 26. The operation up to storage is the same as in the fourth embodiment. Hereinafter, the continuation will be described.

When the transfer data is stored in the memory 26, the memory control unit 30 reads the transfer data from the memory 26 and transfers the read data to the arithmetic processing unit 12. Arithmetic processing unit 1
2 is for transfer data transferred from the memory 26,
The arithmetic processing is performed based on the operand instruction 56. The arithmetic processing based on the operand command 56 will be described in detail below.

For example, when the flag unit instructs the transfer of the transfer data to the memory 26 when the transfer data matches the predetermined condition, the arithmetic processing unit 12 performs the following search processing as the primary arithmetic processing. I do. That is, the arithmetic processing unit 12 compares the transfer data transferred from the memory with the comparison data in the comparison operand address section, and searches whether or not the data matches the predetermined condition indicated by the flag section. At this time, the data portion for comparing the transfer data with the comparison data is only the portion specified by the operation mask unit. For example, the operation mask unit is set to 0 for 8-byte transfer data.
When 1111000 is specified, the comparison target portion is 2 to 5 bytes of data, and 1, 6, 7, and 8 bytes of data are ignored. Then, the arithmetic processing unit 12 compares only the part (2 to 5 bytes) specified by the arithmetic mask unit in the transfer data with the corresponding part (2 to 5 bytes) of the comparison data.

As a result of the comparison, if the transfer data does not match the predetermined condition, the arithmetic processing unit 12
Nothing is output to 0. As a result of the comparison, when they match, the arithmetic processing unit 12 notifies the memory control unit 30 of the match. Upon receiving the notification of the coincidence, the memory control unit 30 transfers the data amount designated by the counting unit to the operation processing result storage address in the memory 26 for the subsequent transfer data from the coincident transfer data. Then, after the amount of data designated by the counting unit is transferred from the arithmetic processing unit 12 to the memory, the arithmetic processing unit 12 performs the arithmetic operation based on the operand command 56 on the subsequent transfer data as described above. Perform processing. These search and transfer operations are stored in memory 2
6 for all the transfer data stored in the memory.

When the primary processing (search processing) is completed, the arithmetic processing unit 12 prepares for the secondary processing. The arithmetic processing unit 12 calculates 2 for all the arithmetic processing results.
When the next operation processing is performed, the composite function end command 54 is
Analyzed at 4. Based on the analyzed composite function end command 54, the memory control unit 30 causes the calculation processing unit 12 to end the calculation process based on the start command 55.
Further, the memory control unit 30 ends transferring the transfer data transferred from the input / output device 4 to the memory 26. Then, the memory control unit 30 issues the multifunction termination command 5
Based on No. 4, the I / F circuit 22 is notified that all arithmetic processing has been completed. The I / F circuit 22 recognizes that all the arithmetic processing has been completed, and transfers the result of the secondary arithmetic processing stored in the memory 26 to the main storage device 8 based on the transfer command 51.

The information transfer apparatus of the fifth embodiment can perform arithmetic processing on transfer data transferred to the memory 26 only for a part thereof. For this reason,
It becomes easy to set conditions such as search for transfer data, and the amount of calculation processing can be reduced.

Note that the operand command 56 in the present embodiment can be applied to the arithmetic processing (primary arithmetic processing) described in the third embodiment. In this case, a portion to be subjected to arithmetic processing is specified by the operation mask unit for the transfer data and the comparison data to be searched.

Embodiment 6 FIG. FIG. 2 is a block diagram showing a data transfer system including an information transfer device according to the sixth embodiment.

One side of the information transfer device 40 is connected to the CPU 6 and the main storage device 8 via the system bus 3b. The other side of the information transfer device 40 is connected to the input / output buses 3a, 3a.
c, they are connected to the input / output devices 4a, 4b, respectively.

The information transfer device 40 includes two input / output devices 4
In correspondence with a and 4b, each has two functions of the information transfer device with an arithmetic processing function of FIG.

That is, for the input / output device 4a, the arithmetic processing unit 12a, the memory 26a, the memory control unit 30a, the storage address instruction register group unit 28a, the transfer unit (I / F circuit 2
0a, buffer 24a, I / F circuit 23) and analysis unit 1
5 (hereinafter collectively referred to as a first arithmetic processing unit). Then, for the input / output device 4b, the arithmetic processing unit 12b, the memory 26b, the memory control unit 30b,
Storage address instruction register group 28b, transfer unit (I / F
The circuit 20b, the buffer 24b, the I / F circuit 23) and the analysis unit 15 (hereinafter, these are collectively referred to as a second arithmetic processing function unit) correspond. However, in the information transfer device 40, I
The / F circuit 22 and the analysis unit 14 are each one.

The multifunction command and the transfer command included in the transfer program 10 are respectively shown in FIGS. 3 (d-1) and (d-
See 2). The detailed description of the same commands as those shown in FIGS. 3A-1 and 3A-2 is omitted.

The transfer command 57 has a device address section for identifying each input / output device, in addition to a command code section, a data address section, a flag section, and a byte count section. The composite function command 58 has a command code part, a result storage address part, a comparison operand address part, and the device address part.

In FIG. 2, a configuration having a function different from that of FIG. 1 will be described below.

The analysis unit 15 analyzes a multifunction command or a transfer command, and, based on a device address section included in the multifunction command or the like, analyzes the first operation processing function unit (the memory control unit 30).
a) or the second arithmetic processing function unit (memory control unit 30b)
The analyzed command is transferred to

The I / F circuit 23 transfers the data and the result of the arithmetic processing transferred from each arithmetic processing function unit to the main storage device 8 via the system bus.

The operation of using the information transfer device with arithmetic function 40 configured as described above to perform arithmetic processing on the data transferred from the input / output device and then transferring the data to the main storage device 8 This will be described below.

The CPU 6 issues a data transfer command to the information transfer device 40. Then, the information transfer device 4
0 is the transfer program 1 stored in the main storage device 8
0 is read out via the I / F circuit 23. The read transfer program 10 is analyzed by the analysis unit 15. The analysis unit 15 analyzes the device address part of the multifunction command 58 and determines an input / output device. For example, when the input / output device 4a is determined, the analysis unit 15 serves as an arithmetic processing function unit that performs arithmetic processing on data transferred from the input / output device 4a.
Determines the memory control unit 30a, the arithmetic processing unit 12a, the memory 26a, the storage address instruction register group unit 28a, and the transfer unit (I / F circuit 20a, buffer 24a) corresponding to the input / output device 4a.

When the input / output device 4a and the like are determined in this manner, the determined arithmetic processing unit 12a and the like are set so as to be able to perform each arithmetic process specified by the composite function command. The following operation (transfer of data from the input / output device, primary operation processing, secondary operation processing, transfer of the result of the secondary operation processing to the main memory) is the same as that of the information transfer apparatus of the first embodiment.

When the input / output device 4b is determined,
As an arithmetic processing function unit that performs arithmetic processing on data transferred from the input / output device 4b, the analysis unit 15
b, the memory control unit 30b, the arithmetic processing unit 12b,
A memory 26b, a storage address instruction register group 28b,
The transfer unit (I / F circuit 20b, buffer 24b) is determined.

In the sixth embodiment, among the plurality of input / output devices, a plurality of types of arithmetic processing can be performed during the data transfer from each input / output device to main storage device 8. . For this reason, data to be subjected to arithmetic processing is stored separately in the input / output devices 4a and 4b according to the model, and the arithmetic processing units 12a and 12b are implemented as dedicated hardware according to the processing method. be able to.
Thus, one information transfer device 40 can handle various arithmetic processes such as scientific and technological calculations to office work.

The information transfer device 40 of the sixth embodiment
Is connected to the two input / output devices 4a and 4b,
It can be connected to N (N is an integer) input / output devices. At this time, in the information transfer device 40, a memory, an arithmetic processing unit, a memory control unit,
N transfer units (I / F circuits, buffers) are also provided, respectively. That is, N arithmetic processing units are built in the information transfer device 40.

Further, in the first to sixth embodiments, the case where data is transferred from the input / output device to the main storage device 8 has been described. The present invention is also applicable to the case where data is transferred by the device 4. In this case, the I / F circuit 20 (the I / F circuits 20a and 20b in the sixth embodiment) and the I / F 22 (the I / F circuit 23 in the sixth embodiment) are provided on the input side and the output side. Be exchanged.

Further, in the first to sixth embodiments, the data transfer between the input / output device 4 and the main storage device 8 has been described. However, the present invention is not limited to these devices, and general devices A and B are used. It can also be applied to data transfer between.

Further, in the first to sixth embodiments, a case has been described in which data is transferred by performing a composite operation process instructing two operation processes, but the present invention is also applicable to M (M is an integer) operation processes. Is possible. Further, the present invention can be applied to arithmetic processing other than search processing.

[0120]

According to the first aspect of the present invention, after the arithmetic processing means performs each arithmetic processing on a large amount of data transferred from the apparatus A, each arithmetic processing result is sorted out. Stored in the storage means. Further, the control means causes the arithmetic processing means to perform arithmetic processing, stores the arithmetic processing result in the storage means, and transfers the arithmetic processing result between the arithmetic processing means and the storage means a plurality of times. Thus, arithmetic processing and storage can be sequentially performed. Then, when all the arithmetic processing specified by the composite function command has been performed, the transfer unit transfers the arithmetic processing result to the device B. Therefore, according to the present invention, the data transferred from the device A can be subjected to a plurality of types of arithmetic processing and then transferred to the device B.

According to the second aspect of the present invention, based on the multifunction start instruction, the arithmetic processing means performs each operation specified by the multifunction start instruction. Then, based on the composite function end command, the arithmetic processing means terminates each arithmetic processing specified by the composite function start instruction, and cancels the setting of each arithmetic processing of the composite function start command to the arithmetic processing means. Thus, if a plurality of multifunction commands are included in the program, it is possible to change the arithmetic processing performed by the arithmetic processing means for each multifunction command.

According to the third aspect of the present invention, the arithmetic processing means for the data transferred from the device A uses the flag unit for determining whether the transferred data matches a predetermined condition. The arithmetic processing is performed, and only the transfer data that does not match the predetermined condition is transferred to the storage unit. For this reason,
According to the present invention, the transfer data to be subjected to the arithmetic processing can be selected by the flag section. Therefore, for example, the transfer data to be subjected to the secondary arithmetic processing is limited to reduce the arithmetic processing amount of the arithmetic processing means. Can be.

According to the fourth aspect of the present invention, when the data transferred from the device A matches a predetermined condition,
The data following the above data is transferred to the storage means by a predetermined amount without performing any arithmetic processing. For this reason, for example, when a large amount of data of one record is stored in the device A, the arithmetic processing unit
The data can be searched using, for example, a predetermined field as a key without performing the arithmetic processing on all the fields. For this reason, according to the present invention, it is possible to reduce the amount of calculation in the calculation processing means.

According to the fifth aspect of the present invention, the arithmetic processing means can perform arithmetic processing on the data transferred from the storage means only for a predetermined portion of the data. Therefore, according to the present invention, in addition to the effects described in claim 4, search processing of transferred data and the like become easy, and the amount of arithmetic processing is further reduced.

According to the sixth aspect of the present invention, n (n
(An integer), a plurality of types of arithmetic processing can be performed during the data transfer from each device An to the device B. For this reason, data to be subjected to arithmetic processing is stored separately in each device An according to its model, and each arithmetic processing means is provided with dedicated hardware for each arithmetic processing means according to its processing method. Can be.
Thus, one information transfer device can handle various arithmetic processes such as scientific calculations to office work.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a system including an information transfer device with an arithmetic processing function according to Embodiments 1 to 5 of the present invention.

FIG. 2 is a block diagram showing a system including an information transfer device with an arithmetic processing function according to a sixth embodiment of the present invention.

FIG. 3 is a schematic diagram showing a model of each command according to the embodiment of the present invention.

FIG. 4 is a block diagram showing a system including a conventional information transfer device with an arithmetic processing function.

[Explanation of symbols]

2,40,82 Information transfer device with arithmetic function, 4,4
a, 4b, 84 input / output device, 6 CPU, 8 main storage device, 10, 94 transfer program, 12, 12a, 1
2b, 88 arithmetic processing unit, 14, 15, 90 analysis unit,
16, 92 transfer unit, 18 storage unit, 20, 20a, 2
0b, 22, 23 I / F circuit, 24, 24a, 24b
Buffer, 26, 26a, 26b memory, 28, 2
8a, 28b storage address indication register group, 30,
30a, 30b memory control unit, 51, 57 transfer command, 52, 58 multifunction command, 53, 55 multifunction start command, 54 multifunction end command, 56 operand command.

 ──────────────────────────────────────────────────の Continued on the front page (72) Inventor Seiji Seki 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsubishi Electric Corporation

Claims (6)

[Claims] An analysis of a transfer program including an operation command instructing an operation process, and based on the analyzed operation command,
In an information transfer device with an arithmetic function for performing an arithmetic process on the data transferred from the device A and then transferring the data to the device B, the program includes a composite function command for instructing a plurality of types of arithmetic processes. An arithmetic processing means for performing each arithmetic processing for each arithmetic processing based on the analyzed multifunction command and outputting each arithmetic processing result; and a storage means for storing each arithmetic processing result at each predetermined position. And control means for transferring each arithmetic processing result between the arithmetic processing means and the storage means to sequentially perform each arithmetic processing and storage; and arithmetic processing in which all arithmetic processing of the multifunction command is performed Transfer means for transferring the result of the arithmetic processing to the device B when the result is stored in the storage means; and performing each arithmetic processing on the data transferred from the device A based on the composite function command. Performed, the operation result apparatus B
An information transfer device with an arithmetic function, wherein the information is transferred to a computer. 2. The multi-function command includes a multi-function start command for instructing the start of a plurality of types of arithmetic processing and a multi-function end command for instructing the end of a plurality of types of arithmetic processing. After transferring the data transferred from the device A to the storage means, based on the analyzed composite function start command, the arithmetic processing means performs each arithmetic processing, and the analyzed composite function end When a predetermined amount of the data is stored in the storage unit based on the command, the transfer of the data transferred from the device A to the storage unit is terminated, and the multi-function command is issued to the data. When all the arithmetic processings designated by the instruction have been performed, the arithmetic processing means terminates the arithmetic processing based on the composite function start command, and the transfer means based on the analyzed composite function end instruction. 2. The information transfer apparatus with an arithmetic function according to claim 1, wherein the arithmetic processing result on which all the arithmetic processings specified by the composite function start command are performed is transferred to the apparatus B. 3. The multifunction start command includes a flag for determining whether data transferred from the storage unit matches a predetermined condition, and the control unit converts the data transferred from the device A into the data. After storing the data in the storage means, the data is transferred to the processing means.If the data does not match the predetermined condition indicated by the flag, the processing result is transferred from the calculation processing means to the storage means. Transferring data subsequent to the data from the storage unit to the arithmetic processing unit; and transferring the data subsequent to the data from the storage unit to the arithmetic processing unit when the data matches the predetermined condition. 3. The information transfer device with an arithmetic function according to claim 2, wherein the operation is stopped. 4. The multi-function start command includes a flag for determining whether data transferred from the storage unit matches a predetermined condition, and does not perform an arithmetic process on the data transferred from the storage unit. The control unit stores the data transferred from the device A in the storage unit, and then transfers the data to the arithmetic processing unit. When the data matches a predetermined condition indicated by the flag, the data transferred from the data to the arithmetic processing means is not subjected to the arithmetic processing by the amount of data indicated by the count without performing the arithmetic processing. 3. The information transfer device with an arithmetic function according to claim 2, wherein the information is transferred to a storage unit. 5. The multi-function start command includes an operand command for instructing the data transferred from the storage means to perform a calculation process only on a predetermined portion of the data. , Based on the operand directive,
5. The information transfer device with a calculation function according to claim 3, wherein a calculation process specified by the composite function start command is performed on a predetermined portion of the data transferred from the storage unit. 6. A transfer program including an operation instruction for instructing operation processing is analyzed, and based on the analyzed operation instruction,
In an information transfer device with an arithmetic function for performing an arithmetic process on data transferred from n (n is an integer) devices and then transferring the data to the device B, the program instructs a plurality of types of arithmetic processes The multi-function command includes a device identification address for identifying each device An. Based on the analyzed multi-function command, each calculation process is performed for each calculation process. N (n is an integer) arithmetic processing means Cn for performing and outputting each arithmetic processing result, and n for storing each arithmetic processing result at each predetermined position.
(N is an integer) storage means Dn, and n operation results (n is an integer) for causing each operation processing result to be transferred between the operation processing means Cn and the storage means Dn to sequentially perform each operation processing and storage ) And transfer means for transferring the arithmetic processing result to the apparatus B when the arithmetic processing result obtained by performing all arithmetic processing of the composite arithmetic instruction is stored in the storage means Dn. Based on the analyzed multifunction command, the arithmetic processing means C
n, the storage means Dn and the control means En are determined, and the device An is determined from the device identification address, and the data transferred from the device An is subjected to each arithmetic processing based on the composite function command, Calculation result of device B
An information transfer device with an arithmetic function, wherein the information is transferred to a computer.