JPH11122564A - Image processing unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image processing unit in which digital decoration image data are easily synthesized for photographed image data and an image in a state of synthesizing the decorated images is loopback-displayed without using a memory with a high function resulting in a cost increase. SOLUTION: After an analog video signal is converted into digital image data by a decoder 3, the image data before being inputted to a reduction filter 6 are imparted to a switch 12 through a loopback line 13. The switch 12 selects the looped-back image data to attain the loop-back display on a display device 16. The image data whose the size is converted by the reduction filter 6 are stored in an image memory 8. The image data stored in the image memory 8 are fed to the switch 12 via a magnification filter 11 and the display device 16 can display and confirm the image data selected and outputted through the switch 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus used in an image printing system or the like for displaying a captured image on a monitor, further storing the image in a memory, and printing the image.

[0002]

2. Description of the Related Art A photo booth system including a camera, a display for displaying an image picked up by the camera, and a printer for printing the image picked up by the camera has been put into practical use (see, for example, Japanese Patent Application Laid-open No. 189308, JP-A-6-332070). In such a system, an image captured by a video camera is displayed as a moving image on a monitor, and an image is captured while an appropriate image is being captured while watching the monitor, and the image data is stored in a memory. If necessary, redo the image capture,
Thereafter, an image is printed based on the image data stored in the memory.

FIG. 2 is a schematic configuration diagram of a conventional image printing system. The input video signal of the image captured by the video camera is input to the switch 26 as an analog signal, and the switch 26 is normally controlled to selectively output the input video signal from the video camera.
Is output to. On the monitor 28, an image captured by the video camera is displayed as a moving image based on the supplied input video signal (hereinafter, inputting and displaying the input video signal on the monitor side is referred to as loopback display). The input video signal is also input to the decoder 21 at the same time as being input to the switch 26. When an image capture is instructed by an operation panel (not shown), the A / D is processed by the decoder 21 as digital image data. Is converted. A in the decoder 21
The / D-converted image data is scaled by a reduction filter 22 to a pixel (image) size suitable for printing.
The image data is stored in the image memory 24 via the image memory control circuit 23. When displaying based on the image data stored in the image memory to confirm the captured image, the image memory control unit 23 reads out the image data from the image memory 24 and supplies the image data to the encoder 25. Encoder 25
Then, the image data is converted into an analog signal and output as a video signal to the switch 26. The video signal from the encoder 25 is selected by the switch 26, and the captured image is displayed as a still image on the monitor 28. Then, if necessary,
When the image is recaptured and a print instruction is issued from an operation panel (not shown), the image data stored in the print control unit is read from the image memory 24, and the image is printed. The OSD (on-screen display) circuit 27 is for synthesizing a display such as a preset operation guide or operation status guide with the video signal from the switch 26 and displaying it on the monitor 28.

As described above, in the conventional image printing system, an image captured by a video camera needs to be sequentially loop-back displayed as a moving image in order for an operator to capture a preferable image.

[0005]

However, in the case where decorative image data such as a background image and a frame (frame) image is provided in advance and an appropriate decorative image is to be added to a captured image, the decorative image data is digital data. Although it is possible to easily synthesize a captured image (digital data), it is difficult to directly synthesize decorative image data with an analog video signal to be looped back for loopback display. For this reason, when the image captured by the video camera is displayed as a moving image in a loop-back manner, the image on which the decorative image has been synthesized cannot be confirmed on the monitor, and the monitor display of the captured image or the print result of the captured image cannot be performed. It was only possible to confirm the state where the decorative image was synthesized. Therefore, it is necessary to capture the image many times in order to check the state of synthesis with the decorative image, which is extremely inconvenient.

Therefore, it is conceivable to read out the image data while writing it in the image memory and display it in a loop-back manner. In such a configuration, if the decoration image data and the captured image data are combined immediately before writing the image data to the image memory, loopback display in a state where the decoration image is combined becomes possible. However, for that purpose, for example, a FIFO type VRAM is required as the image memory. Further, in order to avoid a restriction that reading for display on a monitor cannot be performed while image data is being read to the print control unit, writing and reading, and furthermore, reading of image data to the print control unit when printing is performed. A high-speed operation that can perform reading at substantially the same time is required including the image memory control unit. And such a VRAM
Also, the image memory control unit increases the cost of the system.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and has been made in consideration of a loop in which a decorative image is synthesized without using an image memory control unit or a VRAM such as a FIFO which requires high speed. An object of the present invention is to provide an image processing device capable of performing back display.

[0008]

According to a first aspect of the present invention, there is provided an image processing apparatus comprising: decoding means for inputting an analog video signal and converting it into digital image data; A scaling means for converting and outputting the image data, an image memory for storing the image data output from the scaling means, and an inverse scaling for performing an inverse size conversion on the image data read from the image memory and outputting the result. Means, image data supplied to the scaling means and image data output from the inverse scaling means, and switch means for selecting and outputting one of the image data; and image data supplied to the scaling means to the switch means. For converting the image data output from the loop-back means and the switch means into an analog video signal. And an encoding means for performing the conversion.

According to a second aspect of the present invention, an image processing apparatus comprises:
The invention according to claim 1, further comprising a decoration image memory for storing decoration image data, wherein the scaling means is supplied with image data obtained by combining the decoration image data with the image data converted by the decoding means. And According to a third aspect of the present invention, in the image processing apparatus according to the first or second aspect, the size conversion by the scaling unit is performed to convert the pixel size into a pixel size having a ratio of approximately 1: 1.

According to a fourth aspect of the present invention, there is provided an image processing apparatus comprising:
According to the present invention, at least the image data supplied to the scaling means and the image data output from the inverse scaling means are processed at a clock rate of 4 fsc. According to a fifth aspect of the present invention, in the image processing apparatus according to the first to fourth aspects, an on-screen display for synthesizing display data for performing on-screen display with image data output from the switch means. With means,
The encoding means is supplied with image data from the on-screen display means.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an example in which an image processing apparatus according to an embodiment of the present invention is applied to a photo printing system, and shows a schematic configuration diagram thereof. 1 is a CPU that controls the entire system, 2 is a camera using a color CCD, and the camera 2 outputs an analog video signal (NTSC) of a captured image. Reference numeral 3 denotes a decoder as a decoding means for inputting an analog video signal and converting it into digital image data.
(= 14.3 MHz)
Each pixel of the digitally converted image data has a dot shape corresponding to 4 fsc. In this case, the aspect ratio (horizontal: vertical) of one pixel is approximately 6: 7.

Reference numeral 4 denotes an image for decorating an image captured by the camera 2, an overlay memory as a decorative image memory storing a plurality of decorative image data composed of pixel information corresponding to 4fsc, and 5 an overlay memory 4. The overlay circuit selectively reads out one piece of decorative image data from the image data, and combines the read decorative image data with the image data from the decoder 3 and outputs the combined image data. The image data from the decoder 3 is selected only for the portion of the image data indicating the transmission in the decoration image data based on the priority of the decoration image data.

Reference numeral 6 denotes a reduction filter as a scaling means for converting the image data output from the overlay circuit 5 into a predetermined size. Of the image data supplied together with the band limitation, data of 7 pixels in the horizontal direction is converted into 6 pixels. To Accordingly, each pixel of the image data has a square rate (= 12.2) in which the aspect ratio of one pixel is approximately 1: 1.
7 MHz). Note that the dot shape corresponds to the square rate, the processing in the reduction filter 6 is performed at a clock rate of 4 fsc, and the image data is also transferred at this rate.

Reference numeral 7 denotes a clock rate conversion circuit for adjusting the supply timing of the image data to a processing clock in an image memory control circuit and an image memory, which will be described later. 8 denotes an image memory for storing the image data converted by the reduction filter 6; Denotes an image memory control circuit for controlling writing and reading of image data to and from the image memory 8. In the clock rate conversion circuit 7, for example, the processing clock in the image memory 8, the image memory control circuit 9, and the subsequent printer is 16
In the case of MHz, the image data is supplied to the image memory control circuit 9 in synchronization with the clock of 16 MHz.
Also, at this time, the processing is performed based on the high-speed clock, and the aspect ratio of each pixel is almost the same.
It remains 1: 1.

10 is a high-speed clock (for example, 16 MHz)
z) a state before the image data supplied from the image memory control circuit 9 is clock-converted by the clock rate conversion circuit 7, that is, a clock rate for transferring the image data at a speed based on a processing clock of 4 fsc. Inverting circuit, 11
Is an enlargement filter as an inverse scaling means for performing size conversion opposite to that of the reduction filter 6, and interpolates and expands data of six pixels in the horizontal direction in image data output from the clock rate inverse conversion circuit 10 to seven pixels. As a result, each pixel of the image data changes from a dot shape corresponding to a square rate with an aspect ratio of approximately 1: 1 to a dot shape corresponding to a 4 fsc rate with an aspect ratio (horizontal: vertical) of 6: 7. The processing clock in the enlargement filter 11 at this time is 4 fsc.

A switch 12 for inputting the same image data as the image data supplied to the reduction filter 6 and the image data output from the enlargement filter 11 and selecting and outputting one of them under the control of the CPU 1;
Reference numeral 13 denotes a loopback line as a loopback means for inputting the same image data as the image data supplied to the reduction filter 6 to the switch 12.

Reference numeral 14 denotes an on-screen display circuit (OSD circuit) for superimposing font data for an on-screen display for displaying operation guide display and item setting on a display under control of the CPU 1 and image data from the switch 12. ) And 15 are OSD circuits 14
An encoder 16 converts the image data from the encoder into an analog video signal and outputs the analog video signal. Reference numeral 16 denotes a display for displaying a monitor on the basis of the video signal from the encoder 15.

Reference numeral 17 denotes a printer for printing an image based on the image data read from the image memory 8 by the image memory control circuit 9. A printer control unit for controlling the printing operation, an actual printing operation, and paper feeding / discharging. And a printing mechanism for performing such operations. In such a system, a video signal of an image captured by the camera 2 is digitally converted by the decoder 3 and input to the overlay circuit 5 as image data. The overlay circuit 5 combines image data of one decorative image selected from a plurality of decorative images stored in the overlay memory 4 with image data input from the decoder 3 by an operation unit (not shown). Output. In the synthesis, the decoration image data is prioritized, and the decoration image is overwritten on the captured image. When the decorative image is not selected, the image data from the decoder 3 is output as it is.

The image data output from the overlay circuit 5 is supplied to the reduction filter 6, but is also supplied to the switch 12 via the loopback line 13. The switch 12 selectively outputs the image data from the loopback line 13 under the control of the CPU 1 when the mode is not the display mode of the captured image. Then, the CPU 1 combines the display data such as the operation guide and the condition setting with the image data from the switch 12 and outputs the combined data with the OSD circuit 14 as appropriate based on the operation status. The image data output from the OSD circuit 14 is converted into an analog video signal suitable for the display 16 by the encoder 15 and supplied to the display 16. Then, on the display 16, an image obtained by combining the image captured by the camera 2 and the decoration image is displayed, and new images are sequentially taken in from the camera 2.
Is displayed as a moving image. That is, the loopback display of the image captured by the camera 2 is performed in a state where the decorative image is synthesized, and the image can be captured by selecting a state in which a preferable image is captured together with the synthetic state with the decorative image.

When an image is instructed by operating an operation unit (not shown) while an appropriate image is being captured and displayed, the CPU 1 sends the image data from the overlay circuit 5 to the image memory control circuit 9. It is stored in the image memory 8. That is, the image data output from the overlay circuit 5 has a dot shape corresponding to a square rate with an aspect ratio of one pixel of approximately 1: 1 by reducing the number of pixels in the horizontal direction to 6/7 by the reduction filter 6. Thus, the size is converted and output to the clock rate conversion circuit 7. Image data is output from the clock rate conversion circuit 7 at a speed corresponding to the processing clock rate of the image memory control circuit 9, and the image memory control circuit 9 stores the input image data in the image memory 8. During this time, on the display 16, the image data from the loopback line 13 is
2 and the loop-back display is performed until the storage of one frame (frame) of image data is completed.

When the monitor display of the captured image is instructed by operating the operation unit (not shown), the CPU
1 causes the image memory control circuit 9 to read the image data stored in the image memory 8, and further causes the switch 12 to selectively output the image data from the enlargement filter 11.
That is, the image memory control circuit 9 sequentially reads out the image data stored at the predetermined position and outputs it to the clock rate reverse conversion circuit 10. At this time, the image data is, for example, 16M
The clock rate is converted in accordance with the processing clock of 4 fsc before being converted by the clock rate conversion circuit 7 in the clock rate reverse conversion circuit 10. Furthermore, clock rate reverse conversion circuit 1
The image data output from 0 is input to the enlargement filter 11, and the enlargement filter 11 reduces the number of pixels in the horizontal direction to 7 /.
By setting the pixel size to 6, the size is converted so that the aspect ratio (horizontal: vertical) of one pixel becomes a dot shape corresponding to a 4 fsc rate of approximately 6: 7, and is output to the switch 12 based on a processing clock of 4 fsc. . The switch 12 is controlled to selectively output the image data from the enlargement filter 11, and outputs the captured image data to the OSD circuit 14 to be displayed in the image memory 8.

The OSD circuit 14 appropriately superimposes OSD display data under the control of the CPU 1, and the encoder 15 converts the image data into an analog video signal. At this time, since the processing clock of the encoder 15 is also 4 fsc, the analog conversion to the video signal is efficiently performed. Then, the video signal is supplied to the display 16, and the captured image is displayed on a monitor in a still image state.

Here, when re-capturing the image,
Under the control of the CPU 1, a loop-back display state is set again. When an image is instructed by operating an operation unit (not shown) in a state where an appropriate image is captured, the CPU
1 reads out the image data stored in the image memory 8 by the image memory control circuit 9 and supplies the image data to the printer 17.
Then, the printer 17 executes image printing based on the supplied image data. At this time, since the aspect ratio of the image data read from the image memory 8 is almost 1: 1, the printer 17 does not perform the dot shape conversion process, and performs image printing as it is based on the supplied image data. Can be performed.

In this embodiment, one image is captured and stored in the image memory. By changing the filter coefficient of the reduction filter, a plurality of reduced images are included in one frame. You may do so. Even in such a case, printing by the printer 17 can be executed as it is without performing a dot shape conversion process based on the supplied image data.

Further, in the present embodiment, a loopback display of an image in which a decorative image is synthesized is possible, but the present invention is not limited to this. For example, between the decoder 3 and the reduction filter 6 or immediately before the OSD circuit 14 , Image tones (full color,
Even in the case where a color tone adjustment circuit for changing the color tone is provided, the image whose color tone has been adjusted by the color tone adjustment circuit can be displayed in a loop-back manner, so that the adjusted image can be easily confirmed.

[0026]

According to the present invention, as is apparent from the above description, after converting an analog video signal into digital image data, the image data before being input to the reduction filter is looped back by a loop-back line. Loopback display is realized. Further, the image data is stored in the image memory after the reduction filter. Thus, digital decoration image data can be easily combined with captured image data, and an image in which the decoration image is combined can be looped back. Therefore, the state in which the decorative image has been synthesized can be confirmed in the state of the loop-back display, which is a moving image display before capture, and the usability of the photo printing system is improved.

Further, since it is not necessary to read out the image data taken into the image memory for the loopback display, there is no need for a FIFO type VRAM or a high-speed writable / readable image memory. Therefore, in order to realize a loopback display of an image synthesized with a decorative image,
This can prevent a significant cost increase. Further, during the loopback display, no readout processing for display is performed in the image memory, and there is no restriction on reading out image data to be printed on the printer, so that the degree of freedom in system construction is increased.

Since the image memory stores dot-shaped image data in which the aspect ratio of one pixel is approximately 1: 1, it is easy to perform image processing and printing processing on the image data read from the image memory. Can be. For example, printing by a printer can be performed as it is in accordance with image data supplied without performing dot shape conversion processing.

In this embodiment, the decoder, overlay circuit, switch, reduction filter, enlargement filter, OSD circuit, and encoder are all digital systems processed by the same processing clock of 4 fsc.
C conversion can also be easily performed. One (or several) ICs
With this configuration, a separate component (for example, an analog switch or the like) is not required, which can contribute to a reduction in the number of components and cost.

[0030]

[Brief description of the drawings]

[0031]

FIG. 1 is a schematic configuration diagram of a photo printing system to which an image processing device according to an embodiment of the present invention is applied.

[0032]

FIG. 2 is a schematic configuration diagram of a conventional image printing system.

[0033]

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 CPU 2 Camera 3 Decoder (decoding means) 4 Overlay memory (decorative image memory) 5 Overlay circuit 6 Reduction filter (scaling means) 7 Clock rate conversion circuit 8 Image memory 9 Image memory control circuit 10 Clock rate reverse conversion circuit 11 Enlargement filter (Inverse scaling means) 12 Switch (switch means) 13 Loopback line (Loopback means) 14 OSD circuit (On-screen display means) 15 Encoder (Encoding means) 16 Display 17 Printer

Claims (5)

[Claims] A decoding means for inputting an analog video signal and converting the converted image data into digital image data; a scaling means for converting the converted image data into a predetermined size for output; and an image output from the scaling means. An image memory for storing data, an inverse scaling unit for performing an inverse size conversion of the image data read from the image memory and outputting the same, and an image data supplied to the scaling unit and output from the inverse scaling unit Switch means for inputting image data to be input and selecting and outputting one of them, loopback means for inputting image data supplied to the scaling means to the switch means, and analog image data output from the switch means. Encoding means for converting the video signal into a video signal. Equipment. 2. The image processing apparatus according to claim 1, further comprising a decoration image memory for storing decoration image data, wherein the scaling means is supplied with image data obtained by combining the decoration image data with the image data converted by the decoding means. Item 2. The image processing apparatus according to Item 1. 3. The image processing apparatus according to claim 1, wherein the size conversion in the scaling means converts the pixel size to a pixel size having an aspect ratio of about 1: 1. 4. The image processing apparatus according to claim 1, wherein at least the image data supplied to the scaling means and the image data output from the inverse scaling means are processed at a clock rate of 4 fsc. 5. An on-screen display means for synthesizing display data for performing on-screen display with image data output from the switch means, and the encoding means is supplied with image data from the on-screen display means. 5. The image processing apparatus according to claim 1, wherein: