JPH11122545A - Solid-state image pickup device for detecting motion - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state image pickup device for detecting motion that detects a mobile body based on a color component of an incident light with a simple configuration and high precision without the need for external image processing. SOLUTION: Green, red and blue group pixels 101G, 101R, 101B are arranged in a matrix to a light receiving section of a motion detection solid-state image pickup device 100 to detect each color component of the incident light. An electric signal from a pixel of a specific row is transferred to vertical read lines 102a,... for each column in a prescribed timing by a vertical scanning circuit 106 and further transferred to a horizontal read line 112 by a horizontal scanning circuit 113. Each of the vertical read line 192a,... is provided with a different value detection circuit 107 that stores an electric signal from the corresponding pixels 101R,... in a prescribed timing as an electric signal of a just preceding frame, compares the electric signal with an electric signal corresponding to a current frame outputted from the same pixels 101R,... in a succeeding prescribed timing and provides an output of a different value signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[Detailed description of the invention]

[0002]

2. Description of the Related Art Conventionally, image data is obtained from a large number of pixels arranged in a matrix, this image data is stored as a value in the immediately preceding frame, and then a value in the current frame is detected. There is a known motion detection image processing apparatus that compares objects with each other to detect a subject (moving object).

FIG. 10 shows a conventional motion detection image processing apparatus 300. This motion detection image processing apparatus 300 includes:
A solid-state imaging device 301 and an AD conversion circuit 302 that converts a video signal (analog signal) representing image data obtained by the solid-state imaging device 301 into a digital signal.
An image memory (first image memory) 303 and an image memory (second image memory) 304 for storing digital signals from the AD conversion circuit 302;
The image processing circuit 305 obtains image data representing motion by comparing digital image data stored in the image data 3304 with each other.

That is, the motion detection image processing apparatus 300
First, after the video signal (analog signal) in the first frame obtained by the solid-state imaging device 301 is converted into a digital signal by the AD conversion circuit 302, the first image is converted into a video signal in the immediately preceding frame. It is stored in the memory 303. Next, the video signal (analog signal) obtained by the solid-state imaging device 301 in the second frame following the first frame (the immediately preceding frame) is
After being converted into a digital signal at 02, it is stored in the second image memory 304 as a video signal of the current frame.

Then, the digital signal stored in the first image memory 303 by the image processing circuit 305 and the second
The magnitude of the digital signal stored in the image memory 304 is compared for each pixel, and the first frame (the immediately preceding frame) and the second frame (the current frame) are compared.
Pixels in which the difference between the compared digital signals is equal to or greater than a predetermined value are detected.

In this case, the first frame and the second frame are continuous, and the digital signal stored in the first image memory 303 is the luminance of each pixel of the solid-state imaging device 301 in the first frame. Signal corresponding to the second
The digital signal stored in the image memory 304 corresponds to the luminance signal of each pixel of the solid-state imaging device 301 in the second frame.

Therefore, by comparing these two digital signals, the difference between the luminance signals between two consecutive frames (the immediately preceding frame and the current frame) can be detected, and only the moving object can be detected from the subject. . Then, by repeating the above operation, a continuously moving subject (moving object)
Can be detected.

[0008]

However, when motion detection of a moving object is performed using the conventional motion detection image processing apparatus 300 (FIG. 10), a video signal (analog signal) is output from the solid-state imaging device 301. Later, the AD conversion circuit 3
02 and converts it into a digital signal.
The digital signals are stored in the second image memories 303 and 304, and the image processing circuit 305 uses the stored digital signals to detect a moving object (comparison of the digital signals in the immediately preceding frame and the current frame). 2), the peripheral circuits of the solid-state imaging device 301 are complicated, and the entire image processing device 300 for motion detection has a problem that it becomes expensive.

A signal corresponding to incident light generated at each pixel (not shown) of the solid-state imaging device 301 is an analog signal, and thereafter, the analog-to-digital conversion circuit 302
Output, so it was susceptible to noise. Further, in the above-described conventional motion detection image processing device 300, the effective range of the video signal (analog signal),
That is, the dynamic range is adjusted by the AD conversion circuit 30 described above.
Limited by 2 inputs. Thus, the AD conversion circuit 302
Since the input dynamic range is narrower than the dynamic range of the solid-state imaging device 301, there is a problem that the wide dynamic range of the solid-state imaging device 301 cannot be used effectively in the process of detecting a moving object.

In order to avoid the above-mentioned problems, a memory for storing the video signal of the immediately preceding frame and the current frame is provided for each pixel of the solid-state imaging device 301,
Further, it is conceivable to provide a circuit for comparing the video signal stored in the memory for each pixel to generate a signal representing a moving object for each pixel, but using such a method,
The structure of each pixel becomes complicated, causing a decrease in the aperture ratio of the solid-state imaging device 301 and a decrease in resolution, and there is a problem that it is impossible to respond to the increase in the number of pixels.

Further, if the motion of a moving object is detected only based on the change in luminance between frames in each pixel, it is difficult to detect the motion of the moving object if the motion of the moving object does not appear as a change in luminance. become. This is because, for example, when a bright subject (moving body) moves in a bright place or when a dark subject (moving body) moves in a dark place, even if the moving body is recognized as an image, the luminance of each pixel does not change so much. It depends.

In such a case, if a subject (moving object) is recognized as a color image and its change is detected for each hue in the color image, a bright subject moves in a bright place or a dark place in a dark place. Even when the subject moves, the movement can be detected by recognizing the change in the color of the subject (moving object) and the background. However,
If a color image is obtained and motion detection is performed based on this image data, three types of pixels constituting the color system (for example, “red (R)” and “green (G )), “Blue (B)”, and “cyan (C)”, “magenta (M)”, “yellow (Y)” for complementary colors.
, One frame of image data must be held, and the capacity of the image memory is reduced by two to that in the case where the motion detection of a moving object is performed based solely on a change in luminance (FIG. 10). This requires about three times, and further complicates the image processing apparatus for motion detection, resulting in an increase in cost.

The present invention has been made in view of the above-mentioned problems, and does not require external image processing in detecting the intensity of each color component of the incident light and detecting the movement of a moving object more precisely. It is another object of the present invention to provide a motion detection solid-state imaging device having a simple configuration.

[0014]

In order to achieve the above object, according to the first aspect of the present invention, at least an electric signal corresponding to at least three types of color components constituting a predetermined color system is output. A solid-state imaging device in which a plurality of kinds of pixels are arranged in a matrix in a predetermined arrangement pattern, wherein a plurality of vertical read lines provided for each column of the pixels arranged in the matrix; A vertical scanning circuit for selecting a specific row of pixels and transferring an electric signal from the pixel to the vertical readout line at a certain timing, and being arranged on the vertical readout line and outputting from a specific pixel at a certain timing; The stored electric signal is stored as an electric signal for the immediately preceding frame, and the stored electric signal and the electric signal for the current frame output from the pixel at the next fixed timing are stored. And a signal transfer circuit that outputs a signal representing the result of the comparison and a signal transfer circuit that sequentially transfers the signal representing the result of the comparison output from the plurality of vertical read lines to a horizontal read line. It is provided with.

According to a second aspect of the present invention, the three types of pixels constituting the predetermined color system are red, green, and blue pixels constituting an RGB color system. It is. According to a third aspect of the present invention, the three types of pixels constituting the predetermined color system are cyan, magenta, and yellow pixels constituting a CMY color system.

According to a fourth aspect of the present invention, a motion judging circuit for judging the motion of a moving object is connected to the horizontal read line in accordance with the state of generation of a signal representing the result of the comparison. .

(Operation) According to the first aspect of the present invention,
For three types of electric signals output from each pixel corresponding to three types of color components constituting a predetermined color system, an electric signal for the immediately preceding frame and an electric signal for the current frame are obtained. Since these values are compared by signal comparison means provided for each vertical read line,
An outlier signal indicating the motion of the moving object can be easily generated for each color component. Further, since the different value signals generated for each of the three color components are binarized and transmitted from the vertical readout line to the output terminal via the horizontal readout line, when the signal passes through the horizontal readout line, Even if noise is added to the binarized different-value signal, the influence of noise can be reduced as compared with the case of an analog signal.

According to the second aspect of the present invention, RG
According to the three color components of the B color system (primary color system), it is possible to generate a different value signal representing the motion of the moving object for each color component. According to the third aspect of the present invention, it is possible to generate a different value signal representing the motion of a moving object for each color component according to three kinds of color components of the CMY color system (complementary color system). it can.
According to the fourth aspect of the present invention, a change occurs in any of the electrical signals corresponding to the three types of color components output from the pixels corresponding to the three types of color components. The movement of the moving object can be detected based on the outlier signal, that is, by obtaining a change in the electric signal for each color component.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. The first embodiment corresponds to claims 1 and 2.

First, the device structure of the light receiving unit of the solid state imaging device 100 for motion detection according to the first embodiment will be described with reference to FIGS.
This will be described with reference to FIG. The color system of the solid-state imaging device 100 for motion detection according to the first embodiment is an RGB color system, and three types of pixels (a red-based pixel 101R, a green-based pixel, The pixels 101G and the blue pixels 101B) are arranged in a matrix in a predetermined arrangement pattern. FIG. 1 shows four pixels 101G,
101G, 101R and 101B are shown.

That is, in the color system of the solid-state imaging device 100 for motion detection shown in FIG.
01G, 101G, one red pixel 101R, and one blue pixel 101B are arranged. In the illustrated example, two pixels 101 at the upper left and lower left of the four pixels 101 are shown.
Green transmission filters 111G and 111G are formed on the incident surface of G and 101G (upper part in FIG. 3), and the upper right pixel 101R is formed.
A red transmission filter 111R is formed on the incident surface of the pixel 101B, and a blue transmission filter 111B is formed on the incident surface of the lower right pixel 101B. These four pixels 101G, 101
G, 101R and 101B are the color filters 111
The structures other than G, 111G, 111R, and 111B are identical to each other.
The device structure of the pixel (upper right pixel in FIG. 1) will be described.

As shown in FIG. 1, a pixel (red pixel) 101R of the solid-state imaging device 100 for motion detection includes a photodiode (PD: photoelectric conversion unit) 21 for generating signal charges corresponding to incident light, A junction field effect transistor (amplifying transistor QA; hereinafter abbreviated as “JFET”) 22 that outputs an electric signal (Vout) in accordance with the signal charge supplied to the gate region 22A, and a photodiode 21 that generates and outputs the electric signal (Vout). The accumulated signal charges are transferred to the gate region 22.
A P-type transfer MOS transistor (QT) 23 for supplying (transferring) to A, and a P-type resetting MOS transistor for discharging the signal charge supplied (transferred) to the gate region 22A via the reset drain 15. MOS transistor (Q
P) 24 and a pixel separating MOS transistor (QX) 25 for selectively connecting the source region 22S of the JFET 22 and the vertical read line 102b are formed.

As shown in FIG. 3, the photodiode 21 includes a P-type impurity diffusion layer (charge storage region) 121 formed in the N-type semiconductor layer 12 on the semiconductor substrate 11, and
A high-concentration N-type impurity diffusion layer 122 is formed above the P-type impurity diffusion layer 121.
In the photodiode 21, the signal charges generated according to the incident light are transferred to the P-type impurity diffusion layer (charge storage region) 12.
1 is stored.

In the JFET 22, as shown in FIGS. 2 and 3, the P-type impurity diffusion layer 124 formed in the N-type semiconductor layer 12 forms a gate (gate region) 22A, and the N-type impurity diffusion layer 125 Constitutes the source 22S, the N-type impurity diffusion layer 126 constitutes a channel, and the N-type semiconductor layer 12
Constitute the drain. JF configured in this way
The ET 22 is supplied (transferred) with signal charges generated and accumulated in the photodiode 21 in the gate region 22A via the transfer MOS transistor 23 shown in FIG. An electric signal Vout corresponding to the (transferred) signal charge is output from the source 22S.

As shown in FIGS. 2 and 3, the gate region 22A of the JFET 22 has a channel region (12).
6) is formed so as to be sandwiched from above and below in the figure, and has a structure in which the gain of the source follower operation can be increased and the variation in gain can be suppressed. Also, reset MOS
Transistor 24 is a gate region 22A of JFET 22
The electric charge accumulated in the gate region 22A is reset (set to the read level VRD) by setting the potential of the reset drain 15 and the reset drain 15 to the same potential.

The color filter 111 of the pixel 101R
R is formed above the photodiode 21 as shown in FIG.
11R is for causing the photodiode 21 to generate signal charges corresponding to the intensity of red light. FIG.
3, reference numeral 13 denotes a wiring for connecting the source 22S of the JFET 22 and the main electrode of the pixel separating MOS transistor QX, 102a denotes a vertical read line, and 103a, 1
03b is a clock line for a transfer gate, 104a, 1
04b is a clock line for a reset gate, 105
Reference numerals a and 105b denote clock lines connected to the gates of the pixel separating MOS transistors QX.

FIG. 4 is a circuit diagram schematically showing the above-described solid-state imaging device 100 for motion detection. As shown in this figure, pixels 101G, 101 arranged in a matrix
G, 101R, and 101B are connected to the vertical read lines 102a and 102b for each column.
The vertical scanning circuit 106 is connected via 103b, 104a, 104b, 105a, 105b. The pixels 101G, 101G, 1
01R, 101B, the green component and the red component of the incident light,
Three types of electric signals corresponding to the blue component are transferred to the corresponding vertical read lines 102a and 102b.

The vertical read lines 102a, 102
A different value detection circuit 107 is connected to b. The output of the different value detection circuit 107 is connected to a corresponding bit register of the shift register (signal transfer circuit) 113 for each column. This outlier detection circuit 107 outputs a signal to each pixel 101G, 101G, 101 at a certain timing.
R, 101B to each vertical read line 102a, 10b.
The electric signals corresponding to the respective color components output to the pixels 101G and 10G are output as electric signals for the immediately preceding frame.
1G, 101R, and 101B, and store the same pixel 10 at the next fixed timing with the stored electric signal.
The electric signals for the current frame output from the 1G, 101G, 101R, and 101B are compared with each other, and signals (different value signals) representing the results of the comparison are output from the output side at different timings.

The different value signal from the different value detection circuit 107 is stored in a corresponding register of the shift register 113, and thereafter, by the operation of the shift register 113,
The data is sequentially transferred to the horizontal read line 112, and then output from the output terminal VO. That is, the output of the different value detection circuit 107 in the first column (on the vertical read line 102a) is connected to the data input terminal Q1 of the first bit register of the shift register 113, and the second column (in the vertical read line 102a). 10
2b) is output from the data input terminal Q of the second bit register of the shift register 113.
2 are connected.

The load signal input terminal LD of the shift register 113 is connected to a node 111 on the side of a drive pulse generating circuit (not shown) via a clock line 111a. Then, according to the level of the drive pulse φLD input to the load signal input terminal LD, the shift register 1
Reference numeral 13 stores the electrical signals from the different value detection circuit 107 input to the data input terminals Q1 and Q2 in corresponding registers (not shown). The output terminal of the shift register 113 is connected to the output terminal VO via the horizontal read line 112.

In this case, what is read out to the horizontal read-out line 112 is an electric signal corresponding to each of the pixels 101G, 101G, 101R, and 101B output from the different value detection circuit 107. Is a different value signal corresponding to a change in the intensity of the color component (green, red, blue). An electric signal (different value signal) indicating the degree of change in the intensity of each color component (green, red, blue) of the incident light is transmitted to the shift register 1.
Thirteen clock terminals (not shown) are sequentially output from the output terminal VO at the rising timing.

Next, each pixel 101G, 101G, 101
R, 101B, and vertical read line 102
a, 102b, clock lines 103a, 103b,...
The connection relationship with the like will be described in detail with reference to FIG.

Each of the pixels 101G, 101G, 101R, 1
01B, each color filter (111G, 11G in FIG. 1)
1G, 111R, 111B), a signal (signal charge) corresponding to the light component that has reached the photodiode PD is supplied to the gate (control region) of the amplifying transistor QA, and the current is amplified by the source follower operation. . The current-amplified electric signal is thereafter read out to the corresponding vertical readout lines 102a and 102b at a predetermined timing.

In this case, the source of each amplifying transistor QA is connected via a pixel separating MOS transistor QX.
Vertical readout line 1 for each column arranged in a matrix
02a or 102b. The power supply voltage VD (positive) is applied to the drain of each amplifying transistor QA and the cathode side of the photodiode PD.

One main electrode (source or drain) of the transfer MOS transistor QT is connected to the anode side of the photodiode PD and the gate (control region) of the amplification transistor QA. The transfer gate of the transfer MOS transistor QT is commonly connected to the clock lines 103a and 103b for each row of the pixels 101G, 101G, 101R and 101B arranged in a matrix, and connected to the clock lines 103a and 103b. Drive pulse φT transmitted from the vertical scanning circuit 106
When G1 and φTG2 are applied, the drive pulse φTG
The transfer MOS transistors QT operate sequentially for each row in accordance with the levels of 1, TG2.

The power supply voltage VRD is supplied to the drains of the reset MOS transistors QP in the respective pixels 101G and 101G.
1G, 101R, and 101B are commonly connected, and the voltage VRD is applied. The gate of the reset MOS transistor QP is commonly connected to the clock lines 104a and 104b connected to the vertical scanning circuit 106, and one main electrode (source) is connected to one main electrode of the transfer MOS transistor QT. (Source) and shared.

When the drive pulses φRG1 and φRG2 are given from the vertical scanning circuit 106 to the gate of the reset MOS transistor QP, the reset M transistor
The OS transistor QP is driven by the drive pulses φRG1, φRG
It operates according to the level of RG2.
The gates of the pixel separating MOS transistors QX are connected to the pixels 101G, 101G, 1 arranged in a matrix.
01R and 101B for each row.
a, 105b and the vertical scanning circuit 106
The pixel separating MOS transistors QX are sequentially operated for each row in accordance with the levels of the driving pulses φPX1 and φPX2.

Also, the vertical read lines 102a, 1
02b, as shown in the lower part of FIG. 4, a reset switch MOS transistor (N-type) QRSV
, QRSV2 and each constant current source 117a, 1
17b is connected. In this case, the sources of the reset switch MOS transistors QRSV1 and QRSV2 are grounded, and the constant current sources 117a and 117b are supplied with the power supply voltage VC (negative).

The gates of the reset switch MOS transistors QRSV1 and QRSV2 are connected to a node 16 on the side of a drive pulse generating circuit (not shown) via a clock line 116a. These reset switch MOS transistors QRSV1 and QRSV are provided in accordance with the level of the drive pulse φRSV supplied via the clock line 116a.
SV2 operates, and each vertical read line 102a, 102
b is reset.

Next, the vertical read lines 102a, 102a
Outlier detection circuit (signal comparison circuit) arranged in the middle of 2b
Details of 107 will be described. Note that here, the different value detection circuit 107 connected to the vertical read line 102a side
(FIG. 5) will be described as an example. As shown in FIG. 5, the vertical read line 102a is branched into two read lines 102a-1 and 102a-2 at a node n1, and the different value detection circuit 1 is provided on the branched vertical read line 102a.
07 is arranged.

The read line 10 on the downstream side of the switching MOS transistor QR of the vertical read line 102a
One terminal of the first signal storage capacitor CR is connected to 2a-1. One terminal of a second signal storage capacitor CS is connected to a read line 102a-2 downstream of the switching MOS transistor QS of the vertical read line 102a.

The read lines 102a-1 and 102a-2 on the side of the vertical read line 102a are connected to two input terminals of the different value detector XA, respectively. As shown in FIG. 4, the gate of the switching MOS transistor QR is connected to a node 10 on the side of a drive pulse generation circuit (charge storage control means) (not shown) via a clock line 108a.
8 and the switching MOS transistor QS
Is connected to a node 109 on the side of a drive pulse generating circuit (not shown) via a clock line 109a. The switching MOS transistor QR and the switching MOS transistor QS are driven by driving pulses φTR and φTS supplied from a driving pulse generating circuit (not shown).
Operates according to the level of

In the first embodiment, the two different value detection circuits 107, 107 are connected to the respective vertical read lines 102a, 1
02b corresponding to pixels 101G, 101G, 101R,
An electric signal corresponding to the color component of the incident light output from the first and second signal storage capacitors C
It is stored in R and CS. Then, the outlier detection circuit 107,
At 107, when the electric signals stored in the first and second signal storage capacitors CR and CS are different from each other, a logical high level or low level signal (different value signal)
Is output from the outlier detector XA.

In this case, the electric signals stored in the first and second signal storage capacitors CR and CS and compared by the different value detector XA are the electric signals of the same color component output from the same pixel. Which is an electric signal generated in different frames. Outlier detector XA of outlier detector 107
Are two voltage comparators AP1, AP, as shown in FIG.
2 and an OR operator OR.

The voltage comparator AP1 has its non-inverting input terminal connected to the readout line 102a-1 and one terminal of the first signal storage capacitor CR connected thereto, and has its inverting input terminal connected to the readout line 102a-1. Readout line 102a-2
And a second signal storage capacitor CS connected thereto.
Is connected to one of the terminals. Also, the voltage comparator AP2
Has a non-inverting input terminal connected to the readout line 102a-2 and one terminal of the second signal storage capacitor CS connected thereto, and an inverting input terminal connected to the readout line 102a-1 and the readout line 102a-1. One terminal of the connected first signal storage capacitor CR is connected.

Then, the two voltage comparators AP1 and AP2
Are connected to two input terminals of an OR operator OR, and the output of the OR operator OR is connected to the different value detection circuit 1
07 output. FIG. 6 is a characteristic diagram showing an example of the input / output characteristics of the voltage comparators AP1 and AP2 forming the outlier detector XA.

In FIG. 6, the voltage ΔH is a threshold voltage, which is set to be sufficiently larger than the magnitude of a normal random noise component. V1 is a voltage comparator AP
1, the input voltage value input to the non-inverting input terminal of AP2, V2 is the input voltage value input to the inverting input terminal,
out indicates an output voltage value. In this case, (V1-V2)
Is greater than the threshold voltage ΔH, the output Vout is inverted (inverted from low level to high level).

Next, the operation of the solid-state imaging device 100 for motion detection having the above configuration will be described with reference to a timing chart shown in FIG. FIG. 7 shows four pixels 10
1G, 101G, 101R, and 101B, the pixels in the same column (the pixels 101 connected to the vertical readout line 101a).
G, 101G, or the electric signals output from the pixels 101R, 101B connected to the vertical readout line 102b are successively output by the different value detection circuits 107, 107 arranged on the respective vertical readout lines 102a, 102b. This is an example in which the comparison is made between the frames.

Here, the period t10 to t15 of the (N-1) th frame or the Nth frame is the pixel 101G of the first row.
(Upper left of FIG. 4) and the read operation of the pixel 101R, and periods t20 to t25 show the read operation of the pixel 101G (lower left of FIG. 4) and the pixel 101B of the second row, respectively. In this case, the values of the electric signal appearing on the vertical read line 102a in the immediately preceding frame (the (N-1) th frame) and the current frame (the Nth frame) are set in the vertical read line 10a.
The values of the previous frame and the current frame of the electric signal appearing on the vertical read line 102b are compared by the different value detection circuit 107 disposed on the vertical read line 102a. Be compared.

As a result, the outlier detection circuit 107 for the vertical readout line 102a can detect the motion of the subject (moving object) based on the change in the intensity of the green component of the incident light. Also, the different value detection circuit 107 of the vertical read line 102b
Accordingly, the motion of the subject (moving object) can be detected based on the change in intensity of each of the red component and the blue component of the incident light. Hereinafter, a description will be given from the time when the period t10 of the Nth frame in the timing chart of FIG. 7 is reached. Note that the read operation in the (N-1) th frame is the same as the read operation in the Nth frame described below, and the description of the operation will be omitted.

First, in the period t10 to t15, the first
A read operation is performed on the pixels 101G (upper left in FIG. 4) and the pixels 101R in the row. Period t of Nth frame
Before reaching 10 (at the end of the period t25 of the (N-1) th frame), the driving pulses φTG1 and TG2 are both held at a high level, the driving pulses φPX1 and φPX2 are both held at a low level, and the driving pulses φRG1 and φRG2 are Both are held at a high level. Also, the driving pulse φRS
V, φTR, and φTS are kept at a low level, and the drive pulse φLD is kept at a low level.

As described above, before the period t10, since the drive pulses φTG1 and φTG2 are at the high level, the transfer MO
The S transistor QT is turned off, and the driving pulse φRG
1, since φRG2 is at a high level, the resetting MOS transistor QP is off. Therefore, although the gate (control region) of the amplifying transistor QA is in a floating state, due to the effect of the parasitic capacitance, the amplifying transistor QA has already been connected via each transfer MOS transistor QT in the immediately preceding N-1 frame. The charge (first signal charge) corresponding to the color component of the incident light generated by each photodiode PD transferred to the gate is transferred to the transfer MOS.
Even after the transistor QT is turned off, the state is maintained at the gate of each amplifying transistor QA. Thus, the amplifying transistor QA outputs an electric signal Vout corresponding to the gate voltage by the source follower operation until the charge stored in the gate is reset.

After the transfer MOS transistor QT is turned off, each photodiode PD
Charges (second signal charges) corresponding to the color components of 01G, 101G, 101R, and 101B are generated and accumulated. The first signal charge at this time is a charge corresponding to each color component of the incident light in the (N-1) th frame (the immediately preceding frame) generated and accumulated by each photodiode PD, and the second signal charge is Each of the photodiodes PD has a charge corresponding to each color component of the incident light in the Nth frame (current frame) generated and accumulated.

Before the period t10, the driving pulse φP
Since X1 and φPX2 are at low level, the pixel separating MOS transistor QX is off, and each pixel 101G,
101G, 101R, and 101B are vertical read lines 10
2a and 102b.

At this time, since the drive pulse φRSV is at low level, the reset switch MOS transistor QR
SV1 and QRSV2 are both off. Further, since the driving pulses φTR and φTS are both at the low level, both the switching MOS transistors QR and QS are turned off,
Electric signals on the vertical read lines 102a and 102b are not supplied to any of the first and second signal storage capacitors CR and CS. Also, shift register 1
Since the drive pulse φLD input to the load signal input terminal LD of the load register 13 is at a low level, the shift register 113 supplies the different value detection circuit 10 to its data input terminals Q1 and Q2.
The electric signal from the first and the seventh 107 is not input.

Next, when the period t10 is reached, the driving pulse φ
The RSV, the drive pulse φTR, and the drive pulse φTS are inverted from a low level to a high level. At this time, the reset switch MOS transistors QRSV1 and QRSV2
Is turned on, the switching MOS transistors QR and QS are turned on, and the charges remaining in the first signal storage capacitor CR and the second signal storage capacitor CS are discharged.

Then, at the end of the period t10 (the period t11
), The drive pulse φRSV is inverted to the low level, and the drive pulse φTS is also inverted to the low level. By inversion of the driving pulse φRSV and the driving pulse φTS, the reset switch MOS transistor QRSV
1, QRSV2 and the switching MOS transistor QS are turned off. At this time, the switching MOS transistor Q
R remains on.

In the period t11, the driving pulse φP
X1 is inverted to a high level. This drive pulse φPX
As a result, the pixel separation MOS transistors QX of the pixels 101G (upper left in FIG. 4) and the pixel 101R in the first row are turned on, and the pixels 101G and 101R are turned on.
The sources of the amplifying transistors QA, QA are connected to the vertical readout lines 102a, 102b, and are turned on (selected).

At this time, the first row of pixels 101G (FIG. 4)
, The first signal charge corresponding to the incident light has already been transferred to the gate (control region) of the amplifying transistor QA of 101R in the immediately preceding frame (in the period t13 of the (N-1) th frame), Since the first signal charge is held even after the transfer MOS transistor QT is turned off, an electric signal Vout corresponding to the held first signal charge is output to the vertical read lines 102a and 102b. You.

As described above, during the period t11, the reset switch MOS transistors QRSV1 and QRSV
Since V2 is off, when each of the amplifying transistors QA of the first row selected in the period t11 performs the source follower operation, the potential of the source becomes the current flowing between the source and the drain (the drain current). ) Is I
B (current value flowing through the constant current sources 117a and 117b).

At this time, as described above, each of the amplifying transistors QA in the first row has, at its gate (control region), its previous frame (the period t1 of the (N-1) th frame).
In 3), the first signal charge is transferred, and after the transfer is completed (the transfer MOS transistor QT is off), the gate voltage is maintained. Therefore, the first output corresponding to the first signal charge is performed by the source follower operation. Signal (a first electric signal), and the first output signal is output during the period t11.
Then, the first signal storage capacitor CR is charged through the switching MOS transistor QR already turned on.

At this time, with respect to each amplifying transistor QA in the second row, since the drive pulse φPX2 is still at a low level, each pixel separating MOS transistor QX in the second row is off. The source of each amplifying transistor QA in the second row is connected to the vertical read line 1.
02a and 102b are not connected (not selected).

At the end of the period t11, that is, when the period t12 is reached, the driving pulse φRG1 is inverted to a low level, and the driving pulse φTR is inverted to a low level.
When the drive pulse φTR becomes low level,
The switching MOS transistor QR is turned off, and the first
Is stored in a floating state and holds the value of the first output signal as it is.

As described above, during this period t11, the first
The first output signal held by the signal storage capacitor CR of the previous frame (the period t-1 of the (N-1) th frame)
13) The output of the amplifying transistor QA in a state where the first signal charge generated in 13) is held in the gate (control region). Assuming that the first output signal is VSS1, V1
The value of SS1 is a value represented by the following equation (1).

VSS1 = VRD + VS1-VT (1) Here, VRD is the reset MOS in the (N-1) th frame.
Power supply voltage supplied when the transistor QP is on,
VS1 is the rise of the gate potential of the amplifying transistor QA according to the first signal charge in the (N-1) th frame,
T is a voltage between the gate and the source when the drain current of the amplifying transistor QA is IB. Note that the value of VS1 is determined by (first signal charge / gate capacitance according to each color component of incident light).

In the period t11, the driving pulse φ
Since TR is at a high level (the switching MOS transistor QR is on), the first signal storage capacitor CR
Are both at the potential VSS1 represented by the above equation (1) charged during the period t11. Note that this potential VSS1
By the time the drive pulse φTR is inverted to the low level at the end of the period t11 (at the start of the period t12), the first switching pulse is turned off and the switching MOS transistor QR is turned off.
Is charged in the signal storage capacitor CR, and its value VSS
1 is held.

Returning to the description of FIG. 7, in the period t12 after the end of the period t11, when the drive pulse φRG1 goes low, each reset MOS transistor QP in the first row is turned on, and the power supply voltage VRD ( The read level is transmitted to the gate (control region) of each amplifying transistor QA in the first row. By turning on the reset MOS transistor QP, the amplification transistor Q
The first signal charge is discharged from the gate of A, and the gate of the amplifying transistor QA is biased to the power supply voltage VRD (read level). At this time, the drive pulse φTR also becomes low level, whereby the switching MOS transistor QR is turned off.

At the end of the period t12, that is, when the period t13 is reached, the driving pulse φTG1 is inverted to a low level,
The drive pulse φRG1 is inverted to a high level. When the drive pulse φRG1 goes high, the first
Each resetting MOS transistor QP in the row is turned off again, and the gate of the amplifying transistor QA in the first row is in a floating state. However, due to the effect of the parasitic capacitance, the gate is connected to the power supply voltage VRD (readout). Level).

On the other hand, when the drive pulse φTG1 goes low, the transfer MOS transistors QT of the pixels 101G in the first row (upper left in FIG. 4) and 101R turn on, and the pixels 101G, The charge (second signal charge) corresponding to the incident light generated and accumulated in the photodiode PD of 101R is applied to each pixel 101 in the first row.
G and 101R are transferred to the gates of the respective amplification transistors QA. This second signal charge becomes a signal charge corresponding to the incident light in the Nth frame.

As described above, the charge (second component) corresponding to each color component (green component, red component) of the incident light in the N-th frame (current frame) is provided to the gate of the amplification transistor QA.
Is transferred, each amplifying transistor Q
Since the gate potential of A rises by the amount of transferred charges, the amplification MOS transistor QA in the first row performs a source follower operation, and the source potential of the amplification transistor QA rises by the rise of the gate potential. Just rise.

In this case, a second output signal (second electric signal) corresponding to the second signal charge is turned on at this time from each of the amplifying transistors QA in the first row performing the source follower operation. Are output to the vertical readout lines 102a and 102b via the pixel separating MOS transistor QX. At the end of the period t13, that is, at the start of the period t14, the driving pulse φTG1 is inverted to the high level, and the driving pulse φTS and the driving pulse φLD are inverted to the high level.

When the drive pulse φTG1 goes high, each transfer MOS transistor QT in the first row is turned off, and the photodiodes PD in the pixels 101G (upper left in FIG. 4) and 101R in the first row are turned off. Generation
The transfer of the charge (second signal charge) corresponding to each color component of the accumulated incident light to the gate of the amplifying transistor QA ends, and the gate of the amplifying transistor QA is again brought into a floating state. Due to the effect of the parasitic capacitance, the state is maintained while the potential of the gate is increased by the transferred charge (second signal charge).

In the Nth frame, the charge transferred to the gate (control region) as the second signal charge for the current frame is reset in the next (N + 1) th frame (not shown). (Until the reset MOS transistor QP is turned on). As a result, the charge accumulated in the gate at this time is used as the first signal charge (charge for the immediately preceding frame) in the (N + 1) th frame.

As described above, transfer MOS transistor QT
Is turned on, the second signal charge is once transferred to the gate (control region) of the amplification transistor QA, and then, even if the transfer MOS transistor QT is turned off, the second signal charge is transferred to the gate. Since the signal is held, the signal (voltage signal) corresponding to the electric charge (second signal electric charge) accumulated in the gate is output from the amplifying transistor QA by the source follower operation until the gate is reset thereafter (period t14). Is output.

When the driving pulse φTS goes high, the switching MOS transistor QS is turned on, and the amplifying transistors in the first row whose second signal charges are stored in the gate by the source follower operation. The second output signal output from the QA is charged to the second signal storage capacitor CS via the pixel separation MOS transistor QX and the vertical readout lines 102a and 102b which are turned on.

In this period t14, when the current flowing between the source and the drain becomes IB due to the source follower operation, the value of the potential of the source of the amplifying transistor QA (second output signal; denoted as VSS2) VSS2 is , The value shown in the following equation (2). VSS2 = VRD + VS2-VT (2) Here, VS2 is an increase in the gate potential of the amplifying transistor QA according to the second signal charge. Incidentally, the value of VS2 is expressed as (second signal charge / gate capacitance according to each color component of incident light), similarly to VS1 described above.

In this period t14, since the driving pulse φTS is at the high level (the switching MOS transistor QS is turned on), both ends of the second signal storage capacitor CS are charged during the period t14. It becomes the potential VSS2 represented by the equation (2). Note that this potential V
SS2 is at the end of period t14 (at the start of period t15)
By the time the drive pulse φTS is inverted to a low level and the switching MOS transistor QS is turned off, the second signal storage capacitor CS is charged.

As described above, the second output signal (voltage signal) represented by the equation (2) is stored and held in the second signal storage capacitor CS, while the first signal storage capacitor CS stores the second output signal (voltage signal). As described above, the first output signal (voltage signal) represented by the equation (1) is stored and held in the capacitor for use CR. Then, the stored second output signal (voltage signal) and first output signal (voltage signal) are input to the different value detector XA.

From the different value detector XA, as will be described in detail later, when the magnitude of the difference between the first output signal (analog signal) and the second output signal (analog signal) is equal to or larger than a predetermined value. Only output is high level (logic level high level)
Alternatively, a low level (low level of logic level) different value signal (digital signal) is output.

Here, the operation of the outlier detector XA in the outlier detector 107 will be described. As described above, in the period t11, the electric signal from the amplifying transistor QA is held in the first signal storage capacitor CR (first output signal VSS1), and in the period t12, the amplifying transistor QA
The gate of A is reset. Then, in a period t13,
The signal charge from the photodiode PD is newly transferred to the gate of the amplifying transistor QA, and an electric signal corresponding to the signal charge is further transferred to the vertical read lines 102a and 102a.
b.

The electric signal transferred at this time is in the period t1
At 4, the signal is stored in the second signal storage capacitor CS via the switching MOS transistor QS (second output signal VSS2). By the way, in this period t14, as described above, the first output signal VSS1 is already stored and held in the first signal storage capacitor CR.
The first output signal VSS1 is supplied to a non-inverting input terminal of the voltage comparator AP1 and an inverting input terminal of the voltage comparator AP2. Then, the second output signal VSS2 is newly obtained.
Is stored and held in the second signal storage capacitor CR, the second output signal VSS2 is input to the non-inverting input terminal of the voltage comparator AP2 and the inverting input terminal of the voltage comparator AP1.

As a result, in the different value detection circuit 107, the first and second voltage comparators AP1 and AP2 separately
The magnitude of the output signal VSS1 and the magnitude of the second output signal VSS2 are compared. The first output signal V at this time
SS1 is represented by the above equation (1), and the second output signal VSS2 is represented by the above equation (2).

Therefore, the voltage comparator AP1 and the voltage comparator A
In P2, the first output signal VSS1 shown in the following equation (3)
And the second output signal VSS2. VSS1−VSS2 = (VRD + VS1−VT) − (VRD + VS2−VT) = VS1−VS2 (3) Thus, the magnitudes of the first output signal VSS1 and the second output signal VSS2 are compared. This means that the intensity of the color component (green, red, blue) of the specific pixel in the (N-1) th frame (equivalent to VS1) changes from the intensity (VS2) of the color component in the Nth frame to the intensity (VS2), This is synonymous with detecting the change in the intensity of the color component between the two frames.

Both the voltage comparator AP1 and the voltage comparator AP2 which compare the value shown in the above equation (3) are used when the signal input to the non-inverting input terminal is larger than the signal input to the inverting input terminal. Outputs the power supply voltage level (high level) and outputs the ground level (low level) when the signal input to the non-inverting input terminal is equal to or smaller than the signal input to the inverting input terminal. I do.

Therefore, when the first output signal VSS1 is larger than the second output signal VSS2, the voltage comparator AP
1 becomes the power supply voltage level (high level), and conversely, the second output signal VSS2 becomes the first output signal VSS1.
If it is larger, the output of the voltage comparator AP2 becomes the power supply voltage level (high level).

When the first output signal VSS1 is equal to the second output signal VSS2, the voltage comparators AP1 and A1
Both outputs of P2 are at the ground level (low level). The outputs of the voltage comparators AP1 and AP2 obtained in this manner are both input to a logical OR calculator OR to perform a logical OR operation. In this case, only when the magnitude of the first output signal VSS1 and the magnitude of the second output signal VSS2 are different (either one is larger or smaller than the other), the output of the OR operator OR, that is, the output of the different value detector XA Becomes a high level (high level of a logic level).

When the magnitudes of the first output signal VSS1 and the second output signal VSS2 are equal, the logical sum OR
That is, the output of the different value detector XA is at a low level (logic low level). It is known that the value of VT (gate-source voltage) in the above formulas (1) and (2) varies from one amplification transistor QA to another and causes so-called fixed pattern noise. Therefore, as shown in the above-described equation (3), when performing the outlier detection, that is, the first
When calculating the difference between the output signal VSS1 and the second output signal VSS2, the different value signal is not affected by the VT value.
Outlier detection (moving object detection) can be performed without being affected by fixed pattern noise.

It is known that the first output signal VSS1 and the second output signal VSS2 usually include a random noise component in addition to the fixed pattern noise component. Therefore, when detecting a different value, an erroneous signal may be generated due to these random noise components. However, in the present embodiment, the voltage comparator AP1 and the voltage comparator AP2 are connected to the signal voltage input to the non-inverting input terminal and the inverting input terminal in order to prevent the generation of an erroneous signal due to the random noise component. The output is inverted when the difference between the input signal voltages exceeds a certain threshold voltage.

Returning to the description of FIG. 7, the different value signal from the different value detector XA of the different value detection circuit 107 having the above-described configuration is applied during the period t1.
At 4, the drive pulse φLD is stored in the register corresponding to each bit of the shift register 113 at the timing when it becomes high level. At the end of the period t14 (at the start of the period t15), the driving pulse φPX1, the driving pulse φTS,
The drive pulse φLD is inverted to a low level.

When the drive pulse φPX1 goes low as described above, the pixel separating MOS transistor QX is turned off, and the first row of pixels 101G (FIG. 4)
And the pixel 101R and the vertical readout line 102a,
102b. When the driving pulse φTS goes low, the switching MOS transistor QS is turned off.

When the drive pulse φLD goes low, the vertical read lines 102a and 102b are again stored in the register corresponding to each bit of the shift register 113.
No different value signals are inputted from the different value detection circuits 107, 107. In this period t15, the clock pulse φCK is input to the shift register 113, and the different value signal (digital signal) held in the register corresponding to each bit is sequentially changed according to the timing at which the clock pulse φCK is generated. Horizontal readout line 112
And output to the output terminal VO.

Note that due to the influence of the parasitic capacitance of the horizontal read line 112, the voltage signal (different value signal) read out to the horizontal read line 112 takes a long time until its waveform is distorted and reaches a steady state. In the present embodiment, the number of electric signals (different value signals) appearing on the horizontal read line 112 is 2
Because it is digitized (digitized), if it reaches a certain level (threshold level of a logic circuit), it does not reach a steady state,
It is possible to determine whether the signal is at the low level, and the reading operation is speeded up.

In the subsequent period t20 to t25, the second
The same operation as the readout operation of the pixel 101G (upper left in FIG. 4) and the pixel 101R in the first row in the above-described period t10 to t15 is repeated for the pixel 101G (lower left in FIG. 4) and the pixel 101B in the row. And a different value signal (digital signal) in the Nth frame from the pixel 101G (lower left in FIG. 4) and the pixel 101B in the second row.
Are sequentially output from the output terminal VO. That is, during this period t20 to t25, a change between frames of the green component of the incident light by the green pixel 101G and a change between the frames of the green component of the incident light by the blue pixel 101B are detected.

As described above, in the motion-detecting solid-state imaging device 100, the pixels in the first row, that is, the green pixels 101G (upper left in FIG. 4), during the periods t10 to t15,
An electric signal (analog signal) corresponding to each color component output from the red pixel 101R is output in two consecutive frames (Nth frame).
-1 frame and the Nth frame), and when the magnitude of the difference is equal to or greater than a certain value, the vertical read line 10
Outlier detection circuits 107 and 10 arranged in 2a and 102b
7 outputs a different value signal for each color component (green, red).

In the period t20 to t25, the second
The electric signals (analog signals) corresponding to the respective color components output from the pixels in the row, that is, the green pixels 101G (lower left in FIG. 4) and the blue pixels 101B are consecutive two frames (the (N−1) th frame). Nth frame)
When the magnitude of the difference is equal to or larger than a certain value, the different value detection circuit 10 arranged on the vertical read lines 102a and 102b
7, 107 output different value signals for each color component (green, blue).

The different value signal generated by each different value detection circuit 107, 107 is output to the output terminal V by the operation of the shift register 113 every time the clock pulse φCK is generated.
O individually (the four pixels 101G, 101G, 101
R, 101B). By using such a solid-state imaging device 100 for motion detection, for example, from the output terminal VO, all the different value signals indicating the intensity change of each color component are counted, and when the value becomes a predetermined value or more,
The presence / absence of the movement of the subject (moving object) can be determined.
In this case, if at least a change in luminance indicating light and shade causes a change in intensity of any color component, the movement of the subject (moving object) can be detected.

Further, according to the solid-state imaging device 100 for motion detection, the shift register 113 outputs, for each color component,
Since the different value signal can be output at an individual timing, the generation state of the different value signal is monitored by paying attention to a specific color component, and the presence or absence of movement of the subject (moving object) is determined according to the result. Is also good. That is, by monitoring the different value signals individually, it is possible to detect a motion according to the color of the subject (moving object). For example, for a red subject (moving body),
By paying attention to the generation state of the different value signal corresponding to the electric signal obtained from the red pixel 101R, more precise motion detection can be performed.

Such motion detection for outputting a different value signal for each color component can be performed continuously between two or more consecutive frames by repeating the above operation. (Second Embodiment) Next, a motion detection solid-state imaging device 200 according to a second embodiment will be described with reference to FIGS. It should be noted that this second embodiment is described in claims 1, 3,
This corresponds to claim 4.

In the solid-state imaging device 200 for motion detection according to the second embodiment, three types of pixels 201C, 201C, 201M, and 20 constituting a complementary color system (CMY color system) are provided in a light receiving unit.
1Y is arranged. In the solid-state imaging device 200 for motion detection according to the second embodiment, a signal processing circuit 240 and a motion determination circuit 250 are connected to an output terminal VO, and video signal processing circuits 230a and 230a are connected to vertical readout lines 202a and 202b. 230b is connected.

The other configuration of the solid-state imaging device 200 for motion detection is the same as that of the solid-state imaging device 100 for motion detection of the first embodiment. First, the solid-state imaging device 2 for motion detection
The outline of the circuit configuration of 00 will be described.

The motion detecting solid-state imaging device 200 includes a pixel 2
01C, 201C, 201M, and 201Y are arranged in a matrix, and each pixel 201C, 201C, 201M,
201Y is a vertical read line 102a, 102b for each column.
It is connected to the. This pixel 201C, 201C, 20
1M and 201Y have a cyan transmission filter, a magenta transmission filter and a yellow transmission filter formed on the incident surface (not shown), and pixels 201C and 201C.
Represents a cyan pixel, pixel 201M constitutes a magenta pixel, and pixel 201Y constitutes a yellow pixel.

Each pixel 201C, 201C, 201
M and 201Y are a photodiode PD, an amplifying transistor QA, and a transfer M, as in the pixel of the first embodiment.
It comprises an OS transistor QT, a reset MOS transistor QP, and a pixel separation MOS transistor QX. Here, the specific configuration,
The connection relationship is the same as in the first embodiment described above, and a description thereof will be omitted.

The pixels 201C, 201C, 201M,
201Y includes pixels 201C, 201C, 201M,
201Y from the corresponding vertical readout line 2
Vertical scanning circuit 206 for transferring the data to the address lines 02a and 202b.
Is connected. Further, different value detection circuits (signal comparison circuits) 207, 207 are arranged on the vertical read lines 202a, 202b provided for each column, and shift registers (signals) are provided to the outputs of the different value detection circuits 207, 207. Transfer circuit) 213 is connected.

As described above, the vertical read lines 202a, 20
The different value detection circuit 207 arranged in each of the pixels 201C, 201C, 201M, 20M
When an electric signal corresponding to each color component (cyan, magenta, yellow) of the incident light is output from 1Y to the corresponding vertical read line 202a, 202b, the electric signal is stored as an electric signal for the immediately preceding frame, and The same pixel 2 at the next fixed timing as the stored electric signal
An electrical signal indicating the intensity of each color component output from 01C, 201C, 201M, and 201Y is compared with an electric signal for the current frame, and a different value signal representing the result of the comparison is output.

In this case, the different value signal (each pixel 201C, 201C, 201C) output from the shift register 213
M, 201Y) are cyan,
The signals indicate the intensity changes of the magenta and yellow color components, respectively. The specific configuration of the outlier detection circuit 207 is the same as that of the outlier detection circuit 107 (FIG. 5) of the first embodiment, and a detailed description thereof will be omitted.

The operation of the shift register 213 for transferring the outputs of the different value detection circuits 207 and 207 is the same as that of the shift register 113 of the first embodiment. That is,
In a corresponding register of the shift register 213, a different value signal indicating a change in intensity of each color component (cyan, magenta, yellow) of the incident light is stored, and thereafter, for each color component transferred to the horizontal readout line 212 sequentially. Are sequentially output from the output terminal VO at a constant timing.

The vertical read lines 202a, 202
b, the reset switch MOS transistors QRSV1 and QRSV2, and the constant current sources 217a and 217
The operation and the like of b are the same as those in the first embodiment, and a detailed description thereof will be omitted. Also, the video signal generation circuit 230a,
230b is connected to each of the vertical read lines 202a and 202b, and each pixel 201C, 20
1C, 201M, 201Y to each vertical read line 2
When an electric signal corresponding to each color component is output to 02a and 202b, a signal obtained by subtracting a dark current component from the electric signal is output as a video signal in the current frame.

The video signal generation circuits 230a and 230
The video signal output from b is sequentially transferred to the horizontal readout line 234 by the operation of the horizontal scanning circuit 235, and then output from the output terminal Ao via the output buffer amplifier 237. The drain of a reset switch MOS transistor (n-channel type) QRSH whose source is grounded is connected to the horizontal read line 234. When a reset drive pulse φRSH is output from a drive pulse generating circuit (not shown) from the node 236 to the gate of the reset switch MOS transistor QRSH via the clock line 236 a, the reset pulse remains on the horizontal read line 34. The discharged (reset) operation of the discharged charges is performed.

Video signal generation circuits 230a and 240b
Are the hold capacitances CV1 and CV2 as shown in FIG.
And switching MOS transistors (n-channel type) QV1 and QV2 for switching the sample and hold. Here, one electrode (the upper side in the figure) of the hole capacitors CV1 and CV2 is connected to the vertical read line 202a,
202b, and the other electrode (the lower side in the figure) is grounded via the switching MOS transistors QV1 and QV2, and the selection signal lines 238a and 238b,
Furthermore, the MOS transistor QH for the horizontal read switch
1 and QH2, and is connected to the horizontal readout line 234. Switching MOS transistors QV1, QV2
Is connected to a clock line 232a to supply a drive pulse φV.

The solid-state imaging device 200 for motion detection thus configured operates according to the timing chart shown in FIG. The timing chart shown in FIG.
Compared with the timing chart of the embodiment (FIG. 7), a drive pulse φV for generating a video image using an electric signal (analog signal) corresponding to each color component, and for transferring the drive pulse φV to the horizontal scanning circuit 235 Drive pulse φH1, H
2 and that a driving pulse φRSH for resetting the horizontal read line 234 is added.

Therefore, each pixel 201C, 201C, 20C
The procedure for obtaining a different value signal between frames according to the electric signal indicating the intensity of each color component (cyan, magenta, yellow) from 1M, 201Y is the same as that of the first embodiment.
Detailed description is omitted. Incidentally, the period t10 to t1
The generation of the different value signal based on the electric signal from the cyan pixel 201C of the first row (upper left of FIG. 8) and the magenta pixel 201M is performed in the cyan pixel 201C of the second row in the period t20 to t26. 8 and the yellow pixel 20
Generation of an outlier signal based on the electric signal from 1M is performed.

Here, the processing operation of the video signal will be briefly described. In the video signal generation circuits 230a and 230b,
Via the clock line 232a, the switching MOS transistors QV1 and QV
When the drive pulse φV is supplied to the second gate, a video signal (analog signal) is output according to the timing at which the drive pulse φV changes.

As shown in FIG. 9, the drive pulse φV rises to a high level during periods t13 and t23. At the start of this period t13, the drive pulse φRG1 is inverted to the high level, so that each reset MOS transistor QP in the first row is turned off, and the gate of the amplification transistor QA in the first row is brought into a floating state. However, due to the effect of the parasitic capacitance, this gate is kept in the period t12
Power supply voltage VRD (read level) already supplied at
, The biased state is maintained.

Then, when the drive pulse φV is inverted to the high level, the video signal generation circuits 230a, 230a
30b switching MOS transistors QV1, QV2
Turns on, the lower electrodes of the hold capacitors CV1 and CV2 in the figure are grounded, and the potential difference between both ends of the hold capacitors CV1 and CV2 becomes equal to the dark output signal VD. The dark output signal VD is charged to the hold capacitor CV by the time the drive pulse φV is inverted to a low level and the switching MOS transistor QV is turned off.

At the end of period t13 (at the start of period t14), drive pulse φV is again inverted to low level, and this time, drive pulse φTG1 is inverted to low level. When the drive pulse φTG1 becomes low level, the pixels 201C of the first row (upper left in the figure), 20
The 1M transfer MOS transistor QT is turned on, and charges (according to the cyan and magenta color components in the current frame) corresponding to the incident light generated and accumulated in these pixels 201C (upper left in the figure) and the photodiode PD of 201M. (The second signal charge shown) is the pixel 201C of the first row.
(Upper left in the figure), 201M1 amplifying transistor QA
Is transferred directly to the gate. This second signal charge becomes a signal charge corresponding to the intensity of the color component (cyan, magenta) of the incident light in the Nth frame.

As described above, when the charge (second signal charge) corresponding to the intensity of the color component of the incident light in the N-th frame (current frame) is transferred to the gate (control region) of the amplification transistor QA. Since the gate potential of each amplifying transistor QA rises by the amount of the transferred charges, the amplifying MOS transistor QA in the first row performs a source follower operation, and the source potential of the amplifying transistor QA becomes It rises by the rise of the gate potential.

In this case, an electric signal corresponding to the second signal charge is supplied from each of the amplifying transistors QA in the first row performing the source follower operation via the pixel separating MOS transistor QX which is on at this time. , Vertical read line 2
02a and 202b. And in period t15,
When the drive pulse φTG1 goes high, each transfer MOS transistor QT in the first row is turned off, and the electric charge (according to the incident light generated and accumulated in the photodiode PD of the pixel 1 in the first row) The transfer of the second signal charge) to the gate (control region) of the amplifying transistor QA ends, and the gate (control region) of the amplifying transistor QA is again brought into a floating state. The state is maintained while the potential of the gate is increased by the transferred charge (the second signal charge).

Thereafter, in period t16, drive pulse φH
1, φH2 are sequentially activated for a certain period, and the horizontal readout switch MOS transistors QH1, QH2
Are turned on alternately at a predetermined timing.

When the horizontal readout switch MOS transistors QH1 and QH2 are turned on, the video signal generated by the video signal generation circuits 230a and 230b is transferred to the horizontal readout line 234. This period 1
During 6, the reset drive pulse φRSH is raised to a high level at a predetermined timing. Then, at the timing when the drive pulse φRSH becomes high level, the reset switch MOS transistor QRSH is turned on, and the operation of discharging (resetting) the charge remaining on the horizontal read line 234 is performed.

In the period from t20 to t26, the video signal generation circuit 2 is operated in the same manner as in the period from t10 to t16.
Charges (second signal charges) corresponding to the incident light generated and accumulated in the photodiodes PD of the pixels 201C (lower left in the drawing) and 201Y of the second row from 30a and 230b are generated. The signal charge generated at this time is a signal charge corresponding to the intensity of the color component (cyan, yellow) of the incident light in the Nth frame.

In the motion detecting solid-state imaging device 200 according to the second embodiment, similarly to the first embodiment, the different value signals generated by the different value detection circuits 207 and 207 are shifted by a shift register. 213, the clock pulse φ
Each time CK occurs, it is individually output from the output terminal VO and sent to the signal processing circuit 240. Here, the signal processing circuit 240 is based on the timing when the different value signal is sent from the shift register 213 and the generation timing of the drive pulse supplied to each of the pixels 201C, 201C, 201M, and 201Y from the vertical scanning circuit 206 and the like. Then, the different value signals sequentially transmitted are recognized for each color component (cyan, magenta, yellow), and the generation state of these different value signals is monitored. The motion determination circuit 250 connected to the signal processing circuit 240 counts, for example, all the number of outlier signals detected by the signal processing circuit 240, and when the value becomes equal to or greater than a predetermined value, the subject ( The presence or absence of the movement of the (moving body) is determined.

The signal processing circuit 240 can process the different value signal from the shift register 213 for each color component. Therefore, the signal processing circuit 240 monitors the generation state of the different value signal for each color component, and according to the result, the subject ( (Moving body) can be determined. Also in this case, by individually monitoring the different value signals generated for each color component, it is possible to detect a motion according to the color of the subject (moving object) by focusing on a specific color component.

In the first and second embodiments, the case where the amplifying stage (amplifying transistor QA) of the pixel is used as the JFET has been described. However, the present invention is not limited to this. Even if it is a transistor or a bipolar transistor, any device that can control the output voltage / current such as the drain or collector, the source or the emitter by the voltage of the control electrode such as the gate or the base can be similarly applied. May be used.

In the first and second embodiments, the charge corresponding to the intensity of the color component (green, red, blue, or cyan, magenta, or yellow) of the incident light generated by the photoelectric conversion element is used.
Although the case of direct transfer to the control area of the amplification element has been described,
The present invention is not limited to this, and is similarly applied to the case where these charges are transferred to the diffusion region and held, and then the potential is detected at the gate of an amplification element such as a MOS transistor via a signal line. It goes without saying that you can do it.
As an example of such a pixel, for example, the document “Acti
ve Pixel Sensors: Are CCD's Dinosaurs? ', Fossum E.
R., Proceeding of SPIE: Charge-Coupled Device and S
olid State Optical Sensors III, Vol. 1900, pp2-14 (199
The one described in 3) is well known.

Further, in the first and second embodiments, the case where the pixels are arranged on a two-dimensional matrix has been described, but the present invention can be similarly applied to the case where the pixels are arranged on a one-dimensional matrix.

[0126]

According to the invention as set forth in any one of claims 1 to 4, for each color component of the incident light, the intensity change of the color components of two consecutive frames is converted into a binary value at a point in time when the color change is transferred to the horizontal readout line. It is possible to perform dynamic image processing according to each color component in the solid-state imaging device for motion detection, and it is necessary to provide peripheral circuits such as an AD conversion circuit, an image memory, and an image processing circuit outside the moving image processing. As a result, the cost of the entire apparatus can be reduced.

In addition, since the externally required AD conversion circuit is unnecessary, the dynamic range is not limited, and the signal processing can be performed in a wide dynamic range of the motion detecting solid-state imaging device itself. it can. Further, since it is not necessary to provide a separate circuit (signal comparison circuit) or the like for generating a different value signal indicating a change in intensity of the color component of the incident light for each pixel, the aperture ratio and the resolution can be improved. It is planned.

Also, an electric signal indicating the intensity of each color component of the incident light output from the pixel is used as an electric signal for the immediately preceding frame and an electric signal for the current frame, and a different value indicating a change in intensity of each color component. Since the signal is generated, the moving object detection processing can be performed without being affected by fixed pattern noise or random noise for each amplifying transistor, and highly accurate and stable moving object detection processing can be performed. Also, at the time of reading out to the horizontal readout line, since the different value signal indicating the intensity change of each color component is a binary signal, the processing can be speeded up.

[Brief description of the drawings]

FIG. 1 is a plan view illustrating a device configuration of a motion detection solid-state imaging device 100 according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of the motion detection solid-state imaging device 100 taken along the line II-II of FIG.

FIG. 3 is a cross-sectional view of the solid-state imaging device for motion detection 100 along the line III-III in FIG. 1;

FIG. 4 is a circuit diagram schematically showing the motion detection solid-state imaging device 100 according to the first embodiment of the present invention.

FIG. 5 is a circuit diagram showing an internal configuration of an outlier detection circuit 107 of the solid-state imaging device 100 for motion detection.

FIG. 6 is a characteristic diagram showing an example of input / output characteristics of an outlier detector XA in an outlier detector 107;

FIG. 7 is a timing chart for explaining the operation of the solid-state imaging device for motion detection 100;

FIG. 8 is a schematic circuit diagram illustrating a schematic configuration of a motion detection solid-state imaging device 200 according to a second embodiment of the present invention.

FIG. 9 is a timing chart for explaining the operation of the motion detection solid-state imaging device 200 according to the second embodiment of the present invention.

FIG. 10 is a block diagram showing a conventional image processing apparatus 200 for motion detection for generating a different value signal.

[Explanation of symbols]

100, 200 solid-state imaging device for motion detection 101G, 101R, 101B, 201C, 201M,
201Y pixels 102a, 102b, 202a, 202b vertical readout lines 111G, 111R, 111B color filters 106, 206 vertical scanning circuits 107, 207 outlier detection circuits (signal comparison circuits) 113 shift registers (signal transfer circuits) 235 horizontal scanning circuits ( Signal transfer circuit) PD photodiode QA amplifying transistor (JFET) CR signal storage capacitor (first charge storage unit) CS signal storage capacitor (second charge storage unit) XA outlier detector CV hold capacitance QV switch MOS transistor

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code FI H04N 11/04 H01L 27/14 D

Claims (4)

[Claims] 1. At least 3 constituting a predetermined color system
A solid-state imaging device in which a large number of three kinds of pixels each outputting an electric signal corresponding to a kind of color component are arranged in a matrix in a predetermined arrangement pattern, wherein each column of the pixels arranged in the matrix is A vertical scanning circuit that selects a specific row of the plurality of pixels and transfers an electrical signal from the pixel to the vertical reading line at a fixed timing; Each of which is arranged on the readout line and stores an electric signal output from a specific pixel at a fixed timing as an electric signal for the immediately preceding frame, and outputs the stored electric signal and the output from the pixel at the next fixed timing. A signal comparing circuit that compares the electrical signals with respect to the current frame and outputs a signal representing the result of the comparison. A solid-state imaging device for motion detection, comprising: a signal transfer circuit for sequentially transferring a signal representing the result of the comparison output to the horizontal readout line. 2. The three types of pixels forming the predetermined color system include a red pixel, a green pixel, and a RGB pixel forming an RGB color system.
The solid-state imaging device for motion detection according to claim 1, wherein the solid-state imaging device is a blue pixel. 3. The three pixels constituting the predetermined color system are a cyan pixel, a magenta pixel, and a yellow pixel constituting a CMY color system.
4. The solid-state imaging device for motion detection according to 4. 4. A motion judging circuit for judging a motion of a moving object in accordance with a state of generation of a signal representing the result of the comparison, is connected to the horizontal read line. The solid-state imaging device for motion detection according to any one of claims 1 to 3.