JPH11122256A - Atm switch - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the effect of congestion by providing a cell buffer so as to conduct priority control with a simple configuration and aborting an input cell when a delay time not allowed by the service is in excess. SOLUTION: An N×N switch 20 is placed between input side cell buffers 101 , 102 ,...10N having a buffer for each service class of a communication cell and a destination port and output side cell buffers 301 , 302 ,...30N. Storage cell level information representing a storage cell level for a storage state of all the output cell buffers and buffers of the N×N switch and other input cell buffers than its own input side cell buffer is given to each input cell buffer, and a cell is aborted from a delay value collected from the storage cell level information and a delay time allowable time set to each queue at the input. Furthermore, the input cell outputted to a destination port is selected based on the delay time allowable value, the service class set simultaneously and the storage cell level.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an ATM switch having a cell buffer for each port, and more particularly to an ATM switch in which communication cells are discarded for traffic control.

[0002]

2. Description of the Related Art Asynchronous Transfer Mode
In an ATM switch in the fer mode (ATM) network, when an ATM cell input from a plurality of input ports is switched to a plurality of output ports, cells input from different input ports use the same port in the internal or output port. Use can cause collisions. The ATM switch having the cell buffer stores the cells and performs contention control in order to avoid this collision. Furthermore, with the ATM switch in multimedia, with the increase in communication volume and the diversification of communication applications, in the case of a certain kind of voice data that does not hinder the user even if the communication cells overflow from the cell buffer, this is intended. The priority is prioritized and discard control is performed to improve the throughput.

An ATM switch having such a cell buffer queues cells with a cell buffer for each service class in priority control and discard control of cell traffic, and provides a service class having a high delay priority in congestion. Cells are preferentially output from the queue, and when the maximum queue length is exceeded, a newly arrived cell is discarded, or the head cell of the queue is pushed out. An ATM switch having a cell buffer for performing such delay control and discard control is disclosed in Japanese Patent Application Laid-Open No. 7-297831.
, There is an input buffer type ATM switch using an "input buffer type ATM switch circuit".

FIG. 7 shows such an input buffer type ATM.
This shows an outline of the configuration of the switch. This input
The buffer type ATM switch is provided for the ATM switch.
Input buffer 7 for queuing input cells
1₁, 71_Two, ..., 71_NAnd this input cell
Matrix that switches to the corresponding output port 79 first
Switch 75 and a competition arbitration circuit 76.
ing. Input buffer 71 ₁, 71_Two, ..., 71_NIs
Each corresponds to the input port of the matrix switch
Has a cell buffer and the service class of the input cell
Queue for each cell and manage the storage time for each cell
It has become. The contention arbitration circuit 76 has all input buffers.
Cell to be output to the matrix switch
Contention arbitration information and cell output permission as control signals for selecting
An enable signal 78 is output. This competitive mediation
The information and cell output enable signal 78 indicate the cell delay level and cell
Storage time and cells output from the buffer
Based on the number of cells in the input buffer output from the counter.
Contention arbitration information and the weight of each input buffer
This is a control signal based on output destination information. The Matrix
For switch 75, the matrix switch
Switching settings for switching the switch configuration
Information 77 is output. Also, the maximum
-Service class and cell storage time
And discard from the cell buffer based on the number of stored cells.
After selecting a cell, it is discarded.

That is, such an input buffer type ATM
The switch has a cell buffer for each service class for a plurality of service classes according to the priority of the cells, and performs priority control and discard control of these cells in consideration of the delay time. I have.

[0006]

In such an ATM switch, a cell buffer is indispensable in order to perform priority control when handling cells in a service class. For traffic that is becoming more and more frequent, a large capacity cell buffer of tens of thousands of cells or more is required in order to accumulate communication cells and withstand temporary congestion. Further, if the capacity of the cell buffer is increased, it is advantageous in terms of cell discard control, but in terms of priority control, the cell delay time cannot be ignored, and the possibility of becoming longer than the time allowed in the communication service increases.

In the case of real-time traffic such as voice data cells, if a delay exceeding a certain value occurs due to congestion, even if some data is discarded during reproduction, the effect is small in terms of the quality of service. Rather, if a delay equal to or greater than this fixed value occurs, discarding at the time of occurrence of this delay rather than increasing the priority of the voice data cell and taking into account the quality of the entire communication system is considered. The influence can be kept small.

However, in the conventional ATM switch, cells are queued up to the maximum queue length, and weighted for each cell based on the delay priority, storage time, and the number of stored cells for each service class. Selects cells to be discarded, but does not have a function to discard when the delay time exceeds the time allowed for communication service due to congestion, so the quality of service provided to users at a certain time due to this congestion deteriorates It can be done.

Further, when the maximum queue length is exceeded, a cell to be discarded is selected from the queue, so that a complicated discarded cell selection circuit is required. It is necessary to process the weights of all cells in the buffer within one cell processing time, which makes it difficult to increase the speed of the ATM switch port and increase the capacity of the buffer, and enhance the performance and functions by diversifying future communication services. It lacks the development potential.

Further, a complicated contention arbitration circuit for arbitrating cells output to the matrix switch among a plurality of input cell buffers is required. The number of competitive arbitration operations that can be performed within one cell processing time is limited, and when it is desired to increase the speed of the port of the ATM switch, a so-called head-of-of-the-head that cells that cannot be output stagnate at the head of the cell buffer. -It is difficult to completely avoid line blocking (HOL).

An object of the present invention is to provide a cell buffer, perform priority control with a simple configuration, and discard input cells when the delay time exceeds a service unacceptable, thereby suppressing the influence of congestion. A made it possible
To provide a TM switch.

[0012]

According to the first aspect of the present invention, (a) an input port for inputting a communication cell;
(B) connecting a line to an output port for outputting the cell based on the destination of the cell input from the input port, and (c) connecting a line to an output port based on the destination of the cell input from the input port; A matrix switch having an exchange buffer for accumulating cells input from the input port for each output port, (d) an exchange buffer monitoring unit for monitoring the accumulation state of the exchange buffer, and (e) a cell input from the input port , An input cell buffer that accumulates the data corresponding to the output port based on the destination of the cell, (f) an input cell buffer monitoring unit that monitors the accumulation state of the input cell buffer, and (g) output from the matrix switch. An output cell buffer for accumulating cells for each output port, and (h) an output cell buffer for monitoring the accumulation state of the output cell buffer A viewing unit, (i) an output cell header adding unit that adds destination header information to cells output from the output cell buffer to the output port, and (nu) an input cell buffer monitoring unit and an output cell buffer monitoring unit. A selection output control unit for sequentially outputting cells stored in a corresponding input cell buffer to a matrix switch based on a monitoring result of the exchange buffer monitoring unit; and (l) an input cell buffer monitoring unit and an output cell buffer monitoring unit. The ATM switch is provided with an input cell discarding unit for discarding cells input from the input port to the input buffer based on the monitoring result.

That is, according to the first aspect of the present invention, the input cell buffer, the output cell buffer, and the matrix switch are provided with buffers corresponding to the output ports, and each of the buffers has a monitoring unit for monitoring the buffer accumulation state. It was provided. Then, based on the accumulation state, selection control of cells output from the input cell buffer to the matrix switch is performed, and cells input to the input cell buffer are discarded without queuing.

According to the second aspect of the present invention, (a) an input port for inputting a communication cell, and (b) an output port for outputting the cell based on a destination of the cell input from the input port. (C) a matrix switch having an exchange buffer for connecting a line to an output port based on a destination of a cell input from an input port and accumulating cells input from the input port for each output port; An exchange buffer monitoring unit that monitors the accumulation state of the exchange buffer, and (e) a cell input from an input port is provided for each input cell buffer in which the input cell is accumulated based on header information of the destination of the cell. An input cell header information adding unit for adding the set delay time allowable value to the header information of the input cell; and (f) input from the input cell header information adding unit. An input cell buffer for accumulating cells corresponding to an output port based on the destination of the input cell; (g) an input cell buffer monitoring unit for monitoring the accumulation state of the input cell buffer; and (h) an output from the matrix switch. An output cell buffer for accumulating cells to be output for each output port, (i) an output cell buffer monitor for monitoring the accumulation state of the output cell buffer, and (nu) a cell output from the output cell buffer to the output port. An output cell header adding unit for adding header information serving as a destination to the input cell buffer; and (v) an output cell header adding unit that accumulates in a corresponding input cell buffer based on monitoring results of an input cell buffer monitoring unit, an output cell buffer monitoring unit, and an exchange buffer monitoring unit. A selection output control unit for sequentially outputting the cells that are present to the matrix switch,
(I) a delay value counting unit that counts the delay values based on the monitoring results of the input cell buffer monitoring unit, the output cell buffer monitoring unit, and the exchange buffer monitoring unit; and (v) the delay values counted by the delay value counting unit. A delay value allowance determining unit for determining whether or not the delay time allowance value added by the input cell header information adding unit is exceeded; and (f) the delay value aggregated by the delay value aggregation unit by the delay value allowance determination unit. When it is determined that the delay time allowable value has been exceeded, the ATM switch is provided with an input cell discarding unit for discarding cells input from the input cell header information adding unit to the input buffer.

That is, according to the second aspect of the present invention, the input buffer cell, the output buffer cell, and the matrix switch are provided with buffers corresponding to the output ports, and each of the buffers has a monitoring unit that monitors the accumulation state of the buffer. It was provided. Based on the accumulation state, the selection control of the cell output from the input cell buffer to the matrix switch is performed, and the input cell adds an allowable delay time based on the header information in the input cell buffer. Compared with the delay time calculated from the accumulation state of each buffer, a buffer exceeding the allowable delay time is discarded without being newly queued.

According to the third aspect of the present invention, (a) an input port for inputting a communication cell, and (b) an output port for outputting the cell based on a destination of the cell input from the input port. (C) a matrix switch having an exchange buffer for connecting a line to an output port based on a destination of a cell input from an input port and accumulating cells input from the input port for each output port; An exchange buffer monitoring unit that monitors the accumulation state of the exchange buffer, and (e) a cell input from an input port is provided for each input cell buffer in which the input cell is accumulated based on header information of the destination of the cell. The input cell header information for adding the set delay time allowable value and service class information indicating whether or not the cell can be discarded to the header information of the input cell. An adding unit; (f) an input cell buffer for storing cells input from the input cell header information adding unit in correspondence with service class information and an output port based on the destination of the input cell; An input cell buffer monitoring unit that monitors the accumulation state of the cell buffer; (h) an output cell buffer that accumulates cells output from the matrix switch for each output port based on the service class information; An output cell selection control unit that selects a cell to be output from the output cell buffer based on the output cell buffer; and (nu) an output cell header addition unit that adds destination header information to cells output from the output cell buffer to the output port. (L) an output cell buffer monitoring unit for monitoring the accumulation state of the output cell buffer; and (ヲ) an input cell buffer. A selection output control unit for sequentially outputting the cells stored in the corresponding input cell buffers to the matrix switch based on the monitoring results of the viewing unit, the output cell buffer monitoring unit, the exchange buffer monitoring unit, and the service class information; And (f) a delay value counting unit that counts delay values based on monitoring results of the input cell buffer monitoring unit, the output cell buffer monitoring unit, and the exchange buffer monitoring unit.
A delay value allowance determining section for determining whether or not the delay value totalized by the delay value totaling section exceeds the delay time allowable value added by the input cell header information adding section; When it is determined that the delay value totalized by the delay value totaling unit exceeds the allowable delay time,
The ATM switch is provided with an input cell discarding unit for discarding cells input from the input cell header information adding unit to the input buffer based on the service class information.

That is, according to the third aspect of the present invention, the input buffer cells, the output buffer cells, and the matrix switches are provided with buffers corresponding to the output ports and the service classes, and the buffer accumulation state of each buffer is monitored. A monitoring unit is provided. Based on the accumulation state and the service class, the selection control of the cells output from the input cell buffer to the matrix switch is performed, and the input cells are added with an allowable delay time based on the header information in the input cell buffer. Then, the delay time calculated from the accumulation state of each buffer is compared, and the buffer exceeding the allowable delay time is discarded without being newly queued.

According to a fourth aspect of the present invention, in the ATM switch according to the third aspect, the selection output control unit exchanges a cell to be output to the matrix switch from the input cell buffer with an input cell buffer monitoring unit and an output cell buffer monitoring unit. It is characterized in that selection is made based on the monitoring result of the buffer monitoring unit and then fixedly selected based on the service class.

That is, in the present invention, the control for selecting and outputting from the input buffer is selected based on the accumulation state of each cell buffer, and then is fixedly selected according to the service class.

According to the fifth aspect of the present invention, in the ATM switch according to the third aspect, the service class information is information indicating whether it is a real-time system or a non-real-time system. It is a real-time communication cell.

That is, according to the fifth aspect of the present invention, a buffer provided for each service class can tolerate transfer data and a real-time system in which the allowable value of delay time is small. The size of the time is divided into non-real-time systems that do not matter so much, and the selection control of real-time data is prioritized.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to embodiments.

FIG. 1 shows an ATM switch according to an embodiment of the present invention.
It shows the outline of the configuration of the switch. This ATM
The switch is connected to the input cell 13₁, 13_Two, ..., 13_NBut
Input side cell buffer 10 to be input respectively₁, 10_Two,
…, 10_NAnd these input-side cell buffers 10₁, 10
_Two, ..., 10_NMatrix switch input output from
Force cell 14₁, 14_Two, ..., 14_NAre entered and these
Output port (not shown) corresponding to the cell destination
Matrix switch output cell 22₁, 22 _Two,…,
22_NAnd an output port
Matrix switch output cell before output to
22₁, 22_Two, ..., 22_NOutput side to queue
Cell buffer 30₁, 30_Two, ..., 30_NComposed of
ing.

The input-side cell buffers 10 ₁ , 10 ₂ ,.
The 10 _N, all of the output-side cell buffer 30 _1, 30 ₂ having a cell buffer for each service class and destination port corresponding to the output port, ..., an output cell storage level information 31 from 30 _N, output port The matrix switch queue information 21 from the N × N switch 20 having a buffer corresponding to each is input. Each of the input-side cell buffers 10 ₁ , 10 ₂ ,..., 10 _N has a buffer for each input cell service class and destination port, and stores input cell accumulation level information 11 indicating the accumulation state of each cell. The input cell accumulation level information of the input-side cell buffer other than the self-input-side cell buffer is input. For example,
Paying attention to each accumulation level information input / output to / from the input side cell buffer 10 ₁ , the output side cell buffer accumulation level information 32 ₁ , 32 ₂ ,..., 32 _N and the input side cell buffer accumulation level information 12 ₂ , 12 ₃ , ..., 12 _N are input, the input-side cell buffer storage level information 12 ₁ is that being output.

As described above, each cell buffer notifies each other of the storage cell level of the buffer, so that each cell buffer can grasp the queuing state of the cell on the path corresponding to the destination port of the cell to be transferred. Can be selected, and a cell to be output can be selected based on this situation. In addition, it is possible to calculate the delay value from the input cell reaching the output side cell buffer to the output side cell buffer based on the storage cell level of all the cell buffers, and this delay value is set to an allowable value set for each connection. Is exceeded, the cell to be input in the input side cell buffer is discarded without queuing.

FIG. 2 shows the input of the ATM switch shown in FIG.
This is a concrete representation of the main part of the configuration of the side cell buffer.
is there. Input side cell buffer 10₁, 10_Two, ..., 10_N
Cells for each service class and destination port
Configuration for priority control and discard control
Are basically the same, so that the input side cell buffer 10 ₁
Only the configuration of the other input-side cell buffer is illustrated.
Omitted, and the same parts as those in FIG.
And description thereof will be omitted as appropriate.

The cell input to the input side cell buffer 10 ₁ is input to the demultiplexer 43 via the header conversion unit 41 which converts the cell header information of the input cell 13 ₁ based on the input side connection table 42. I have. The header conversion unit 41 adds the switching information of the service class, the destination port number, and the internal connection number, and the permissible delay time of the cell. The demultiplexer 43 sorts the cell into a corresponding buffer based on the service class. Queued in the buffer.

This input-side cell buffer has a service class of a real-time system and a non-real-time system. Therefore, the input cells of the real-time system as the service class are input to the input cell buffers 45 ₁ , 45 ₂ ,
.., 45 _N and are queued. Non-real-time input cells are input cell buffers 46 ₁ , 46 ₂ ,.
.., 46 _N are inputted and queued. The storage cell level monitoring unit 48 includes a cell buffer 45 ₁ , 45 ₂ ,..., 45 _N , 46 ₁ , 46 ₂ ,.
Check the storage state of 6 _N, and outputs to the other input side cell buffer as an input-side cell buffer storage level information 12 _1. This storage cell level monitor 4
The feature of No. 8 is that the cell level for delay value control is used as a threshold value, and not only the cell level is notified to the control in the preceding stage in order to prevent the overflow of the conventional buffer, but also detected. Is a point.

FIG. 3 shows the input connection table shown in FIG.
The table configuration of the table 42 is shown.
The storage information 50 of the input side connection table is
Force cell 13₁"Virtual packet" in the header information of the ATM cell
Resource identifier-virtual channel identifier (VPI-VCI) "information
Information and the “destination port number” corresponding to the destination port of this cell.
No. ”and whether this cell is real-time data or not.
“Service class” that indicates whether the data is real-time data
Information and that this cell is real-time data
Time is acceptable without dropping queuing
"Allowable delay time" and the local
“In” corresponding to the output side cell buffer assigned to the
Part connection number ". Input side cell
Buffer 10 ₁Input cell 13 input to₁This is
In the header conversion unit 41 with reference to such a table,
“Destination port number” based on “VPI-VCI”,
"Service Class", "Delay Tolerance" and "Internal"
"Connection number" is newly added as header information
It has become.

The input-side cell buffer 10 ₁ stores output cell accumulation level information 32 ₁ , 3 as described above.
2 _2, ..., 32 _N and the input cell storage level information 12 _2, 1
2 _3, ..., 12 _N but is adapted to be input, performs aggregate delay value as a judgment material for performing discard control input cells from each of these storage level information in the delay value totaling unit 49 It has become. In the present embodiment, the accumulation level is added for each destination port. The discard control unit 44 compares the delay value with the permissible delay time of this cell added by the header conversion unit, and when the totaled delay value exceeds the permissible delay time, the discard control unit 44 sends the data to the corresponding input buffer. Discard as it is without performing queuing.

The selection output control unit 47 controls each input buffer 4
_{5 1, 45 2, ...,} 45 N, 46 1, 46 2, ..., 46
Cells from _N are input, and output cells are selected based on accumulated cell level information 31 of each output side cell buffer and matrix switch queue information 21 from the N × N switch 20. Also, based on the service class information, the real-time data 45 ₁ , 45 ₂ ,.
_N and non-real-time data 46 ₁ , 46 ₂ ,..., 46
_N is selected and output. In this input-side cell buffer, since only real-time or non-real-time service class information exists, real-time data in which real-time transfer data is important is fixedly selected.

FIG. 4 specifically shows the main part of the configuration of the output-side cell buffer of the ATM switch shown in FIG. Output side cell buffers 30 ₁ , 30 ₂ ,..., 30 _N
Configuration for priority control of the cell for each service class and destination port queuing to about because basically the same, shows only the output-side cell buffer 30 _1,
Illustration of other output side cell buffer configurations is omitted, and the same portions as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

The matrix switch output cell 22 ₁ input to the output side cell buffer is supplied to the demultiplexer 5.
1 in the input-side cell buffer based on the service class information added by each of the header conversion units described above.
Like the input-side cell buffer, the data is distributed to one of the real-time output buffer 52 and the non-real-time output buffer 53 and queued. The selection output control unit 54 selects and outputs the cell to be output based on the service class information in the header information of the cell to be output. The difference from the selection output control unit 47 of the input side cell buffer is that
The point is that only selection output based on service class information is performed. The storage cell level monitoring section 57 checks the storage state of each of the cell buffers 52 and 53 and outputs the output state as the output side cell buffer storage level information 32 ₁ to the input side cell buffer and the N × N switch 20. I have. The feature of the storage cell level monitoring unit 57 is that, in order to prevent the buffer overflow in the related art, not only the cell level is notified to the preceding control but also the cell level for delay value control is set as a threshold value. Is detected. That is, for the N × N switch 20,
This is a notification for preventing buffer overflow, and for an input-side cell buffer, for preventing buffer overflow and totalizing delay values.

The header conversion section 55 adds new transfer information to the header information of the ATM cell to be output to the output port based on the output side connection table 56 and outputs it.

FIG. 5 shows a table configuration of the output side connection table 56 shown in FIG. Storage information 58 of the output-side connection table is added at the input cell buffer in the header information of the matrix switch output cell 22 ₁ of the ATM cell "internal connection number" and corresponds to "VP
The cell output from the matrix switch is newly referred to in the header conversion unit 55 based on the "internal connection number" by referring to this table. Therefore, the transfer cell output from the output port of the ATM switch is referred to as “VP”.
It is routed based on the "I-VCI" information and is successively transferred to the destination transmission destination.

FIG. 6 shows an outline of the configuration of the N × N switch shown in FIG. This N × N switch 20
Are input cell buffers 10 ₁ , 1 as shown in FIG.
0 ₂ ,..., 10 _N and the output side cell buffers 30 ₁ , 3
0 _2, ..., 30 _N are disposed between, so as to switch the communication line between these cell buffer corresponding to the destination of the transfer cell. The N × N switch 20 also has buffers 61 ₁ , 61 ₂ ,.
1 _N , and the cell level is monitored by the cell accumulation level monitoring unit 62 of each buffer and output to the input side cell buffer. The matrix switch input cells 14 ₁ ,
14 _2, ..., 14 _S after being multiplexed through the multiplexing controller 60, a buffer 61 ₁ of the corresponding destination port, 61 _2,
..., it is queued in any of the 61 _N.

The cells input to the ATM cells are input to the input-side cell buffers 10 ₁ , 10 ₂ ,..., 10 _N based on the “VPI-VCI” of the header information of the input cells. The "service class", the "permissible delay time" and the "internal connection number" are added as cell header information, and are queued in buffers prepared for each "destination port number" and "service class" information. ing. In addition, the delay value totalizing section of each input side cell buffer outputs each output side cell buffer 30 ₁ ,
30 _2, ..., 30 delay value from the cell accumulation level information in the buffer of _N and N × N switch 20 is sequentially aggregated. The cell to be output for each destination port is selected and output from the cell accumulation level information of each buffer, and when the data to be newly queued can be discarded as in the case of real-time data, this delay value is used. When the value exceeds the allowable delay time added as header information, the input cell is discarded. The transfer cell output from the input side cell buffer is N
The × N switch 20 performs switching to the corresponding output port based on the “internal connection information” added by the input-side cell buffer, and is internally queued. The cell output from the N × N switch 20 is input to a corresponding output-side cell buffer, and is queued in a buffer prepared for each “service class” of the header information. When the data is finally output to the output port in this way, the header conversion section 55 adds a new "VPI-VCI" based on the "internal connection information" added by the input-side cell buffer and transmits the data. It has become.

[0039]

As described above, according to the first aspect of the present invention, the input buffer cell, the output buffer cell and the N × N
A switch is provided with a buffer corresponding to the output port,
A monitoring unit for monitoring the buffer accumulation state is provided for each buffer. Then, based on the accumulation state, selection control of cells output from the input cell buffer to the matrix switch is performed, and cells input to the input cell buffer are discarded without queuing. As a result, it becomes possible to perform cell discard control and priority control in the case of congestion based on the accumulation state with a simpler configuration than in the related art. In addition, since cells to be output in each cell buffer are determined, a complicated contention arbitration circuit for arbitrating output cells among a plurality of cell buffers is not required. It is possible to cope with an increase in the speed of an ATM switch port and an increase in the capacity of a buffer.

According to the second aspect of the present invention, the input buffer cell, the output buffer cell, and the matrix switch are provided with buffers corresponding to the output ports, and each of the buffers has a monitoring unit for monitoring the buffer accumulation state. It was provided. Based on the accumulation state, the selection control of the cell output from the input cell buffer to the matrix switch is performed, and the input cell adds an allowable delay time based on the header information in the input cell buffer. Compared with the delay time calculated from the accumulation state of each buffer, a buffer exceeding the allowable delay time is discarded without being newly queued. As a result, since cells to be output in each cell buffer are determined, a complicated contention arbitration circuit for arbitrating output cells among a plurality of cell buffers and a complicated discarded cell selection circuit are not required, which is simpler than in the past. In the case of congestion based on the accumulation state with a simple configuration, it becomes possible to perform cell discard control and priority control. In addition, it is possible to flexibly cope with data such as discarding input cell data that can be discarded at the time of congestion according to the traffic situation at the time of input from the allowable delay time for each queue that is input simply by changing the input connection table. Become like As a result, a comfortable service can be provided to the user at the same time as the early solution of the congestion.

According to the third and fifth aspects of the present invention, the input buffer cells, the output buffer cells, and the matrix switches are provided with buffers corresponding to the output ports and the service classes, and the buffers are stored in the respective buffers. A monitoring unit that monitors the status is provided. Based on the accumulation state and the service class, the selection control of the cells output from the input cell buffer to the matrix switch is performed, and the input cells are added with an allowable delay time based on the header information in the input cell buffer. Then, the delay time calculated from the accumulation state of each buffer is compared, and the buffer exceeding the allowable delay time is discarded without being newly queued. As a result, since cells to be output in each cell buffer are determined, a complicated contention arbitration circuit for arbitrating output cells among a plurality of cell buffers and a complicated discarded cell selection circuit are not required, which is simpler than in the past. In the case of congestion based on the accumulation state with a simple configuration, it becomes possible to perform cell discard control and priority control. Also, since the service class is added according to the storage information of the input side connection table, in the ATM switch of the ATM network in which the real-time system and the non-real-time system coexist, the discard at the time of congestion is determined from the permissible delay time for each input queue. It is possible to flexibly cope with such a case that data of an input cell that can be used is discarded according to the traffic situation at the time of input. As a result, a comfortable service can be provided to the user at the same time as the early solution of the congestion.

Further, in the invention according to the fourth aspect, the selection output control unit further includes a monitoring result of the input cell buffer monitoring unit, the output cell buffer monitoring unit, and the exchange buffer monitoring unit for outputting cells to be output to the matrix switch from the input cell buffer. ATM switch that performs priority control and discard control with a simpler configuration without deteriorating the quality of the service provided to the user because the selection is made fixedly based on the service class after selecting based on the service class. Will be able to

[Brief description of the drawings]

FIG. 1 is a block diagram showing an outline of an overall configuration of an ATM switch according to an embodiment of the present invention.

FIG. 2 is a block diagram specifically showing a configuration of an input-side cell buffer in the present embodiment.

FIG. 3 is a table configuration diagram showing stored contents of an input-side connection table in the present embodiment.

FIG. 4 is a block diagram specifically showing a configuration of an output-side cell buffer in the present embodiment.

FIG. 5 is a table configuration diagram showing storage contents of an output side connection table in the present embodiment.

FIG. 6 is a block diagram illustrating an outline of a configuration of an N × N switch according to the present embodiment.

FIG. 7 is a block diagram showing an outline of a configuration of a conventionally proposed ATM switch.

[Explanation of symbols]

10 ₁ to 10 _N input-side cell buffer 11 input cell accumulation level information 12 _{1 to} 12 _N input-side cell buffer accumulation level information 13 _{1 to} 13 _N input cell 14 _{1 to} 14 _N matrix switch input cell 20 N × N switch 21 matrix switch queue information 22 ₁ through 22 _N matrix switch output cells 30 ₁ to 30 _N output cell buffer 31 the output cell storage level information 32 ₁ to 32 _N output cell buffer storage level information 33 ₁ ~ 33 _N output cell 41 and 55 header Conversion unit 42 Input side connection table 43, 51 Demultiplexer 44 Discard control unit 45 _{1 to} 45 _N , 46 _{1 to} 46 _N , 52, 53 Cell buffer 47, 54 Selection output control unit 48, 57 Storage cell level monitoring unit 49 Delay Value tabulation unit 56 Output connection table 60 Multiplex control unit

Claims (5)

[Claims] An input port for inputting a communication cell; an output port for outputting the cell based on a destination of the cell input from the input port; and a destination of a cell input from the input port A matrix switch having an exchange buffer for connecting a line to the output port based on the input port and accumulating cells input from the input port for each output port, and an exchange buffer monitoring unit for monitoring the accumulation state of the exchange buffer An input cell buffer that accumulates a cell input from the input port corresponding to the output port based on the destination of the cell; an input cell buffer monitoring unit that monitors an accumulation state of the input cell buffer; An output cell buffer for storing cells output from the matrix switch for each output port; An output cell buffer monitoring unit that monitors a storage state of a buffer; an output cell header adding unit that adds header information serving as a destination to cells output from the output cell buffer to the output port; and an input cell buffer monitoring unit. A selection output control unit for sequentially outputting cells stored in the corresponding input cell buffer to the matrix switch based on monitoring results of the output cell buffer monitoring unit and the exchange buffer monitoring unit; An ATM switch, comprising: an input cell discarding unit that discards a cell input from the input port to the input buffer based on a monitoring result of the cell buffer monitoring unit. 2. An input port for inputting a communication cell, an output port for outputting the cell based on the destination of the cell input from the input port, and a destination of the cell input from the input port A matrix switch having an exchange buffer for connecting a line to the output port based on the input port and accumulating cells input from the input port for each output port, and an exchange buffer monitoring unit for monitoring the accumulation state of the exchange buffer Based on the header information of the destination of the cell, the cell input from the input port is used as the header information of the input cell with the allowable delay time set for each input cell buffer in which the input cell is stored. An input cell header information adding unit to be added, and a cell input from the input cell header information adding unit.
An input cell buffer that accumulates corresponding to the output port based on the destination of the input cell; an input cell buffer monitoring unit that monitors the accumulation state of the input cell buffer; and a cell output from the matrix switch for each output port An output cell buffer that accumulates in the output cell buffer; an output cell buffer monitoring unit that monitors the accumulation state of the output cell buffer; and an output that adds header information serving as a destination to cells output from the output cell buffer to the output port. A cell header adding unit, a selective output for sequentially outputting cells stored in the corresponding input cell buffer to the matrix switch based on monitoring results of the input cell buffer monitoring unit, the output cell buffer monitoring unit, and the exchange buffer monitoring unit. The control unit, the input cell buffer monitoring unit, the output cell buffer monitoring unit, and the exchange A delay value counting unit that counts the delay values based on the monitoring result of the monitoring unit; and whether the delay value counted by the delay value counting unit exceeds the allowable delay time added by the input cell header information adding unit. A delay value permissible discriminator that determines whether the delay value totaled by the delay value tabulator exceeds the delay time permissible value. An ATM switch, comprising: an input cell discarding unit for discarding cells input to the input buffer. 3. An input port for inputting a communication cell, an output port for outputting the cell based on the destination of the cell input from the input port, and a destination of the cell input from the input port A matrix switch having an exchange buffer for connecting a line to the output port based on the input port and accumulating cells input from the input port for each output port, and an exchange buffer monitoring unit for monitoring the accumulation state of the exchange buffer A cell input from the input port, based on the header information of the destination of the cell, whether the delay time allowable value set for each input cell buffer in which the input cell is stored and whether the cell can be discarded. An input cell header information adding unit for adding service class information indicating whether or not the input cell has header information to the input cell; The cells inputted from header information adding unit,
An input cell buffer that accumulates corresponding to each of the output ports based on the service class information and a destination of the input cell; an input cell buffer monitoring unit that monitors the accumulation state of the input cell buffer; An output cell buffer for storing cells to be output for each output port based on the service class information; an output cell selection control unit for selecting cells to be output from the output cell buffer based on the service class information; An output cell header adding unit for adding header information serving as a destination to a cell output from the cell buffer to the output port; an output cell buffer monitoring unit for monitoring the accumulation state of the output cell buffer; and an input cell buffer monitoring unit And output cell buffer monitoring unit and exchange buffer monitoring unit monitoring results and previous A selection output control unit for sequentially outputting cells stored in the corresponding input cell buffer to the matrix switch based on service class information; and an input cell buffer monitoring unit, an output cell buffer monitoring unit, and an exchange buffer monitoring unit. A delay value totalizing unit for totalizing the delay values based on the monitoring result; and determining whether the delay value totalized by the delay value totaling unit exceeds the allowable delay time added by the input cell header information adding unit. A delay value allowance determining unit, when the delay value allowance determining unit determines that the delay value totalized by the delay value totaling unit exceeds the delay time allowance value, the input cell header information based on the service class information; An input cell discarding unit for discarding cells input to the input buffer from the adding unit. Pitch. 4. The selection output control unit selects a cell to be output to the matrix switch from an input cell buffer based on monitoring results of an input cell buffer monitoring unit, an output cell buffer monitoring unit, and an exchange buffer monitoring unit. 4. The ATM switch according to claim 3, wherein a fixed selection is made based on a service class. 5. The service class information is information indicating whether it is a real-time system or a non-real-time system. What is discarded in the input cell discarding unit is a real-time communication cell. 4. The ATM switch according to claim 3, wherein the selected output is a real-time communication cell.