JPH11122196A - Optical reception circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an optical reception circuit by which an identification error of a large signal and a small signal is less. SOLUTION: This circuit is made up of a photodiode 1 that converts a burst optical signal into an electric signal, an amplifier 2 that amplifies the electric signal, a decision circuit that consists of an amplifier stage 3 and a peak detection circuit 4 and sets a decision level corresponding to the reception power, a reset circuit that restores a state of the decision circuit to an initial value before receiving the burst signal, and an identification circuit 10 having a hysteresis characteristic to identify the output from the decision circuit. The decision circuit is configured to be a multi-stage that is a pre-stage decision circuit 7 and a post-stage decision circuit 9 and after the initializing of the pre-stage discrimination circuit 7 is finished, the post-stage decision circuit 9 is initialized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD OF THE INVENTION

The present invention provides an optical receiving circuit adapted to a system for transmitting an optical signal in a burst. In particular, PDS (Passive) which is promising in optical subscriber system
The present invention relates to an optical receiving circuit suitable for receiving burst transmission in an optical transmission system having a double star configuration.

[0003]

2. Description of the Related Art In burst transmission in an optical subscriber system, it is necessary to detect the amplitude of each burst signal and determine the judgment level of an input signal based on the result. In this case, it is necessary to detect the peak value immediately after the burst signal is input and determine the determination level, and to balance the conflicting characteristics of maintaining the determination level. For this reason, even if one burst signal ends, there is a possibility that the determination level is held as it was before.

In a conventional receiving circuit which does not change the determination level once determined even when the burst signal is replaced, even if the one-level determination level is set according to the level of the input burst signal, the next input burst signal Is changed, the previously set determination level is not an appropriate determination level, and a determination error may occur.

A circuit block configuration of a conventional optical receiving circuit will be described with reference to FIG. The optical receiving circuit includes a photodiode 1 for receiving an optical burst signal, a preamplifier 2, a determination circuit 7 including an amplifier 3 including a differential amplifier, and a peak detector 4, and an identification circuit 10. It is configured. The peak detector 4 includes a buffer 5 and a peak value storage capacity 6.

In this optical receiving circuit, a signal current generated by the photodiode 1 based on the received optical signal is amplified to a signal voltage by the preamplifier 2 and input to the amplifier 3 and the peak detector 4 of the determination circuit 7.

The output signal of the preamplifier 2 input to the buffer 5 of the peak detector 4 charges the peak value storage capacitor 6 with its peak value. The output of the buffer 5, that is, the potential of the peak value storage capacitor 6 on the buffer 5 side is a value proportional to the peak value of the burst signal, and is output from the peak detector 4. The output of the peak detector 4 is input to a reference voltage input terminal of the differential amplifier 3 as a reference voltage. The differential amplifier 3 actually amplifies the output signal of the preamplifier 2 based on half the peak value. This allows
The determination circuit 7 reproduces the received signal based on the amplitude of the received signal centered on half of the amplitude.

Further, the output of the determination circuit is finally identified by the identification circuit 10 into "1" and "0" signals.

In this circuit configuration, the reference voltage corresponding to the signal amplitude charged by the first burst signal is used as a reference when the subsequent signal is determined by the determination circuit 7. When the amplitude of the received signal changes in this state, the changed signal is amplified by the determination circuit 7 based on the reference voltage before corresponding to the changed amplitude of the received signal. The waveform of the output signal will be distorted. Such a situation, P
This occurs when a plurality of burst signals having different transmission distances are handled in transmission in an optical transmission system having a DS configuration. For example, FIG.
0, a burst 1 is input as a large signal (about -10 dBm) Vb ₁ as a first signal, and a next burst 2
Is input as a small signal (about −30 dBm) Vb ₂ , the level Vb ₁ of burst ₁ and the level Vb _{2 of} burst ₂
Is large, and the signal level of burst 2 is burst 1
Because the voltage is extremely lower than the reference voltage Vr ₂ set from the peak value of, the signal may not be amplified and may disappear.

[0010]

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problem by providing an optical receiving circuit for burst transmission using an optical transmission system having a PDS configuration, which is expected to be used in an optical subscriber system. It is an object of the present invention to provide an optical receiving circuit that prevents an error in signal level determination for input signals having different levels.

[0011]

To solve this problem, the present invention provides a light receiving diode for converting an optical signal into an electric signal, an amplifier for amplifying the electric signal, and a determination level corresponding to the received power. In an optical receiving circuit comprising a determination circuit for setting, a reset circuit for returning the state of the determination circuit for setting a determination level to an initial value before receiving a signal, an output from the determination circuit for setting the determination level and an input signal A comparison circuit having a hysteresis characteristic for comparing outputs is provided, and a circuit for setting a judgment level of an optical receiving circuit before an input optical burst signal is input is set to set a judgment level for each input burst signal. To solve the problem.

[0012]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a diagram showing a circuit block configuration of an optical receiving circuit according to the present invention. This optical receiving circuit is characterized in that a reset circuit 8 is added as compared with the conventional optical receiving circuit shown in FIG. Blocks assigned the same numbers as the blocks shown in FIG. 9 have similar functions. That is, the optical receiving circuit according to the present invention includes the photodiode 1, the preamplifier 2, and the amplifier 3
And a peak detector 4, a reset circuit 8, a second determination circuit 9, and an identification circuit 10.

The photodiode 1 receives the optical burst signal and outputs a current signal having a level proportional to the level of the optical signal. The preamplifier 2 converts the current signal from the photodiode 1 into a voltage signal having a level proportional to the level of the current signal, and inputs the voltage signal to the first determination circuit 7. The first determination circuit 7 includes an amplifier 3 composed of a differential amplifier and a peak detector 4, and the peak detector 4 includes a buffer 5 and a peak value storage capacitor 6. The first determination circuit 7 determines whether the value of the input burst signal is “0” or “1” using half of the peak value of the input signal as a reference value, Outputs a binary signal. The identification circuit 10 determines that the value of the input signal is “0”.
Or “1”. First judgment circuit 7
And the second determination circuit 9 are connected in multiple stages, and the output of the first determination circuit 7 is input to the second determination circuit 9.

FIG. 2 shows a circuit configuration of the peak detector 4.
The peak detector 4 includes a signal input terminal, a buffer 5 composed of an operational amplifier, a peak value storage capacitor 6, a first transistor 41, a second transistor 42, a third transistor 43, and a fourth Transistor 44 and resistor 4
5, a resistor 46, a constant voltage source 47, a positive power supply terminal, and an output terminal.

The first transistor 41, the second transistor 42, and the third transistor 43 all have N
A PN transistor is used. Fourth transistor 4
4 uses a PNP transistor.

The signal input terminal is connected to the first
Is connected to the base of the transistor 41. The collector of the first transistor 41 is connected to a positive power supply via a positive power supply terminal, and the emitter is connected to one end of the peak value storage capacitor 6 and the base of the second transistor 42. The other end of the peak value storage capacitor 6 is grounded. The collector of the second transistor 42 is connected to the base of the fourth transistor 44 via a resistor 46, and the emitter is the output terminal and the collector of the third transistor 43 and the collector of the fourth transistor 44 and the reference voltage of the buffer 5. Connected to input terminal. Third transistor 4
The base of 3 is connected to a constant voltage source 47, and the emitter is grounded via a resistor 45 to form a constant current source. The emitter of the fourth transistor 44 is connected to a positive power supply via a positive power supply terminal.

The output terminal of the reset circuit 8 is connected to the peak value storage capacitor 6 of the peak detector 4 provided in the first determination circuit 7 and the second determination circuit 9. , A reset signal is input at each break of the burst signal. When the reset signal is input, the reset circuit 8 operates to extract the electric charge of the peak value storage capacitor 6. By this operation, the peak value storage capacity 6 of the peak value detector 4 is initialized, and the peak value of the next input burst signal is further detected. Therefore, the amplifier 3 of the first determination circuit 7 can amplify the input signal based on the reference voltage based on the updated peak. In this system, since the center station of the transmission system determines the transmission / reception timing of the burst signal, the logic processing unit of the optical receiving circuit generates a reset signal based on the timing, and the reset circuit 8 automatically operates based on the reset signal. It is possible to know the break of the burst signal.

A specific circuit configuration of the reset circuit 8 will be described with reference to FIG. The reset circuit 8 includes an input terminal, a plurality of transistors 82-1 to 82-12, a plurality of resistors 83-1 to 83-14, two capacitors 84-1,
84-2.

When the level of the input burst signal is low, the first determination circuit 7 among the determination circuits 7 and 9 connected in multiple stages simply functions as an amplifier circuit, and the second determination circuit 9 is input. The burst signal "0" or "1" is determined. When the input burst signal level is high,
First determination circuit 7 of determination circuits 7 and 9 connected in multiple stages
Work as a judgment circuit, and the second judgment circuit 9 works as a waveform shaping circuit.

The detailed block configuration of the determination circuit according to the present invention will be described with reference to FIG. Each of the determination circuit 7 and the determination circuit 9 is composed of two systems of a positive phase and a negative phase, and the identification reference voltage Vr formed by the peak value detector 4.
Amplify the input signal around. By configuring the determination circuit with two systems of the normal phase and the negative phase in this way, the reference voltage for identification Vr can be set to an intermediate value between the “0” level and the “1” level of the input signal. The amplifier 3 includes a positive-phase differential amplifier 31s, a negative-phase differential amplifier 31r, and an amplifier 32 that outputs a positive-phase output and a negative-phase output. The peak detector 4 includes a positive-phase buffer 5s, a positive-phase peak value storage capacitor 6s, a positive-phase transistor 41s that short-circuits the terminals of the positive-phase peak value storage capacitor, and a negative-phase buffer 5r. And a reverse-phase peak value storage capacity 6r,
A negative-phase transistor 41r for short-circuiting the terminals of the negative-phase peak value storage capacitor. The base of each transistor is connected to the output of the reset circuit 8.

FIG. 5 shows a specific circuit configuration of the amplifier 3 of the determination circuit 1. The amplifier 3 is a positive-phase differential amplifier 31s.
, A negative-phase differential amplifier 31r, an amplifier 32 that outputs a positive-phase output and a negative-phase output, and a constant current source 319 including, for example, a constant voltage source, a switching transistor, and a resistor. The positive-phase differential amplifier 31s and the negative-phase differential amplifier 31r have the same configuration, and transistors 311, 3
12,317 and resistors 313,314,315,31
6 and 318 are connected as shown. The amplifier 32 includes four transistors 321 to 324
, Resistors 325 to 328, and constant current sources 329-1 and 32
9-2 and 329-3 are connected as shown in the figure.

The operation of this circuit will be described with reference to FIGS. When the burst signal 1 is inputted, the peak value detecting circuit 4 charges the peak value storage capacitor 6 voltage proportional to the peak value Vb ₁ of the burst signal 1, the terminal voltage as an identification reference voltage Vr ₁ Output. The amplifier 3 identifies the level of the input burst signal 1 by using the identification reference voltage Vr ₁ and outputs a shaped signal. When the burst signal 1 ends, a reset signal having a predetermined pulse width created by detecting a break from the phase or the like is input to the reset circuit 8 via the reset signal terminal 81. Then, the reset circuit 8 raises the output voltage, sets the transistor 41 to the operating state for a predetermined time, and short-circuits the terminals of the peak value storage capacitor 6. The electric charge stored in the peak value storage capacitor 6 is supplied to the ground via the transistor 41 during this time, and the peak value storage capacitor 6 is initialized.

In the state thus initialized, the level Vb ₂
Is input, the peak value detection circuit 4
Charges the peak value storage capacitor 6 voltage proportional to the peak value Vb ₂ of the burst signal 2 and outputs the terminal voltage as an identification reference voltage Vr _2. Amplifier 3 outputs a signal obtained by shaping the level of the burst signal 2 inputted by using the identification reference voltage Vr ₂ identify and.

With the above operation, the burst signal is always amplified based on the reference voltage corresponding to the amplitude of the input burst signal, and a correct determination is made.

First judgment circuit 7 and second judgment circuit 9
Are set differently for each stage, so that the initialization of the second determination circuit 9 is performed after the initialization of the first determination circuit 7 is completed.

As shown in the input / output characteristics of FIG. 7, the discriminating circuit 10 has a hysteresis characteristic, and once discriminating "0", the discriminating circuit 10 outputs "1" unless a signal having a magnitude larger than a predetermined value is input. ".

FIG. 8 shows a specific circuit configuration of the identification circuit 10. The identification circuit 10 includes ten transistors 101-
1 to 101-10 and seven resistors 102-1 to 102-
7 and constant current sources 103-1 to 103-5 are connected as shown in the figure.

This has the effect of amplifying noise in a no-signal section between bursts and outputting an unnecessary signal in burst transmission, thereby preventing an error in subsequent processing.

[0029]

According to the present invention having the above-described configuration, in burst transmission in an optical transmission system having a PDS configuration, appropriate burst signals are transmitted to a plurality of terminals having different transmission distances. A determination process can be performed based on the level, and burst signals from a plurality of terminals having different reception levels can be determined according to the levels of the respective burst signals and can be accurately received.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram illustrating an embodiment of an optical receiving circuit according to the present invention.

FIG. 2 is a circuit diagram showing a specific circuit configuration of a light receiving circuit detector according to the present invention.

FIG. 3 is a circuit diagram showing a specific circuit configuration of a reset circuit for an optical receiving circuit according to the present invention.

FIG. 4 is a block diagram showing a detailed configuration of an optical receiving circuit determination circuit according to the present invention.

FIG. 5 is a circuit diagram showing a specific circuit configuration of an optical receiver circuit amplifier according to the present invention.

FIG. 6 is an operation time chart of the optical receiving circuit according to the present invention.

FIG. 7 is a diagram illustrating input / output characteristics of an identification circuit of the optical receiving circuit according to the present invention.

FIG. 8 is a circuit diagram showing a specific circuit configuration of an identification circuit for an optical receiving circuit according to the present invention.

FIG. 9 is a circuit block diagram of a conventional optical receiving circuit.

FIG. 10 is an operation time chart of a conventional optical receiving circuit.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 light receiving diode (photodiode) 2 preamplifier 3 amplifier 4 peak detector 5 buffer 6 peak value storage capacity 7 judgment circuit 8 reset circuit 9 judgment circuit 10 identification circuit

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H03F 3/08 (72) Inventor Makoto Nakamura 3-2-1, Nishishinjuku, Shinjuku-ku, Tokyo Nippon Telegraph and Telephone Corporation (72) Inventor Noboru Ishihara Nippon Telegraph and Telephone Corporation 3-1-2, Nishi-Shinjuku, Shinjuku-ku, Tokyo (72) Inventor Yukio Akazawa 3-2-1, Nishi-Shinjuku, Shinjuku-ku, Tokyo Nippon Telegraph and Telephone Corporation

Claims (5)

[Claims] 1. An optical receiving circuit comprising a light receiving diode for converting an optical signal into an electric signal, an amplifier for amplifying the electric signal, and a judging circuit for setting a judging level corresponding to the received power, sets a judging level. A reset circuit for returning a state of the determination circuit to an initial value before receiving a signal; and an identification circuit having a hysteresis characteristic for identifying an output from the determination circuit for setting the determination level, and setting the determination level. An optical receiving circuit characterized in that an output from a determination circuit is identified by an identification circuit having hysteresis characteristics. 2. The optical receiving circuit according to claim 1, wherein
An optical receiving circuit in which decision circuits for setting a decision level are connected in multiple stages. 3. The optical receiving circuit according to claim 2, wherein
An optical receiving circuit in which the timing of initializing a decision circuit for setting a decision level connected in multiple stages is changed according to each stage. 4. The optical receiving circuit according to claim 3, wherein
An optical receiving circuit in which the timing of initializing the judgment circuits for setting the judgment levels connected in multiple stages is changed so that the initialization of the next stage is performed after the initialization of the previous stage is completed. 5. The optical receiving circuit according to claim 1, wherein the determining circuit for setting the determining level includes an amplifying stage and a peak detecting circuit.