JPH10209825A - Threshold value control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the generation of the deviation of a threshold level, and to identify a non-signal by outputting a level held higher than a non-signal level only by a forced offset value at the time of inputting no signal, and outputting the voltage-division value of signal amplitude as a threshold level when the input signal level is more than a prescribed value. SOLUTION: A peak detecting circuit 10 with a dead zone outputs a level almost equal to a non-signal level at the time of inputting no signal, and when the level of the input signal is more than a prescribed value, the circuit 10 outputs a 1 side output level lower only by level shift amounts equal to VOF×[(R1 +R0 )/R0 ]. In this case, the VOF indicates a forced offset value, and the R0 and R1 indicate resistance values. A voltage dividing circuit operate voltage division at R1 :R0 to 1 side and 0 side output levels, and a level shift circuit 12 outputs a level held higher than the non-signal level only by the forced offset value VOF at the time of inputting no signal, and outputs the voltage-division value at the R1 :R0 of signal amplitude as a threshold level when the level of the input signal is more than a prescribed value.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a threshold value control circuit for identifying the logic of a signal in a signal amplifier circuit for reproducing a pulse signal.

A signal amplifier circuit for reproducing a pulse signal from a weak analog signal is required to support a wide input dynamic range. For such a request,
By using an automatic threshold control (ATC) circuit for setting a threshold level at the center between the 1-side level and the 0-side level of the input signal and a limiter amplifier, a good output waveform can be obtained over a wide input dynamic range. Is known to be.

When an automatic threshold circuit is used, the threshold level when no signal is input coincides with the no-signal level. However, if noise is input in this state, noise will be generated at the output.

In order to identify a no-signal, a forced offset is added to uniformly shift the threshold level.
When the input level is low, the threshold level shift becomes a relatively large value, so that there is a problem that a sufficient eye opening cannot be obtained.

[0005] Therefore, an automatic threshold circuit is required which can identify no signal without deteriorating the eye opening.

[0006]

2. Description of the Related Art FIG. 21 is a block diagram of a conventional example, and FIG.
1 is an operation explanatory diagram, and FIG. 23 is another operation explanatory diagram of FIG. 22 and 23 indicate waveforms of the same reference numerals in FIG.

Hereinafter, the operation of FIG. 21 will be described with reference to FIGS. 22 and 23 in which the input signal is a positive-phase unipolar code. In FIG. 21, reference numeral 90 denotes a peak detection circuit that outputs the 1-side level of the input signal, 91 denotes a reference voltage generation circuit that outputs the 0-side level of the input signal, 92 denotes a level shift circuit, and 93 denotes a 1/2 voltage generation. The circuit 94 is a limiter amplifier circuit.
The automatic threshold control (ATC) circuit includes a peak detection circuit 90, a reference voltage generation circuit 91, a level shift circuit 9
It comprises a 2, 1/2 voltage generating circuit 93.

First, the operation of the automatic threshold control circuit shown in FIG. 21 will be described with reference to FIG. Reference voltage generation circuit 9
The reference level corresponding to the 0-side output level sent by 1 (
Is shifted by 2V _OF (V _OF is a forcible offset value) in the level shift circuit 92 and is converted into a shift reference level (see).
The voltage is applied to one end of the voltage generation circuit 93.

On the other hand, the peak detection circuit 90 detects the 1
The side output level is detected, and the first side output level (corresponding to the peak detection level in the figure) is applied to the other end of the half voltage generating circuit 93 (see).

Therefore, the 1/2 voltage generating circuit 93 adds (see) the threshold level obtained by taking 1/2 of (shift reference level + 1 side output level) to the limiter amplifier circuit 94 (see). The threshold level is higher by V _OF than the threshold level without the level shift circuit.

The dotted line portion of the peak detection level in FIG. 22 is the one-side level, and the one-dot chain line overlapping the dotted line indicates the output of the peak detection circuit, but these levels match.

Next, the waveform response characteristics of the signal amplifier circuit composed of the above-mentioned automatic threshold value control circuit and limiter amplifier circuit will be described with reference to FIG. 23. The "input waveform" in FIG. The case where the signal amplitude is small and the case where the signal amplitude is large are shown, and the rising part of the “ATC part waveform” matches the output level of each part in FIG.

The limiter amplifier 94 in FIG. 21 to which the above-mentioned threshold level is applied performs limiter amplification centering on the threshold, and as shown in FIG. 23, the input level is lower than the threshold level. When it is high, the 1-side output level is reproduced, and when it is low, the 0-side output level is reproduced.

That is, the level shift causes the threshold level at the time of no signal to be higher than the no signal level by the forced offset of V _OF . The value of V _OF is designed to be sufficiently larger than the noise, so that no noise is generated in the output even when there is no signal.

[0015]

The threshold level is ideally in the middle of the input signal. However, as described above, the threshold level is uniformly shifted regardless of the presence or absence of the input signal. As is clear from FIG. 22, the threshold level at the time of signal input is also the forced offset value V from the center of the signal amplitude.
Only _OF shifts to the 1 level.

[0016] On the other hand, the signal amplifying circuit, there is a request to play a very small input signal levels of the same order as the V _OF to correspond to the wide dynamic range. In the case of amplifying such a small input level, the shift of the threshold level due to the forced offset becomes relatively large, causing a problem that a sufficient eye opening cannot be obtained at the output.

It is clear that the problem is that the threshold level is greatly deviated from the center of the input amplitude at the location indicated by "minimum reception level" in FIG. Although this problem can be solved by reducing the forced offset value according to the input amplitude, there is a limit to the reduction because the forced offset is a value determined from the noise level.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a threshold control circuit which does not cause a shift in the threshold level at a signal level to be received and can identify a non-signal.

[0019]

According to a first aspect of the present invention, an input signal is provided.
Send out the 0 side output level which is almost equal to the 0 side level of the signal
0 side output level sending circuit and no signal level when no signal is input
Output level approximately equal to the
Is a preset value V₁In the above case, one side of the input signal
Almost V _OF× [(R₁+ R₀) / R₀]
Equal level shift amount V_SHOnly one side output level
Peak (bottom) detection with dead zone that outputs bell
Circuit, for the 1-side output level and the 0-side output level
R₁: R₀Partial pressure to obtain the threshold level
A circuit and the 1-side output level or the 0-side output level;
Or a level that shifts the level to the threshold level
And a shift circuit.

When there is no signal input, the level maintained substantially higher than the no-signal level by the forced offset value V _OF, and when the level of the input signal is equal to or higher than the preset value V ₁ , the signal amplitude R ₁ : The configuration is such that the partial pressure value of R ₀ is output as a threshold level.

According to a second aspect of the present invention, there is provided a 0-side output level sending circuit for sending a 0-side output level substantially equal to the 0-side level of an input signal, and R ₁ : R for the input signal level and the 0-side output level. _A voltage dividing circuit that performs a voltage dividing of ₀ to obtain a divided voltage signal,
Using the divided signal, when no signal is input, a level that is substantially higher than the no-signal level by the forced offset value V _OF is output, but when the level of the input signal is equal to or higher than a preset value V ₁ , the signal is output. A peak (bottom) detection circuit having a dead zone for outputting, as a threshold level, a level lower than the one-side level of the input signal by a level shift amount V _SH substantially equal to the forcible offset value V _OF ; Or the said 0
A level shift circuit for performing a level shift with respect to the side output level or the threshold level.

When there is no signal input, the level maintained substantially higher than the no-signal level by the forced offset value V _OF, and when the level of the input signal is equal to or higher than the preset value V ₁ , the signal amplitude R ₁ : The configuration is such that the partial pressure value of R ₀ is output as a threshold level.

According to a third aspect of the present invention, there is provided a zero-side output level transmitting circuit for transmitting a zero-side output level substantially equal to the zero-side level of the input signal;
_A level higher by a level shift amount V _SH equal to _OF × [(R ₁ + R ₀ ) / R ₀ ] is output. However, when the level of the input signal is equal to or higher than a predetermined value V _{1, one} level of the input signal is output. A level shift peak (bottom) detection circuit having a dead zone for outputting a first output level substantially equal to the first level;
R ₁ : R for the 1-side output level and the 0-side output level
_A voltage dividing circuit for dividing the voltage by ₀ to obtain a threshold level.

When there is no signal input, the level is higher than the no signal level.
Also almost V_OFLevel, but the level of the input signal
Bell is a preset value V₁In the above case, the signal amplitude
R₁: R ₀Output the partial pressure value as the threshold level.
I made it.

According to a fourth aspect of the present invention, there is provided a zero-side level transmitting circuit for transmitting a zero-side output level substantially equal to the zero-side level of the input signal, and R ₁ for the input signal level and the zero-side output level. : A voltage dividing circuit for dividing the voltage of R ₀ to obtain a divided signal, and outputting a level higher than the no signal level by a level shift amount V _SH substantially equal to the forced offset value V _OF when there is no signal input. The level of the input signal is a preset value V
When the value is ₁ or more, a peak (bottom) detection circuit having a dead zone for outputting a level substantially equal to the one-side level of the divided signal as a threshold level is provided.

When there is no signal input, the level is higher than the no signal level.
Also almost V_OFLevel, but the level of the input signal
Bell is a preset value V₁In the above case, the signal amplitude
R₁: R ₀Output the partial pressure value as the threshold level.
I made it.

In the fifth invention, the ratio R ₁ : R ₀ is 1: 1. In a sixth aspect of the present invention, the level shift peak (bottom) detection circuit having the above-mentioned dead zone is constituted by a differential amplifier circuit, a rectifying element, and a capacitor for holding a detection value.

Then, with respect to the threshold voltage _Vth of the rectifying element, the gain A of the differential amplifier circuit is substantially equal to A = ( _Vth / V
_SH ) -1 to provide a dead zone substantially equal to the voltage V _SH .

According to a seventh aspect of the present invention, there is provided a level shift peak (bottom) detecting circuit having the above-mentioned dead zone, comprising a differential amplifier circuit, a rectifying element, a capacitor for holding a detected value, and a level provided in a feedback loop. It is composed of a shift circuit.

Then, with respect to the threshold voltage _Vth of the rectifying element, the gain A of the differential amplifier circuit is substantially set to A = ( _Vth / V
_SHSH ) -1 to control the level shift amount V _SH
A dead zone almost equal to is provided.

According to an eighth aspect of the present invention, a level shift peak (bottom) detection circuit having the above-described dead zone is provided in a differential amplifier circuit, a rectifier, a capacitor for holding a detection value, and a feedback loop. It is composed of a level shift circuit that can be turned on / off by a signal.

Then, the level shift is performed in a standby state before a signal is input, and the level shift is turned off in a signal receiving state to hold the detected value, whereby the level shift amount V
_A dead zone almost equal to _SH is provided.

In a ninth aspect of the present invention, in a signal amplifier circuit for reproducing a pulse signal from an input signal, a threshold control circuit and a differential amplifier circuit are connected in multiple stages, and the final stage threshold control circuit is claimed. The threshold control circuit according to any one of claims 1 to 9 is used.

According to a tenth aspect of the present invention, in the signal amplifying circuit for reproducing a pulse signal, an output side of a preamplifier for current-to-voltage conversion of a current signal from the photoelectric conversion element is provided.
To the threshold control circuit according to claim 9.

Here, the principle of the present invention will be described with reference to FIGS. FIG. 2 shows a change in each output of the peak detection circuit 10, the reference voltage generation circuit 11, the level shift circuit 12, and the 1/2 voltage generation circuit 13 with respect to a change in the amplitude of the input signal.

The point that the level is shifted by 2V _OF to the 0-side output level output from the reference voltage generating circuit 11 is the same as the conventional example. However, the peak detection circuit sends a 1-side output level 10 did not respond in the dead zone of the input amplitude to 2V _OF, approximately 2V _OF than 1 side output level above 2V _OF
Outputs the peak detection level lower by the amount. Then, by taking 1/2 of the above two levels (shift reference level and peak detection level), a threshold level is obtained.

By providing the above-mentioned dead zone, as is apparent from FIG. 2, the threshold level in the no signal is higher than the no signal level by the forced offset value V _{OF with} respect to the reception level larger than 2V _OF. Alternatively, the threshold can be set at the center of the amplitude of the input signal.

Now, a peak detecting circuit having a dead zone (hereinafter referred to as a peak detecting circuit with a dead zone) will be described with reference to FIG. 1 which is an embodiment of the present invention. 102, a capacity 103, and a buffer 104.

Here, the operation of the peak detection circuit will be analyzed. The operation of the differential amplifier circuit 101 is determined by the following equation. V _amp = V ₀ + A (V _IN −V _OUT ) (1) where V _amp is the output voltage of the differential amplifier circuit, V _IN is the positive-phase input voltage of the differential amplifier circuit, and V _OUT is the peak detection output, that is,
A negative-phase input voltage of the differential amplifier circuit, V ₀ is an output operating point, and A is a gain.

First, the DC state is analyzed. Assuming that no voltage remains at both ends of the diode, the following relational expression is derived in a DC state. The buffer is assumed to be, for example, an emitter follower circuit, and has a gain of 1 and an input / output DC level difference of V
_BF .

V _amp = V _OUT + V _BF (2) That is, the following DC state equation is obtained from the equations (1) and (2).

[0042]

(Equation 1) Here, V _{IN (DC)} is the input level when there is no signal, V _{OUT (DC)}
Is the output level at that time, and it is assumed that V _{OUT (DC)} and V _{IN (DC)} match sufficiently well.

Next, the state in which the peak level is maintained will be analyzed. When a signal having an amplitude V _{IN (PP)} is input and a voltage equal to or higher than the threshold voltage V _th is applied to both ends of the diode,
The diode 102 is turned on to perform peak detection. The condition is approximately expressed by the following equation.

A × V _{IN (PP)} > V _th (4) On the contrary, at a voltage lower than this, the peak detection circuit 10 holds the DC level V _{OUT (DC)} .

Since the peak detection stops when the threshold voltage V _th remains at both ends of the diode 102, the following relational expression is derived for the output voltage V _OUT in the peak level holding state.

V _amp = V _OUT + V _BF + V _th (5) That is, when the level is input, the amplitude of V _{IN (PP)} is expressed by (1),
From the equations (4) and (5), the following equation of the peak level holding state is obtained.

[0047]

(Equation 2) Incidentally, a case of (6) ₁ formula is V _{IN (PP)>} For (V _th / A), (6) ₂ formula is _{V IN (PP) ≦ (V} th / A). From equation (6), the peak detection circuit is essentially V _th / (A +
It can be seen that there is a dead zone of 1) and no response is made with an input amplitude smaller than this. This is the characteristic shown in FIG. 2, but the present invention actively uses this characteristic.

Specifically, the gain A is designed in accordance with the values of V _th and V _OF , and the compression error is made equal to 2V _OF to obtain the gain A shown in FIG.
The characteristics of are realized. The gain is given by the following equation. A = (V _th / 2V _OF ) −1 (7) For example, when V _th = 800 mv and V _OF = 20 mv, the gain A = 19
It should be designed as double.

The gain is a parameter that can be sufficiently designed, and this degree of matching is possible. However, when the gain is low, the error with respect to the signal component V _{IN (PP)} of the second term of the equation ( _{1 )} also increases, but the error of A / (A + 1) is small (in the above numerical example, the error is 5%). There is no.

As described above, according to the present invention, by providing a dead zone in the peak detection circuit, the threshold level is higher than the no-signal level by the forced offset when there is no signal, and the threshold level is higher at the input level to be received. Characteristics such that the level is at the center of the signal amplitude can be realized.

[0051]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows the first and sixth embodiments of the present invention.
2, FIG. 2 is an explanatory diagram of the operation of FIG. 1, FIG. 3 is another explanatory diagram of the operation of FIG. 1, and FIG.
5, FIG. 5 is an operation explanatory diagram of FIG. 4, FIG. 6 is another operation explanatory diagram of FIG. 4, FIG. 7 is a configuration diagram of the second and sixth embodiments of the present invention, and FIG. FIG. 8 is an operation explanatory diagram of FIG. 7.

FIG. 9 is a block diagram of the third and seventh embodiments of the present invention, FIG. 10 is an explanatory diagram of the operation of FIG. 9, and FIG.
FIG. 12 is a diagram illustrating the operation of the tenth embodiment of the present invention, FIG. 12 is a diagram illustrating the operation of FIG. 11, FIG. 13 is another diagram illustrating the operation of FIG. 11, and FIG. FIG. 15 and FIG.
It is operation | movement explanatory drawing of FIG.

FIG. 16 is a block diagram of the third and eighth embodiments of the present invention, FIG. 17 is an explanatory diagram of the operation of FIG. 16, and FIG. 18 is a block diagram of the fourth, eighth and eleventh embodiments of the present invention. FIG. 19 and FIG.
20. FIG. 20 is another operation explanatory diagram of FIG.

Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1 to 20. The parts described in detail above will be described briefly, and the parts of the present invention will be described in detail. In addition,
According to the present invention, as described in detail above, a dead zone is provided in a portion lower than the minimum reception level, and after passing the dead zone, the peak detection circuit with a dead zone outputs an output of (1 side output level -2V _OF ). Thereby, the threshold level applied to the limiter amplifier circuit is always at the center of the amplitude of the input signal.

First, the operation of FIG. 1 will be described with reference to FIGS. 2 and 3 indicate the levels of the same reference numerals in FIG. Here, 10 in FIG. 1 is a peak detection circuit with a dead zone for detecting the output level on one side of the input signal, 11 is a reference voltage generation circuit for outputting a reference level as the output level on the 0 side of the input signal, and 12 is a level shift circuit , 13 are 1/2 voltage generating circuits, and 14 is a limiter amplifier circuit.

FIG. 1 shows a configuration in which a level shift circuit 12 is provided outside a peak detection circuit 10 having a dead zone, and a peak detected output is applied to a 1/2 voltage generation circuit 13.

Further, peak detection circuits 10-1 with dead zones
/ 2 voltage generation circuit 13 uses an automatic threshold control circuit
(Abbreviated as ATC circuit). Well, ATC
The level shift circuit 12 in the circuit includes the reference voltage generation circuit 1
The reference level transmitted by 1 (corresponding to the output level on the 0 side) is 2
The level is shifted by V _OF , and 1 is set as the shift reference level.
The voltage is applied to the other end of the / 2 voltage generating circuit 13 (see, in FIGS. 1 to 3).

On the other hand, since one end of the voltage generating circuit 13 is applied with the peak detection level from the peak detection circuit 10 having a dead zone (that is, the one-side output level), １ ／ of the level applied to both ends is applied. The threshold level can be obtained by taking the threshold level.
4 (see FIGS. 1 to 3).

The limiter amplifier 14 performs limiter amplification centering on the applied threshold level. However, as shown in FIGS. 2 and 3, the threshold is set at the center of the amplitude of the input signal. As shown in FIG. 3, the pulse signal can be reproduced without error.

As described above in detail, the gain of the differential amplifier circuit 101 of the peak detection circuit with dead zone 10 is designed to be approximately (V _th / 2V _OF ) −1, and the level shift amount V
_SH is approximately equal to 2V _OF .

That is, as shown in FIG.
0 means no response up to 2V _OF input amplitude and 1 at 2V _OF or more
Outputs a level approximately 2 V _OF lower than the side level. As described above, by performing the level shift, the threshold level at the time of no signal is higher than the no signal level by the forced offset value V _OF . The value of V _OF is designed to be sufficiently larger than the noise, so that no noise is generated in the output even when there is no signal.

Since the dead band is provided in the peak detection circuit, the threshold level is set at the center of the amplitude at an input amplitude of 2 _VOF or more, so that the eye opening does not deteriorate.
When the input signal is a reverse-phase signal, a dead zone is provided in the bottom detection circuit.

Next, the operation of FIG. 4 will be described with reference to FIGS. In FIG. 4, reference numeral 20 denotes a peak detection circuit that outputs an input 0-side level, 21 denotes a bottom detection circuit with a dead zone that outputs an input 1-side level, 22a denotes a level shift circuit, and 22b denotes a 1/2 voltage generator. The circuit 23 is a limiter amplifier circuit, and the peak detection circuit 20 to the 1/2 voltage generation circuit 22 constitute an ATC circuit.

In FIG. 4, as in FIG. 1, a level shift circuit 22a is provided outside the peak detection circuit 20 with a dead zone, and a peak detected output is applied to a 1/2 voltage generation circuit 22b. It has become.

Further, in this embodiment, the level shift circuit 22
a is a current source, which gives a level shift as a voltage drop at the resistor R of the 1/2 voltage generating circuit 22b.
It is inseparable from the two-voltage generation circuit, and also operates as the level shift / １ ／ voltage generation circuit 22.

FIG. 5 shows the change in the output level of each part in FIG. 3 with respect to the change in the input amplitude.
The waveform of the TC circuit is shown in “ATC part waveform” in FIG. 6, and it is assumed that the input signal is a bipolar code having an opposite phase.

Now, the ATC circuit determines the 0-side peak detection level (see FIGS. 4 to 6), which is the 0-side output level, and
1 to the bottom detection level (FIG. 4 to FIG.
The threshold level (see FIGS. 4 to 6) is obtained by adding the forced offset value V _OF to a half level (see FIGS. 5 and 6) with respect to the half level (see FIGS. 5 and 6). .

The gain of the differential amplifier circuit 201 of the bottom detection circuit 21 with dead zone is designed to be (V _th / 2V _OF ) -1,
The dead zone V _SH is equal to 2V _OF . That is, the bottom detection circuit 2
1 the amplitude of the input signal does not respond to 4V _OF, at least 4V _OF outputs a high level by approximately 2V _OF than 1 side output level.

Further, as shown in FIGS.
By providing a dead zone in the circuit, 4V _OFWith the above input amplitude
Sets the threshold level to the center of the amplitude of the input signal
Therefore, the eye opening does not deteriorate.

[0070] That is, in this embodiment, since the dead zone with bottom detection circuit 21 does not respond only to the half of the amplitude, Figure 5, the amplitude 4V _OF is the threshold level as seen from FIG. 6 is set to the amplitude center This is the case above. In this embodiment, the peak / bottom detection circuit uses the MOS-FET 202 whose gate and drain are short-circuited as the rectifying element, but the principle is exactly the same.

Next, the operation of FIG. 7 will be described with reference to FIG. Here, 30 in FIG. 7 is a peak detection circuit with a dead zone, 31 is a reference voltage generation circuit that outputs the 0 level of the input signal, 32 is a level shift circuit, 33 is a 1/2 voltage generation circuit, and 34 is a limiter amplifier. Circuit.

In FIG. 7, a level shift circuit 32 is provided outside the peak detection circuit 21 with a dead zone,
The half voltage generation circuit is provided on the input side of the peak detection circuit with dead zone.

Further, FIG. 8 shows the "ATC section waveform" and the "output waveform" when the amplitude of the "input waveform" is small and large, but there is no difference in the operation of the ATC circuit depending on the magnitude of the amplitude. .

Now, in FIG. 8, the level shift circuit 3
2 is applied to one end of the 電 圧 voltage generation circuit 33 after shifting the reference value level substantially equal to the 0-side output level of the input signal transmitted by the reference voltage generation circuit 31 by 2V _OF .

On the other hand, the other end of the 電 圧 voltage generating circuit 33 has no signal level, and a level V _OF higher than the no signal level is applied to the input side of the differential amplifier circuit 301. afterwards,
When the input signal is applied to the peak detection circuit 30 with a dead zone via the 1/2 voltage generation circuit 33 (see FIGS. 7 and 8), as described in detail above, after passing 2V _OF ,
Since the threshold level (see FIGS. 7 and 8) is set at the center of the amplitude of the input signal, the input waveform can be reproduced without error.

Next, the operation of FIG. 9 will be described with reference to FIG. Here, 40 in FIG. 9 is a peak detection circuit with a dead band, 41 is a reference voltage generation circuit, 42 is a level shift circuit, 43 is a 1/2 voltage generation circuit, and 44 is a limiter amplifier circuit. An ATC circuit is constituted by the circuits 40 to 1/2 voltage generating circuit 43.

In FIG. 9, a level shift circuit is provided in the peak detection circuit 21 with a dead zone,
The configuration in which the voltage generation circuit is provided on the output side of the peak detection circuit with a dead zone is shown.

Further, FIG. 10 shows the "ATC part waveform" and the "output waveform" when the amplitude of the "input waveform" is small and large, but there is no difference in the operation of the ATC circuit depending on the magnitude of the amplitude. .

In FIG. 10, the level shift circuit 42 is a current source, and gives a 2V _OF shift as a voltage drop across the resistor R in the peak detection circuit 40 with dead zone to the output of this detection circuit (FIG. 9, FIG. (See FIG. 10).

On the other hand, since the reference voltage generating circuit 41 outputs the 0-side output level as the reference level (see FIGS. 9 and 10), the threshold is applied after passing 2V _OF as described in detail above. Since the value (see FIGS. 9 and 10) is set at the center of the amplitude of the input signal, the input waveform can be reproduced without error.

Next, the operation of FIG. 11 will be described with reference to FIGS. Here, 50 in FIG.
A first peak detection circuit 51 for outputting a side level; a first bottom detection circuit 51 for outputting a zero level of an input signal;
2 is a first 1/2 voltage generating circuit, 53 is a first limiter amplifier circuit, 54a is a peak detection circuit with a dead zone for outputting one side level from the first limiter amplifier circuit, 54b is a level shift circuit, 55 Is a first bottom detection circuit that outputs a 0-side level from the first limiter amplifier circuit, 56 is a second 1/2 voltage generation circuit, and 57 is a second limiter amplifier circuit.

A first ATC circuit is constituted by the peak detection circuit 50 to the 1/2 voltage generation circuit 52, and a peak detection circuit 54a having a dead zone, a level shift circuit 54b and a second 1/2 voltage generation circuit 56. A second ATC circuit is configured.

FIG. 11 shows a level shift circuit 54b.
Is provided in the peak detection circuit with dead band 54a, and the 1/2 voltage generation circuit 56 is provided on the output side of the peak detection circuit with dead band 54a. The circuit 54a is inseparable from the circuit 54a.

FIG. 12 shows the change in the output level of each section in FIG. 11 with respect to the change in the input amplitude. The input signal is assumed to be a positive-polarity unipolar code.
The signal input to the TC circuit is a bipolar code (see the output waveform of the first-stage limiter amplifier circuit in FIG. 13).

The ATC circuit comprises a level shift circuit 5
4b, the 1-side level shift peak detection level (see FIGS. 12 and 13) obtained by shifting the peak detection level without shift (see FIGS. 12 and 13) by 2 V _OF , and the 0-side bottom output from the bottom detection circuit 55 Detection level (FIG. 12, FIG. 1
3) to the second 1/2 voltage generating circuit 5
By taking in step 6, the threshold level (see FIGS. 12 and 13) is obtained.

Here, a bottom detection circuit 55a with a dead zone is provided.
The gain of the differential amplifying circuit 541a is (V _th / 2V _OF )
-1 and the dead band of the level shift amount V _SH is 2V _OF
be equivalent to.

[0087] That is, the dead zone with a peak detector circuit 54a until the input amplitude 4V _OF outputs a high level only 2V _OF than the no-signal level, 4V _OF least in "1" side level (FIG. 12, one point of the 13 A level approximately equal to the dotted line overlapping the chain line) is output.

Further, as shown in FIG. 13, by providing a dead zone in the peak detection circuit, the threshold level is set at the center of the amplitude even if the amplitude changes at an input amplitude of 4 V _OF or more ( In the waveform of the second stage ATC circuit in FIG.
), And a correct output waveform can be obtained without deteriorating the eye opening (see the output waveform in FIG. 13).

In this embodiment, the multi-stage configuration allows the small input amplitude to be amplified by the gain A ₁ of the first-stage amplifier circuit and input to the second-stage ATC circuit without being affected by the offset. , The forced offset can be increased to a value of A ₁ times that of the single-stage configuration.

Therefore, it is not necessary to set a minute level shift amount, and the adjustment can be simplified. Next, FIG.
The operation of FIG. 14 will be described with reference to FIG.

Here, 60 in FIG. 14 is a peak detection circuit with a dead zone, 61 is a reference voltage generation circuit, 62 is a level shift circuit, 63 is a 1/2 voltage generation circuit, and 64 is a limiter amplifier circuit.

FIG. 14 shows that a level shift circuit is provided in a peak detection circuit with a dead zone,
This figure shows a configuration in which a two-voltage generation circuit is provided on the input side of a peak detection circuit with a dead band.

Further, FIG. 15 shows the "ATC section waveform" and the "output waveform" when the amplitude of the "input waveform" is small and large, but there is no difference in the operation of the ATC circuit depending on the magnitude of the amplitude. .

In FIG. 14, the level shift circuit 62 is a current source and gives a shift of 2V _OF as a voltage drop across the resistor R in the peak detection circuit 60 with a dead zone (see FIGS. 14 and 15). .

On the other hand, since the reference voltage generating circuit 61 sends out the 0-side output level (see FIGS. 14 and 15),
As described in detail above, the peak detection circuit 60 with a dead zone
Since the distance from the input amplitude 2V _OF outputs a high level by V _OF than the no-signal level, the input amplitude of more than 2V _OF threshold level is set to the amplitude center of an input signal, (FIG. 15
, In the waveform of the "ATC circuit"), a correct output waveform can be obtained without deterioration of the eye opening.

In the embodiments described above, _Vth of the rectifying element of the peak detection circuit is used as a means for providing a dead zone.
0 will be described below.

First, the operation of FIG. 16 will be described with reference to FIG. Here, reference numeral 70 in FIG. 16 denotes a peak detection circuit with a dead zone for transmitting an output level on one side of the input, 71 denotes a reference voltage generation circuit, and 72 denotes a constant current of 2 V _OF / R corresponding to ON / OFF of a control signal. Flow-controlled level shift circuit, 7
3 is a 1/2 voltage generation circuit, and 74 is a limiter amplifier circuit.

FIG. 16 shows a configuration in which the level shift circuit is provided in the peak detection circuit with dead zone, and the 1/2 voltage generation circuit is provided on the output side of the peak detection circuit with dead zone.

Further, the gain of the differential amplifier circuit 701 of the peak detection circuit with dead zone 70 is sufficiently high, and does not have a dead zone function alone. However, the level shift circuit 72 is turned on in a standby state before receiving a signal, and turned off when a signal is received, and the shifted level is held, whereby the level shift and the dead zone can be realized at the same time.

The operating state of the peak detection circuit with a dead zone is as follows depending on the state of the control signal applied to the level shift circuit 72 in FIG. (1) Before Control Signal Input Between the two input terminals of the differential amplifier circuit 701, that is, the input and the connection point between the level shift circuit 72 and one end of the resistor R are virtually short-circuited, and have substantially the same potential.

Since the current is off, there is no potential difference between both ends of the resistor, and the connection point, the output side of the buffer 704 and the connection point at the other end of the resistor R are the same potential. In other words, the potential of the input of the differential amplifier circuit is the same as that of the virtual amplifier because there is no virtual short circuit and no voltage drop. (2) During the input of the control signal Since the current is turned on, a potential difference of 2 V _OF is generated in the resistor R, and between the two input terminals of the differential amplifier circuit 701, ie,
The capacitor 703 is charged so that the potential of the connection point becomes equal to that of the connection point, and the potential of the connection point increases. (3) After the control signal is input Since the current is off, the potential difference between both ends of the resistor R disappears, and the potential difference from the connection point disappears. However, since the input terminal of the buffer and the diode are sufficiently high in resistance, the capacitance 703
Cannot be discharged, and the potential of the connection point is maintained. As a result, a peak holding state is forcibly established. (4) During signal input a) If the input amplitude exceeds the held level (2V _OF ), peak detection is performed and the capacitor is charged.

B) However, if it does not exceed 2V _OF , it is kept as it is. That is, in the stand-by state, the signal level is 2 more than the no-signal level.
It is stabilized at a level higher by V _OF, and becomes a holding state even when the control signal is turned off, and holds this level.

[0103] At the time of signal reception, level is greater if the peak detection circuit than 2V _OF response, the level does not respond smaller than 2V _OF. In this embodiment, when a signal is not input, the forced offset is maintained in the holding state, so that the holding time must be sufficiently longer than the interval of the control signal.

[0104] However, it is not necessary to suppress the gain of the differential amplifier circuit, the coefficient of the (6) _{1 set} second term of A / (A
There is no error of +1), and the bottom detection circuit can be made highly accurate.

As the control signal, any signal may be used as long as the signal is not input. For example, a reset signal for clearing the peak detection level may be used. Of course, the bottom detection circuit with dead zone of the present embodiment may be a circuit using the V _th of the rectifier as described above.

Next, the operation of FIG. 18 will be described with reference to FIGS. 19 and 20. FIG. 18 shows an example in which a signal amplifier circuit using an ATC circuit is applied to an optical signal receiving circuit. In FIG. 18, reference numeral 85 denotes a photodiode which is a photoelectric conversion element, 86 denotes a preamplifier circuit, 80 denotes a reference voltage generating circuit that sends out the 0-side output level of an input signal, and 81 denotes 1/2 that outputs a divided signal.
A voltage generating circuit, 82a is a bottom detection circuit with a dead zone for detecting the bottom of the one-side output level of the divided signal, 82b is a level shift circuit that can be turned on / off by a control signal, 8
3 is a limiter amplifier circuit.

Reference voltage generation circuit 80 to bottom detection circuit 8
An ATC circuit is constituted by 2b. In the present embodiment, the level shift circuit 82b is a current source, and the shift is given as a voltage drop in the resistor R inserted in the loop of the bottom detection circuit 82a. Therefore, the level shift circuit 82b is inseparable from the bottom detection circuit. -It functions as the bottom detection circuit 82.

FIG. 18 shows a level shift circuit 82b.
Is provided in the peak detection circuit with dead zone 82a, and the 1/2 voltage generation circuit 81 is provided on the input side of the peak detection circuit with dead zone.

FIGS. 19 and 20 show changes in the output level of each section in FIG. 18 with respect to changes in the input amplitude. In the preamplifier circuit 86 as shown in FIG. 18, the signal input to the ATC circuit has an opposite-phase unipolar code.

The ATC circuit outputs 0-side output level, that is, 0
The divided voltage signal obtained from the divided voltage between the side reference level (see FIGS. 19 and 20) and the input signal (see FIGS. 19 and 20)
Is shifted by the forced offset amount V _OF, and a bottom level is detected to obtain a threshold level (see FIGS. 19 and 20).

The level shift / bottom detection circuit 82 has a dead zone based on the same principle as the peak detection circuit 70. Depending on the state of the control signal applied to the level shift circuit 82b in FIG. 18, the operation state of the peak detection circuit with dead zone is as follows. (1) Before input of control signal Between two input terminals of the differential amplifier circuit 821a, that is, 1 /
The output of the two-voltage generating circuit and the connection point are substantially at the same potential in a virtual short circuit state.

Since the power supply is off, there is no potential difference between both ends of the resistor R, and the output of the buffer 824 has the same potential. (2) Since the current is turned on during the input of the control signal, a potential difference of V _OF is generated in the resistor R,
The capacitance is discharged so that the potential between the two input terminals of the differential amplifier circuit, that is, the output of the 1/2 voltage generating circuit and the connection point have the same potential, and the potential at the connection point decreases. (3) After the control signal is input Since the current is off, the potential difference of the resistor R disappears, and the potential difference between the output of the 1/2 voltage generating circuit and the connection point disappears.

However, since the input terminal of the buffer and the diode have sufficiently high resistance, the charge of the capacitor cannot be charged, and the potential of the connection point is maintained. As a result, the bottom detection state is forcibly set. (4) During signal input a) If the input amplitude exceeds the held level (V _OF ), bottom detection is performed. b) However, if it does not exceed 2V _OF , it is kept as it is.

[0114]

As described above in detail, according to the present invention, a threshold control circuit capable of discriminating no signal without causing a shift in threshold level at a signal level to be received. The effect is that it can be provided.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a first and a sixth embodiment of the present invention.

FIG. 2 is an operation explanatory diagram of FIG. 1;

FIG. 3 is another operation explanatory diagram of FIG. 1;

FIG. 4 is a configuration diagram of a second embodiment of the first and sixth aspects of the present invention.

FIG. 5 is an operation explanatory diagram of FIG. 4;

FIG. 6 is another operation explanatory diagram of FIG. 4;

FIG. 7 is a configuration diagram of a second and a sixth embodiment of the present invention.

FIG. 8 is an operation explanatory diagram of FIG. 7;

FIG. 9 is a configuration diagram of the third and seventh embodiments of the present invention.

FIG. 10 is an operation explanatory diagram of FIG. 9;

FIG. 11 is a configuration diagram of the third, seventh, and tenth embodiments of the present invention.

FIG. 12 is an operation explanatory diagram of FIG. 11;

FIG. 13 is another operation explanatory diagram of FIG. 11;

FIG. 14 is a configuration diagram of a fourth and a seventh embodiment of the present invention.

FIG. 15 is an operation explanatory diagram of FIG. 14;

FIG. 16 is a configuration diagram of the third and eighth embodiments of the present invention.

FIG. 17 is an operation explanatory diagram of FIG. 16;

FIG. 18 is a configuration diagram of the fourth, eighth, and eleventh embodiments of the present invention.

FIG. 19 is an operation explanatory diagram of FIG. 18;

20 is another operation explanatory view of FIG. 18;

FIG. 21 is a configuration diagram of a conventional example.

FIG. 22 is an operation explanatory diagram of FIG. 21;

FIG. 23 is another operation explanatory diagram of FIG. 21;

[Explanation of symbols]

 Reference Signs List 10 Peak detection circuit with dead zone 11 Reference voltage generation circuit 12 Level shift circuit 13 1/2 voltage generation circuit 14 Limiter amplification circuit 101 Differential amplification circuit 102 Diode 103 Capacitance 104 Buffer

Claims (10)

[Claims] 1. A signal for reproducing a pulse signal from an input signal.
In the amplifier circuit, the 0-side output level substantially equal to the 0-side level of the input signal is
0 side output level sending circuit to send, and output level almost equal to no signal level when no signal is input
However, the level of the input signal is set to a predetermined value V₁that's all
In this case, the level of the input signal is approximately V_OF×
[(R₁+ R₀) / R₀] (Where V_OFIs forced off
Set value, R₀, R₁Is the resistance value)
V_SHOnly output low side 1 output level, insensitive
A peak (bottom) detection circuit having a band, and R for the 1-side output level and the 0-side output level₁: R
₀A voltage dividing circuit that obtains a threshold level by performing a voltage dividing of
The 1-side output level, or the 0-side output level, or
Level shift to perform level shift for threshold level
Circuit and almost no compulsory offset than no signal level when no signal is input
Value V_OFLevel, the input signal level
The preset value V₁In the above case, the signal amplitude R ₁: R₀
Output as a threshold level.
And a threshold control circuit. 2. A signal for reproducing a pulse signal from an input signal.
In the amplifier circuit, the 0-side output level substantially equal to the 0-side level of the input signal is
A 0-side output level sending circuit for sending, and the input signal level
And R for the 0 side output level₁: R₀Of the partial pressure
A voltage dividing circuit for obtaining a divided voltage signal;
Also almost forced offset value V_OFOutput only higher level
Is the input signal level V₁More than
Is almost forcibly offset from the level of one side of the input signal.
G value V_OFLevel shift amount V equal to_SHOnly lower level
Peak with dead zone output as threshold level
(Bottom) detection circuit, the divided signal level, or the 0 side output level, or
Level shift to perform level shift for threshold level
Circuit and almost no compulsory offset than no signal level when no signal is input
Value V_OFLevel, the input signal level
The preset value V₁In the above case, the signal amplitude R ₁: R₀
Output as a threshold level.
And a threshold control circuit. 3. A signal amplifying circuit for reproducing a pulse signal from an input signal, comprising: a 0-side output level sending circuit for sending a 0-side output level substantially equal to the 0-side level of the input signal; _VOF × [(R ₁
+ R ₀₎ / R _0] to but outputs equal level shift amount V _SH only high level, when the level value V ₁ or a preset of the input signal, as approximately equal to one-side level of the input signal A level shift peak (bottom) detection circuit having a dead zone for outputting a proper one-side output level, and R ₁ : R for the one-side output level and the zero-side output level
_A voltage dividing circuit for dividing the voltage to ₀ to obtain a threshold level is provided. When no signal is input, the voltage is maintained at a level which is almost V _OF higher than the no signal level, but the level of the input signal is preset. R ₁ of the signal amplitude when the value V ₁ or more: the threshold control circuit a partial pressure value of R _0, characterized in that a configuration for outputting a threshold level. 4. A signal amplifying circuit for reproducing a pulse signal from an input signal, comprising: a 0-side level transmitting circuit for transmitting a 0-side output level substantially equal to the 0-side level of the input signal; A voltage divider circuit for dividing the output level by R ₁ : R ₀ to obtain a divided signal, and when no signal is input, only a level shift amount V _SH substantially equal to the forced offset value V _OF than the no signal level Although outputs a high level, when the level value V ₁ or a preset of the input signal, a peak having a dead zone to output a level approximately equal to one side level該分pressure signal as a threshold level ( (Bottom) detection circuit is provided, and when no signal is input, the level is maintained at a level which is almost V _OF higher than the no signal level, but when the level of the input signal is equal to or higher than a preset value V ₁ , the signal amplitude R ₁ : the partial pressure value of R ₀ Threshold control circuit being characterized in that a configuration for outputting as have value level. 5. The threshold control circuit according to claim 1, wherein R ₁ : R ₀ is 1: 1. 6. A peak with the dead zone (bottom) detection circuit, a differential amplifier circuit, a rectifying element, has a capacity to hold the detected value for the threshold voltage V _th of the rectifying element Wherein the gain A of the differential amplifier circuit is controlled to approximately A = (V _th / V _SH ) −1 to provide a dead zone substantially equal to the level shift amount V _SH . The threshold control circuit according to claim 2. 7. A level shift peak (bottom) detection circuit having a dead zone, comprising: a differential amplifier circuit, a rectifier, a capacitor for holding a detection value, and a level shift circuit provided in a feedback loop. The gain A of the differential amplifier circuit is controlled to approximately A = (V _th / V _SH ) −1 with respect to the threshold voltage V _th of the rectifying element, so that a dead zone substantially equal to the level shift amount V _SH 5. The threshold value control circuit according to claim 3, wherein the threshold value control circuit is provided. 8. A level shift peak (bottom) detection circuit having the dead zone is provided in a differential amplifier circuit, a rectifier, a capacitor for holding a detection value, and a feedback loop, and is turned on / off by a control signal. A level shift circuit capable of control is provided. The level shift is performed in a standby state before a signal is input, and in a signal reception state, the level shift is turned off to hold the detected value, and a dead zone substantially equal to the level shift amount V _SH 5. The threshold value control circuit according to claim 3, wherein the threshold value control circuit is provided. 9. A signal amplifier circuit for reproducing a pulse signal from an input signal, wherein a threshold control circuit and a differential amplifier circuit are connected in multiple stages, and the final stage threshold control circuit is provided. A signal amplifying circuit having a configuration using the threshold control circuit described above. 10. A signal amplification circuit for reproducing a pulse signal, wherein a threshold value control according to claim 1 is provided at an output side of a preamplification circuit for current-to-voltage conversion of a current signal from a photoelectric conversion element. A signal amplifier circuit characterized by using a circuit.