JPH11121741A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH11121741A JPH11121741A JP9280543A JP28054397A JPH11121741A JP H11121741 A JPH11121741 A JP H11121741A JP 9280543 A JP9280543 A JP 9280543A JP 28054397 A JP28054397 A JP 28054397A JP H11121741 A JPH11121741 A JP H11121741A
- Authority
- JP
- Japan
- Prior art keywords
- conductivity type
- base layer
- type base
- gate
- groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 239000010410 layer Substances 0.000 claims description 126
- 239000000758 substrate Substances 0.000 claims description 23
- 238000000605 extraction Methods 0.000 claims description 18
- 239000011229 interlayer Substances 0.000 claims description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 30
- 229920005591 polysilicon Polymers 0.000 abstract description 30
- 238000000034 method Methods 0.000 abstract description 9
- 230000015556 catabolic process Effects 0.000 abstract description 8
- 239000002184 metal Substances 0.000 abstract description 8
- 230000009467 reduction Effects 0.000 abstract description 3
- 238000004519 manufacturing process Methods 0.000 description 12
- 230000008569 process Effects 0.000 description 7
- 230000000694 effects Effects 0.000 description 6
- 230000007423 decrease Effects 0.000 description 5
- 230000005684 electric field Effects 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、縦型ＭＯＳＦＥ
Ｔ、縦型ＩＧＢＴ及び縦型ＩＥＧＴ等の縦型トレンチ構
造の半導体装置に係わり、特に、ゲート耐圧の低下を阻
止でき、また、メタル段切れを阻止し得る半導体装置に
関する。The present invention relates to a vertical MOSFE
The present invention relates to a semiconductor device having a vertical trench structure such as T, vertical IGBT, and vertical IEGT, and more particularly, to a semiconductor device that can prevent a decrease in gate withstand voltage and a metal step.
【０００２】[0002]
【従来の技術】近年、少ない基板占有面積で高い駆動能
力を得られる縦型トレンチ構造の半導体装置が注目され
ている。この種の半導体装置としては、例えば大電力用
のスイッチング素子として使用可能な縦型ＭＯＳＦＥ
Ｔ、縦型ＩＧＢＴ及び縦型ＩＥＧＴ等があり、これらの
半導体装置は夫々ＰＥＰ(photo etching process) 工程
などにより高密度に集積化されて製造される。2. Description of the Related Art In recent years, attention has been paid to a semiconductor device having a vertical trench structure capable of obtaining a high driving capability with a small substrate occupation area. As this type of semiconductor device, for example, a vertical MOSFE that can be used as a switching element for high power
T, vertical IGBT, vertical IEGT, and the like. These semiconductor devices are manufactured by being integrated at a high density by a PEP (photo etching process) process or the like.
【０００３】図８〜図１９はこの種の縦型ＭＯＳＦＥＴ
の製造工程を説明するための斜視断面図、平面図及びそ
の線矢視断面図などである。なお、平面図では、矢印に
付された数字にて線矢視断面図の図番が示され、矢印の
向きにて視認される断面が示される。FIGS. 8 to 19 show a vertical MOSFET of this type.
Are a perspective cross-sectional view, a plan view, and a cross-sectional view of the same taken along a line for explaining the manufacturing process. In the plan view, the figure number of the cross-sectional view taken along the line is indicated by the number attached to the arrow, and the cross section viewed in the direction of the arrow is indicated.
【０００４】この縦型ＭＯＳＦＥＴは、ＣＶＤ法によ
り、図８に示すように、ｎ+ 型半導体基板１上にｎ- 型
ベース層２が形成され、ｎ- 型ベース層２上に選択的に
２μｍ厚のｐ型ベース層３が形成される。ｐ型ベース層
３表面には選択的に島状のｐ+型コンタクト層４がスト
ライプ状に並べられて形成され、各ｐ+ 型コンタクト層
４間のｐ型ベース層３表面には選択的に深さ０．５μｍ
のｎ+ 型ソース層５が形成される。なお、各ｐ+ 型コン
タクト層４間のｎ+ 型ソース層５の幅は２．６μｍであ
る。ｎ+ 型ソース層５には、図９及び図１０に示すよう
に、その中央部に沿って選択的に０．６μｍ幅のストラ
イプ状の複数のトレンチ（溝）６がｐ型ベース層３を貫
通してｎ- 型ベース層２に達する深さ（ｄ＞２μｍ）ま
で４．６μｍ間隔で互いに略平行に形成される。In this vertical MOSFET, as shown in FIG. 8, an n- type base layer 2 is formed on an n + type semiconductor substrate 1 by a CVD method, and a 2 .mu.m A thick p-type base layer 3 is formed. On the surface of the p-type base layer 3, p-type contact layers 4 in the form of islands are selectively arranged in stripes, and selectively on the surface of the p-type base layer 3 between the p + -type contact layers 4. 0.5 μm depth
N + type source layer 5 is formed. The width of the n + -type source layer 5 between each p + -type contact layer 4 is 2.6 μm. As shown in FIGS. 9 and 10, a plurality of stripe-shaped trenches (grooves) 6 each having a width of 0.6 .mu.m are selectively formed in the n @ + -type source layer 5 along the central portion thereof. It is formed substantially parallel to each other at 4.6 μm intervals to a depth (d> 2 μm) penetrating to the n − type base layer 2.
【０００５】続いて、図１１に示すように、トレンチ６
内壁を含めた全面に酸化膜７が形成され、この酸化膜７
上に各トレンチ６を埋込むようにゲート電極用の第一ポ
リシリコン層８が形成される。続いて、例えばＣＤＥ
（chemical dry etching）法により、第一ポリシリコン
層８が各トレンチ６の開口上面の高さにほぼ等しい高さ
までエッチングされる。Subsequently, as shown in FIG.
An oxide film 7 is formed on the entire surface including the inner wall.
A first polysilicon layer 8 for a gate electrode is formed so as to fill each trench 6 thereon. Then, for example, CDE
The first polysilicon layer 8 is etched to a height substantially equal to the height of the upper surface of the opening of each trench 6 by a (chemical dry etching) method.
【０００６】次に、酸化膜７上及び第一ポリシリコン８
上の全面に第二ポリシリコン層が形成される。図１２及
び図１３に示すように、この第二ポリシリコン層９は、
ＰＥＰ工程により、トレンチ６の終端部において、０．
６μｍ幅の各トレンチ６内の各第一ポリシリコン層８に
１．６μｍ幅の歯を重ねた櫛歯状の平面形状に形成され
る。Next, on the oxide film 7 and the first polysilicon 8
A second polysilicon layer is formed on the entire upper surface. As shown in FIGS. 12 and 13, the second polysilicon layer 9
Due to the PEP process, 0.
A 1.6 μm-wide tooth is formed on each first polysilicon layer 8 in each 6 μm-wide trench 6 in a comb-like planar shape.
【０００７】しかる後、図１４に示すように、ＣＶＤ法
により、基板全面に絶縁層１０が形成される。図１５及
び図１６に示すように、この絶縁層１０は、ＰＥＰ工程
により、各トレンチ６の終端部に位置する第二ポリシリ
コン層９を櫛歯状に露出させるように第一開口部１１が
形成されると共に、各トレンチ６間の中央領域（ＦＥＴ
領域）に位置する各ｎ+ 型ソース層５及び各ｐ+ 型コン
タクト層４を露出させるように３μｍ幅の第二開口部１
２が形成される。After that, as shown in FIG. 14, an insulating layer 10 is formed on the entire surface of the substrate by the CVD method. As shown in FIGS. 15 and 16, the insulating layer 10 has a first opening 11 formed by a PEP process such that the second polysilicon layer 9 located at the terminal end of each trench 6 is exposed in a comb shape. And a central region between each trench 6 (FET
Region) so as to expose each of the n + -type source layers 5 and each of the p + -type contact layers 4.
2 are formed.
【０００８】続いて、Ａｌ金属などにより、図１７乃至
図１９に示すように、各第一開口部内の第二ポリシリコ
ン層９を電気的に接続するようにゲートＡｌ電極１３が
ゲート電極パット部１４と共に選択形成される。また、
これと同時に、図１７に示すように、各第二開口部１２
内の各ｎ+ 型ソース層５及び各ｐ+ 型コンタクト層４を
電気的に接続するようにソース電極１５が選択形成され
る。Subsequently, as shown in FIGS. 17 to 19, the gate Al electrode 13 is electrically connected to the gate electrode pad portion by using Al metal or the like so as to electrically connect the second polysilicon layer 9 in each first opening. 14 is selectively formed. Also,
At the same time, as shown in FIG.
The source electrode 15 is selectively formed so as to electrically connect each of the n + -type source layers 5 and each of the p + -type contact layers 4.
【０００９】以下、図示しないが、ゲートＡｌ電極１３
及びソース電極１５を除く素子の表面に保護層が形成さ
れ、基板の裏面にドレイン電極が形成されて縦型ＭＯＳ
ＦＥＴが製造される。なお、縦型ＭＯＳＦＥＴを例に挙
げて説明したが、ｎ+ 型半導体基板１とｎ- 型ベース層
２との間にｐ+ 型エミッタ層を設けたＩＧＢＴとしても
同様に製造可能である。また、ｐ+ 型エミッタ層をもつ
ＩＧＢＴの構造において、トレンチ６の深さや幅などを
最適化して正孔の蓄積を図ったＩＥＧＴとしても同様に
製造可能である。Hereinafter, although not shown, the gate Al electrode 13
A protective layer is formed on the surface of the device except for the source electrode 15 and a drain electrode is formed on the back surface of the substrate.
An FET is manufactured. Although the vertical MOSFET has been described as an example, an IGBT in which a p + type emitter layer is provided between the n + type semiconductor substrate 1 and the n− type base layer 2 can be similarly manufactured. Further, in the structure of the IGBT having the p @ + -type emitter layer, an IEGT in which holes are accumulated by optimizing the depth and width of the trench 6 can be similarly manufactured.
【００１０】[0010]
【発明が解決しようとする課題】しかしながら以上のよ
うな半導体装置では、トレンチ終端部において、図１８
及び図２０に示すように、トレンチ６内の各第一ポリシ
リコン層８を第二ポリシリコン層９で接続したゲート引
出し構造を有している。このため、トレンチ終端部で
は、第二ポリシリコン層９が絶縁層７を介してトレンチ
６上部の角のｐ型ベース層３を覆う構造となる。従っ
て、トレンチ終端部のゲート引出し構造において、トレ
ンチ上部の角に電界が集中し、ゲート耐圧を低下させる
問題が発生する。However, in the above-described semiconductor device, at the trench end portion, FIG.
As shown in FIG. 20, a gate lead structure is provided in which each first polysilicon layer 8 in the trench 6 is connected by a second polysilicon layer 9. Therefore, at the trench end portion, the second polysilicon layer 9 has a structure that covers the p-type base layer 3 at the upper corner of the trench 6 via the insulating layer 7. Therefore, in the gate lead-out structure at the end of the trench, the electric field is concentrated at the upper corner of the trench, causing a problem of lowering the gate breakdown voltage.
【００１１】さらに、このゲート引出し構造では、図１
８に示すように、トレンチ６内の第一ポリシリコン層８
上に第二ポリシリコン層９を重ねるためにポリシリコン
の段差を生じることから、後工程でのＰＥＰ寸法合せズ
レや電極用金属の段切れを発生させる場合があり、問題
となっている。Further, in this gate lead-out structure, FIG.
8, the first polysilicon layer 8 in the trench 6
Since the second polysilicon layer 9 is superimposed on the second polysilicon layer 9 to cause a step in the polysilicon, there is a case where a PEP dimension misalignment or a step disconnection of the electrode metal occurs in a later step, which is a problem.
【００１２】本発明は上記実情を考慮してなされたもの
で、ゲート耐圧の低下を阻止し得る半導体装置を提供す
ることを目的とする。また、本発明の他の目的は、ＰＥ
Ｐ工程時の寸法合せのズレや、段差による電極用金属の
段切れを阻止し得る半導体装置を提供することにある。The present invention has been made in view of the above circumstances, and has as its object to provide a semiconductor device capable of preventing a decrease in gate breakdown voltage. Another object of the present invention is to provide PE
It is an object of the present invention to provide a semiconductor device capable of preventing a displacement of dimensions in a P step and disconnection of a metal for an electrode due to a step.
【００１３】[0013]
【課題を解決するための手段】請求項１に対応する発明
は、前記基板上に形成された第１導電型ベース層と、前
記第１導電型ベース層上に形成された第２導電型ベース
層と、前記第２導電型ベース層表面に選択的に形成され
た複数の第１導電型ソース層と、前記各第１導電型ソー
ス層内に互いに略平行に形成され、前記第１導電型ソー
ス層及び前記第２導電型ベース層を貫通して前記第１導
電型ベース層に達する深さを有する複数のゲート用溝
と、前記各ゲート用溝の深さに等しい深さを有し、前記
各ゲート用溝の端部を互いに接続するように前記第２導
電型ベース層内に形成された複数の配線用溝と、前記各
溝の開口部の高さにほぼ等しい高さまで前記各溝内にゲ
ート絶縁膜を介して埋込み形成されたゲート電極と、前
記第１導電型ソース層上に形成されたソース電極と、前
記第１導電型ベース層とは反対面の前記基板上に形成さ
れたドレイン電極とを備えた半導体装置である。According to a first aspect of the present invention, a first conductive type base layer formed on the substrate and a second conductive type base formed on the first conductive type base layer are provided. A plurality of first conductivity type source layers selectively formed on the surface of the second conductivity type base layer; and a plurality of first conductivity type source layers formed substantially parallel to each other in each of the first conductivity type source layers. A plurality of gate grooves having a depth reaching the first conductivity type base layer through the source layer and the second conductivity type base layer; and a depth equal to the depth of each of the gate grooves, A plurality of wiring grooves formed in the second conductivity type base layer so as to connect the ends of the respective gate grooves to each other, and the respective grooves to a height substantially equal to the height of the opening of each of the grooves. A gate electrode buried therein via a gate insulating film, and a source of the first conductivity type. A source electrode formed on the upper, wherein the first conductivity type base layer which is a semiconductor device that includes a drain electrode formed on the substrate on the opposite side.
【００１４】また、請求項２に対応する発明は、基板
と、前記基板上に形成された第１導電型ベース層と、前
記第１導電型ベース層上に形成された第２導電型ベース
層と、前記第２導電型ベース層表面に選択的に形成され
た複数の第１導電型ソース層と、前記第２導電型ベース
層内に前記第１導電型ベース層に達する深さまで選択的
に形成され、所定の幅Ｗ１を有する配線用溝と、前記配
線用溝の一部に接続されるように前記第２導電型ベース
層内に選択的に形成され、前記幅Ｗ１よりも太い幅Ｗ２
を有する引出し用溝と、前記各溝内にゲート絶縁膜を介
して埋込み形成されたゲート電極と、前記引出し用溝内
のゲート電極の中心部を露出させるように前記引出し用
溝の縁に沿って前記ゲート電極上に形成された層間膜
と、前記露出されたゲート電極に接して前記層間膜上に
形成された引出し電極と、前記第１導電型ソース層上に
形成されたソース電極と、前記第１導電型ベース層とは
反対面の前記基板上に形成されたドレイン電極とを備え
た半導体装置である。According to a second aspect of the present invention, there is provided a substrate, a first conductive type base layer formed on the substrate, and a second conductive type base layer formed on the first conductive type base layer. And a plurality of first conductivity type source layers selectively formed on the surface of the second conductivity type base layer; and selectively in the second conductivity type base layer to a depth reaching the first conductivity type base layer. A wiring groove having a predetermined width W1 and a width W2 which is selectively formed in the second conductivity type base layer so as to be connected to a part of the wiring groove and which is wider than the width W1.
And a gate electrode buried in each groove via a gate insulating film, and along an edge of the lead groove so as to expose a central portion of the gate electrode in the groove. An interlayer film formed on the gate electrode, a lead electrode formed on the interlayer film in contact with the exposed gate electrode, and a source electrode formed on the first conductivity type source layer. A semiconductor device comprising: a drain electrode formed on the substrate on a surface opposite to the first conductivity type base layer.
【００１５】さらに、請求項３に対応する発明は、基板
と、前記基板上に形成された第１導電型ベース層と、前
記第１導電型ベース層上に形成された第２導電型ベース
層と、前記第２導電型ベース層表面に選択的に形成され
た複数の第１導電型ソース層と、前記各第１導電型ソー
ス層内に互いに略平行に形成され、前記第１導電型ソー
ス層及び前記第２導電型ベース層を貫通して前記第１導
電型ベース層に達する深さを有する複数のゲート用溝
と、前記各ゲート用溝の深さに等しい深さを有し、且つ
所定の幅Ｗ１を有して前記各ゲート用溝の端部を互いに
接続するように前記第２導電型ベース層内に選択的に形
成された配線用溝と、前記配線用溝の一部に接続される
ように前記第２導電型ベース層内に選択的に形成され、
前記幅Ｗ１よりも太い幅Ｗ２を有する引出し用溝と、前
記各溝の開口部の高さにほぼ等しい高さまで前記各溝内
にゲート絶縁膜を介して埋込み形成されたゲート電極
と、前記引出し用溝内のゲート電極の中心部を露出させ
るように前記引出し用溝の縁に沿って前記ゲート電極上
に形成された層間膜と、前記露出されたゲート電極に接
して前記層間膜上に形成された引出し電極と、前記第１
導電型ソース層上に形成されたソース電極と、前記第１
導電型ベース層とは反対面の前記基板上に形成されたド
レイン電極とを備えた半導体装置である。 （作用）従って、請求項１に対応する発明は以上のよう
な手段を講じたことにより、各ゲート用溝の端部を各配
線用溝で接続し、且つ各溝内のゲート電極を各溝の開口
部の高さにほぼ等しい高さをもつように形成している。Further, the invention according to claim 3 is a substrate, a first conductivity type base layer formed on the substrate, and a second conductivity type base layer formed on the first conductivity type base layer. A plurality of first conductivity type source layers selectively formed on the surface of the second conductivity type base layer; and a plurality of first conductivity type source layers formed substantially parallel to each other in each of the first conductivity type source layers. A plurality of gate grooves having a depth reaching the first conductivity type base layer through the layer and the second conductivity type base layer; and a depth equal to the depth of each of the gate grooves, and A wiring groove having a predetermined width W1 and selectively formed in the second conductivity type base layer so as to connect ends of the gate grooves to each other, and a part of the wiring groove. Selectively formed in the second conductivity type base layer to be connected,
A lead groove having a width W2 larger than the width W1, a gate electrode buried in each groove via a gate insulating film to a height substantially equal to the height of the opening of each groove, and the lead An interlayer film formed on the gate electrode along an edge of the extraction groove so as to expose a central portion of the gate electrode in the groove, and an interlayer film formed on the interlayer film in contact with the exposed gate electrode. Drawn out electrode and the first
A source electrode formed on a conductive type source layer;
A semiconductor device comprising: a drain electrode formed on the substrate on the opposite side to the conductive type base layer. (Operation) Therefore, in the invention corresponding to claim 1, by taking the above means, the ends of the respective gate grooves are connected by the respective wiring grooves, and the gate electrodes in the respective grooves are connected to the respective grooves. Is formed so as to have a height substantially equal to the height of the opening.
【００１６】これにより、まず、従来の第二ポリシリコ
ン層の如き導電性材料が溝の上部でゲート電極を覆わな
いことから、溝上部の角部の電界集中を解消してゲート
耐圧の低下を阻止することができる。また、段差をもた
ずにゲート電極を配線することから、段差に起因したＰ
ＥＰ工程時の寸法合せのズレや電極用金属の段切れを阻
止することができる。As a result, first, since the conductive material such as the conventional second polysilicon layer does not cover the gate electrode at the upper portion of the groove, the electric field concentration at the corner at the upper portion of the groove is eliminated, and the reduction of the gate breakdown voltage is reduced. Can be blocked. In addition, since the gate electrode is wired without any step, P
It is possible to prevent misalignment of dimensions during the EP process and disconnection of the electrode metal.
【００１７】また、請求項２に対応する発明は、層間膜
が引出し用溝の縁に沿ってゲート電極を覆うことによ
り、引出し電極がゲート電極の中央部に接する構造であ
るので、請求項１と同様の作用をゲートの引出し構造部
においても奏することができる。According to a second aspect of the present invention, since the interlayer film covers the gate electrode along the edge of the extraction groove, the extraction electrode is in contact with the center of the gate electrode. The same effect as described above can be obtained also in the lead-out structure of the gate.
【００１８】また、引出し用溝の幅Ｗ２が配線用溝の幅
Ｗ１よりも太いため、引出し部の高抵抗化を阻止でき、
良好な引出し構造を実現することができる。さらに、請
求項３に対応する発明は、各ゲート用溝の端部を各配線
用溝で接続し、且つ各溝内のゲート電極を各溝の開口部
の高さにほぼ等しい高さをもつように形成した構造に加
え、層間膜が引出し用溝の縁に沿ってゲート電極を覆う
ことにより、ゲート電極の中心部を露出させ、引出し電
極が露出されたゲート電極の中央部に接する構造を備え
ているので、請求項１及び請求項２の両者に対応する作
用を同時に奏することができる。Further, since the width W2 of the lead groove is larger than the width W1 of the wiring groove, it is possible to prevent the lead portion from having a high resistance.
A good drawer structure can be realized. Further, in the invention corresponding to claim 3, the end of each gate groove is connected by each wiring groove, and the gate electrode in each groove has a height substantially equal to the height of the opening of each groove. In addition to the structure formed as described above, the interlayer film covers the gate electrode along the edge of the extraction groove, thereby exposing the center portion of the gate electrode and bringing the extraction electrode into contact with the exposed central portion of the gate electrode. Since it is provided, the functions corresponding to both the first and second aspects can be achieved at the same time.
【００１９】[0019]
【発明の実施の形態】以下、本発明の実施の形態につい
て図面を参照して説明する。 （第１の実施の形態）図１は本発明の第１の実施の形態
に係る縦型ＭＯＳＦＥＴの構成を示す平面図であり、図
２は図１の２−２線矢視断面図である。図３は引出し構
造の一部を示す平面図であり、図４は図３の４−４線矢
視断面図である。各図について図１乃至図２０と同一部
分には同一符号を付してその詳しい説明を省略し、ここ
では異なる部分について述べる。また、各図において
は、説明の簡素化のため、従来と同様のソース電極並び
にその周辺構成と基板裏面のドレイン電極を省略し、ま
た、配線用トレンチ内のゲート電極上の保護層を省略し
て示している。なお、以下の実施形態の図面も同様な省
略が行なわれるものとする。Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a plan view showing a configuration of a vertical MOSFET according to a first embodiment of the present invention, and FIG. 2 is a sectional view taken along line 2-2 of FIG. . FIG. 3 is a plan view showing a part of the drawer structure, and FIG. 4 is a sectional view taken along line 4-4 in FIG. In each figure, the same parts as those in FIGS. 1 to 20 are denoted by the same reference numerals, detailed description thereof will be omitted, and different parts will be described here. In each figure, for simplicity of description, the same source electrode as in the related art, its peripheral configuration and the drain electrode on the back surface of the substrate are omitted, and the protective layer on the gate electrode in the wiring trench is omitted. Is shown. Note that similar omissions are made in the drawings of the following embodiments.
【００２０】すなわち、本実施の形態は、トレンチ終端
部における各ゲート電極の接続構造と、パッド部領域に
おけるゲート電極の引出し構造とを改善したものであ
り、図１及び図２に示すように、トレンチ終端部におけ
るゲート引出し構造に代えて、各トレンチ６（ゲート用
溝）の終端部を配線用トレンチ２１によって接続する接
続構造を設けている。また、図１、図３及び図４に示す
ように、パッド部領域２２のゲート引出し構造は、配線
用トレンチ２１よりも太い幅の引出し用トレンチ２３を
設け、絶縁性の層間膜２４により引出し用トレンチ２３
の縁を覆った引出し構造を設けている。引出し用トレン
チ２３内のポリシリコン層８は、その中央部にてゲート
電極パッド部２５に接続される。That is, the present embodiment is an improvement of the connection structure of each gate electrode at the end of the trench and the lead-out structure of the gate electrode in the pad region, as shown in FIGS. Instead of the gate lead-out structure at the trench end portion, a connection structure for connecting the end portion of each trench 6 (gate groove) by a wiring trench 21 is provided. As shown in FIGS. 1, 3 and 4, the gate lead-out structure in the pad region 22 is provided with a lead-out trench 23 having a width wider than the wiring trench 21, and a lead-out structure formed by an insulating interlayer film 24. Trench 23
Is provided with a drawer structure that covers the edge of. The polysilicon layer 8 in the extraction trench 23 is connected to the gate electrode pad 25 at the center.
【００２１】具体的には、トレンチ終端部では、各トレ
ンチ６の深さに等しい深さを有し、且つ所定の幅Ｗ１を
有する配線用トレンチ２１が各トレンチ６の端部を互い
に接続するようにｐ型ベース層３内に選択的に形成され
ている。なお、幅Ｗ１は、例えば０．５〜１μｍの範囲
内で適宜設定可能であるが、ここではＷ１＝１μｍとす
る。配線用トレンチ２１内には、ゲート電極としてのポ
リシリコン層８がトレンチ２１の開口部の高さにほぼ等
しい高さまでゲート絶縁膜７を介して埋込み形成されて
いる。More specifically, at the trench end, a wiring trench 21 having a depth equal to the depth of each trench 6 and having a predetermined width W1 connects the ends of the trenches 6 to each other. Are selectively formed in the p-type base layer 3. The width W1 can be set as appropriate within a range of, for example, 0.5 to 1 μm. Here, it is assumed that W1 = 1 μm. In the wiring trench 21, a polysilicon layer 8 as a gate electrode is buried through the gate insulating film 7 to a height substantially equal to the height of the opening of the trench 21.
【００２２】一方、パッド部領域２２のゲート引出し構
造では、配線用トレンチ２１の幅Ｗ１よりも太い幅Ｗ２
を有する引出し用トレンチ２３が配線用トレンチ２１の
一部に接続されるようにｐ型ベース層３内に選択的に形
成されている。幅Ｗ２は、Ｗ１＜Ｗ２の関係を満たしつ
つ、１〜２μｍの範囲内で適宜設定可能であるが、ここ
ではＷ２＝２μｍとする。引出し用トレンチ２３内に
は、ポリシリコン層８がトレンチ２３の開口部の高さに
ほぼ等しい高さまでゲート絶縁膜７を介して埋込み形成
されている。また、引出し用トレンチ２３の開口部及び
その周辺の絶縁膜７の領域上には、層間膜２４が開口幅
Ｗ３にてポリシリコン層８の中心部を露出させるように
引出し用トレンチ２３の縁に沿って形成されている。な
お、開口幅Ｗ３は、Ｗ３＜Ｗ２の関係を満たす範囲内で
適宜設定可能であるが、ここではＷ３＝１μｍとする。
層間膜２４上には、ゲート電極パッド部２５が、層間膜
２４の開口部から露出されたポリシリコン層８に接して
形成されている。On the other hand, in the gate lead-out structure of the pad portion region 22, the width W2 is larger than the width W1 of the wiring trench 21.
Is selectively formed in the p-type base layer 3 so as to be connected to a part of the wiring trench 21. The width W2 can be appropriately set within the range of 1 to 2 μm while satisfying the relationship of W1 <W2. Here, W2 = 2 μm. The polysilicon layer 8 is buried in the extraction trench 23 through the gate insulating film 7 to a height substantially equal to the height of the opening of the trench 23. In addition, on the opening of the extraction trench 23 and the region of the insulating film 7 around the opening, the interlayer film 24 is formed on the edge of the extraction trench 23 so as to expose the center of the polysilicon layer 8 with the opening width W3. It is formed along. The opening width W3 can be appropriately set within a range satisfying the relationship of W3 <W2. Here, W3 = 1 μm.
On the interlayer film 24, a gate electrode pad portion 25 is formed in contact with the polysilicon layer 8 exposed from the opening of the interlayer film 24.
【００２３】なお、配線用トレンチ２１及び引出し用ト
レンチ２３は、ＦＥＴ領域のトレンチ６の形成と同時に
形成されている。また、各トレンチ６，２１，２３内の
ゲート絶縁膜７及びポリシリコン層８も同様である。The wiring trench 21 and the extraction trench 23 are formed simultaneously with the formation of the trench 6 in the FET region. The same applies to the gate insulating film 7 and the polysilicon layer 8 in each of the trenches 6, 21, 23.
【００２４】次に、このような縦型ＭＯＳＦＥＴの作用
について説明する。ＦＥＴ領域のトレンチ終端部におい
ては、各トレンチの端部を各配線用トレンチで接続し、
且つ各トレンチ内のゲート電極を各トレンチの開口部の
高さにほぼ等しい高さをもつように形成している。Next, the operation of such a vertical MOSFET will be described. At the end of the trench in the FET region, the end of each trench is connected by each wiring trench,
Further, the gate electrode in each trench is formed to have a height substantially equal to the height of the opening of each trench.
【００２５】これにより、まず、従来の第二ポリシリコ
ン層の如き導電性材料がトレンチの上部でポリシリコン
層８を覆わないことから、トレンチ上部の角部の電界集
中を解消してゲート耐圧の低下を阻止することができ
る。また、段差をもたずにゲート電極を配線することか
ら、段差に起因したＰＥＰ工程時の寸法合せのズレや電
極用金属の段切れを阻止することができる。As a result, first, since the conductive material such as the conventional second polysilicon layer does not cover the polysilicon layer 8 at the upper part of the trench, the electric field concentration at the corner at the upper part of the trench is eliminated and the gate breakdown voltage is reduced. The decline can be prevented. In addition, since the gate electrode is wired without any step, it is possible to prevent the dimensional deviation and the disconnection of the electrode metal due to the step during the PEP process.
【００２６】また、層間膜２４が引出し用トレンチ２３
の縁に沿ってポリシリコン層８を覆うことにより、ゲー
ト電極パッド部２５がポリシリコン層８の中央部に接す
る構造としている。すなわち、ゲート電極パッド部２５
が引出し用トレンチ２３の上部の角部を覆わない構造で
ある。このため、引出し用のパッド部領域２２において
も、トレンチ上部の角部の電界集中を解消してゲート耐
圧の低下を阻止することができる。Further, the interlayer film 24 is formed by the extraction trench 23.
, The gate electrode pad portion 25 is in contact with the central portion of the polysilicon layer 8. That is, the gate electrode pad 25
Has a structure that does not cover the upper corner of the extraction trench 23. For this reason, also in the extraction pad portion region 22, concentration of the electric field at the upper corner portion of the trench can be eliminated, and a decrease in gate breakdown voltage can be prevented.
【００２７】なお、トレンチ終端部及びパッド部領域２
２の電界集中を解消したことによるゲート耐圧の向上効
果を図５のＩ−Ｖ特性図に比較して示す。図示するよう
に、本実施形態に係る縦型ＭＯＳＦＥＴは、ドレイン電
流ＩD ＝１μＡカットレベルでゲート電圧ＶG ＝７５Ｖ
を得た。一方、従来構造は、ＩD ＝１μＡにてゲート電
圧ＶG ＝５０Ｖであった。すなわち、本実施形態は、従
来と比較して大幅にゲート耐圧を向上することができ
た。The trench end portion and the pad region 2
The effect of improving the gate breakdown voltage by eliminating the electric field concentration of FIG. 2 is shown in comparison with the IV characteristic diagram of FIG. As shown in the figure, the vertical MOSFET according to the present embodiment has a gate voltage V G = 75 V at a drain current ID = 1 μA cut level.
I got On the other hand, in the conventional structure, the gate voltage V G = 50 V at I D = 1 μA. That is, in the present embodiment, the gate withstand voltage can be significantly improved as compared with the related art.
【００２８】また、本実施形態によれば、引出し用トレ
ンチ２３の幅Ｗ２が配線用トレンチ２１の幅Ｗ１よりも
太いため、パッド部領域２２の高抵抗化を阻止でき、良
好な引出し構造を実現することができる。Further, according to the present embodiment, since the width W2 of the extraction trench 23 is larger than the width W1 of the wiring trench 21, it is possible to prevent the pad region 22 from increasing in resistance, and to realize a good extraction structure. can do.
【００２９】さらに、配線用トレンチ２１及び引出し用
トレンチ２３にてゲート配線及びパッドを形成すること
により、従来の第二ポリシリコン層を省略するので、１
つのＰＥＰ工程を削減することができる。 （第２の実施形態）図６は本発明の第２の実施形態に係
る縦型ＭＯＳＦＥＴのトレンチ終端部における構成を示
す平面図であり、図７は図６の７−７線矢視断面図であ
る。なお、図６の２−２線矢視断面は図２に示す通りで
ある。Further, by forming a gate wiring and a pad in the wiring trench 21 and the extraction trench 23, the conventional second polysilicon layer is omitted.
One PEP process can be reduced. (Second Embodiment) FIG. 6 is a plan view showing a configuration of a vertical MOSFET according to a second embodiment of the present invention at a trench termination portion, and FIG. 7 is a sectional view taken along line 7-7 in FIG. It is. The cross section taken along line 2-2 in FIG. 6 is as shown in FIG.
【００３０】すなわち、本実施形態は、図２に示す構造
の変形形態であり、配線抵抗の増加の阻止を図るもので
ある。具体的には、図６及び図７に示すように、ＦＥＴ
領域のトレンチの終端部が複数本の配線用トレンチ２１
ａにて接続されている。That is, the present embodiment is a modification of the structure shown in FIG. 2, and aims at preventing an increase in wiring resistance. Specifically, as shown in FIG. 6 and FIG.
The end portion of the trench in the region has a plurality of wiring trenches 21
a.
【００３１】ここで、各配線用トレンチ２１ａは、それ
らの配線抵抗の合計を従来のゲートポリシリコン層によ
る配線抵抗と同等の値とするように、トレンチ開口幅及
び本数が設定されている。Here, the trench opening width and the number of each wiring trench 21a are set so that the sum of the wiring resistances thereof is equivalent to the value of the conventional wiring resistance of the gate polysilicon layer.
【００３２】以上のような構成により、第１の実施形態
の効果に加え、配線抵抗の増加を阻止でき、また、配線
抵抗の低減を図ることができる。 （他の実施形態）上記第１及び第２の実施形態では、縦
型ＭＯＳＦＥＴの場合を説明したが、これに限らず、縦
型ＩＧＢＴ又は縦型ＩＥＧＴとしても、本発明と同様の
効果を得ることができる。With the above configuration, in addition to the effects of the first embodiment, an increase in wiring resistance can be prevented, and a reduction in wiring resistance can be achieved. (Other Embodiments) In the first and second embodiments, the case of a vertical MOSFET has been described. However, the present invention is not limited to this, and a vertical IGBT or a vertical IEGT can obtain the same effect as the present invention. be able to.
【００３３】また、上記第１及び第２の実施形態では、
第１導電型をｎ型とし、第２導電型をｐ型とした場合を
説明したが、これに限らず、夫々導電型を逆にしても、
本発明を同様に実施して同様の効果を得ることができ
る。その他、本発明はその要旨を逸脱しない範囲で種々
変形して実施できる。In the first and second embodiments,
The case where the first conductivity type is n-type and the second conductivity type is p-type has been described. However, the present invention is not limited to this.
The present invention can be implemented in a similar manner to obtain similar effects. In addition, the present invention can be implemented with various modifications without departing from the scope of the invention.
【００３４】[0034]
【発明の効果】上述したように本発明によれば、ゲート
耐圧の低下を阻止できる半導体装置を提供できる。ま
た、ＰＥＰ工程時の寸法合せのズレや、段差による電極
用金属の段切れを阻止できる。As described above, according to the present invention, it is possible to provide a semiconductor device capable of preventing a decrease in gate breakdown voltage. In addition, it is possible to prevent misalignment of the dimensions during the PEP step and disconnection of the metal for the electrode due to a step.
【図１】本発明の第１の実施の形態に係る縦型ＭＯＳＦ
ＥＴの構成を示す平面図FIG. 1 is a vertical MOSF according to a first embodiment of the present invention.
Plan view showing the configuration of ET
【図２】図１の２−２線矢視断面図FIG. 2 is a sectional view taken along line 2-2 of FIG. 1;
【図３】同実施の形態における引出し構造の一部を示す
平面図FIG. 3 is a plan view showing a part of the drawer structure in the embodiment.
【図４】図３の４−４線矢視断面図FIG. 4 is a sectional view taken along line 4-4 of FIG. 3;
【図５】同実施の形態におけるゲート耐圧の向上効果を
従来と比較して示すＩ−Ｖ特性図FIG. 5 is an IV characteristic diagram showing an improvement effect of a gate withstand voltage in the embodiment in comparison with a conventional example.
【図６】本発明の第２の実施形態に係る縦型ＭＯＳＦＥ
Ｔのトレンチ終端部における構成を示す平面図FIG. 6 is a vertical MOSFET according to a second embodiment of the present invention;
FIG. 2 is a plan view showing a configuration at a trench termination portion of T.
【図７】図６の７−７線矢視断面図FIG. 7 is a sectional view taken along line 7-7 in FIG. 6;
【図８】従来の縦型ＭＯＳＦＥＴの製造工程を説明する
ための斜視断面図FIG. 8 is a perspective cross-sectional view for explaining a manufacturing process of a conventional vertical MOSFET.
【図９】従来の製造工程を説明するための斜視断面図FIG. 9 is a perspective sectional view for explaining a conventional manufacturing process.
【図１０】従来の製造工程を説明するための平面図FIG. 10 is a plan view for explaining a conventional manufacturing process.
【図１１】従来の製造工程を説明するための斜視断面図FIG. 11 is a perspective sectional view for explaining a conventional manufacturing process.
【図１２】従来の製造工程を説明するための斜視断面図FIG. 12 is a perspective sectional view for explaining a conventional manufacturing process.
【図１３】従来の製造工程を説明するための平面図FIG. 13 is a plan view for explaining a conventional manufacturing process.
【図１４】従来の製造工程を説明するための斜視断面図FIG. 14 is a perspective sectional view for explaining a conventional manufacturing process.
【図１５】従来の製造工程を説明するための斜視断面図FIG. 15 is a perspective sectional view for explaining a conventional manufacturing process.
【図１６】従来の製造工程を説明するための平面図FIG. 16 is a plan view for explaining a conventional manufacturing process.
【図１７】従来の製造工程を説明するための斜視断面図FIG. 17 is a perspective sectional view for explaining a conventional manufacturing process.
【図１８】図１７の１８−１８線矢視断面図18 is a sectional view taken along line 18-18 of FIG. 17;
【図１９】従来の製造工程を説明するための平面図FIG. 19 is a plan view for explaining a conventional manufacturing process.
【図２０】従来の課題を説明するための模式図FIG. 20 is a schematic view for explaining a conventional problem.
１…ｎ+ 型半導体基板 ２…ｎ- 型ベース層 ３…ｐ型ベース層 ４…ｐ+ 型コンタクト層 ５…ｎ+ 型ソース層 ６…トレンチ ７…酸化膜 ８…ポリシリコン層 ２１，２１ａ…配線用トレンチ ２２…パッド部領域 ２３…引出し用トレンチ ２４…層間膜 ２５…ゲート電極パッド部 Ｗ１〜Ｗ３…幅 DESCRIPTION OF SYMBOLS 1 ... n + type semiconductor substrate 2 ... n- type base layer 3 ... p type base layer 4 ... p + type contact layer 5 ... n + type source layer 6 ... trench 7 ... oxide film 8 ... polysilicon layer 21, 21a ... Wiring trench 22 Pad area 23 Extracting trench 24 Interlayer film 25 Gate electrode pad W1 to W3 Width
Claims (3)
ス層と、 前記第２導電型ベース層表面に選択的に形成された複数
の第１導電型ソース層と、 前記各第１導電型ソース層内に互いに略平行に形成さ
れ、前記第１導電型ソース層及び前記第２導電型ベース
層を貫通して前記第１導電型ベース層に達する深さを有
する複数のゲート用溝と、 前記各ゲート用溝の深さに等しい深さを有し、前記各ゲ
ート用溝の端部を互いに接続するように前記第２導電型
ベース層内に形成された複数の配線用溝と、 前記各溝の開口部の高さにほぼ等しい高さまで前記各溝
内にゲート絶縁膜を介して埋込み形成されたゲート電極
と、 前記第１導電型ソース層上に形成されたソース電極と、 前記第１導電型ベース層とは反対面の前記基板上に形成
されたドレイン電極とを備えたことを特徴とする半導体
装置。A first conductive type base layer formed on the substrate; a second conductive type base layer formed on the first conductive type base layer; and a second conductive type base layer. A plurality of first conductivity type source layers selectively formed on the surface; and a first conductivity type source layer and a second conductivity type base layer formed substantially parallel to each other in each of the first conductivity type source layers. And a plurality of gate grooves having a depth reaching the first conductivity type base layer, and having a depth equal to the depth of each of the gate grooves, and connecting the ends of the gate grooves to each other. A plurality of wiring grooves formed in the second conductivity type base layer so as to be connected to each other; and buried in each of the grooves via a gate insulating film to a height substantially equal to the height of the opening of each of the grooves. A gate electrode, and a source electrode formed on the first conductivity type source layer. It said semiconductor device being characterized in that a drain electrode formed on the substrate surface opposite to the first conductivity type base layer.
ス層と、 前記第２導電型ベース層表面に選択的に形成された複数
の第１導電型ソース層と、 前記第２導電型ベース層内に前記第１導電型ベース層に
達する深さまで選択的に形成され、所定の幅Ｗ１を有す
る配線用溝と、 前記配線用溝の一部に接続されるように前記第２導電型
ベース層内に選択的に形成され、前記幅Ｗ１よりも太い
幅Ｗ２を有する引出し用溝と、 前記各溝内にゲート絶縁膜を介して埋込み形成されたゲ
ート電極と、 前記引出し用溝内のゲート電極の中心部を露出させるよ
うに前記引出し用溝の縁に沿って前記ゲート電極上に形
成された層間膜と、 前記露出されたゲート電極に接して前記層間膜上に形成
された引出し電極と、 前記第１導電型ソース層上に形成されたソース電極と、 前記第１導電型ベース層とは反対面の前記基板上に形成
されたドレイン電極とを備えたことを特徴とする半導体
装置。2. A substrate, a first conductivity type base layer formed on the substrate, a second conductivity type base layer formed on the first conductivity type base layer, and the second conductivity type base layer. A plurality of first conductivity type source layers selectively formed on the surface; and a plurality of first conductivity type source layers selectively formed in the second conductivity type base layer to a depth reaching the first conductivity type base layer, and having a predetermined width W1. A wiring groove; a lead groove selectively formed in the second conductivity type base layer so as to be connected to a part of the wiring groove, and having a width W2 larger than the width W1; A gate electrode buried in the groove via a gate insulating film, and formed on the gate electrode along an edge of the extraction groove so as to expose a central portion of the gate electrode in the extraction groove. An interlayer film, the interlayer film being in contact with the exposed gate electrode; A source electrode formed on the first conductivity type source layer, and a drain electrode formed on the substrate opposite to the first conductivity type base layer. A semiconductor device characterized by the above-mentioned.
ス層と、 前記第２導電型ベース層表面に選択的に形成された複数
の第１導電型ソース層と、 前記各第１導電型ソース層内に互いに略平行に形成さ
れ、前記第１導電型ソース層及び前記第２導電型ベース
層を貫通して前記第１導電型ベース層に達する深さを有
する複数のゲート用溝と、 前記各ゲート用溝の深さに等しい深さを有し、且つ所定
の幅Ｗ１を有して前記各ゲート用溝の端部を互いに接続
するように前記第２導電型ベース層内に選択的に形成さ
れた配線用溝と、 前記配線用溝の一部に接続されるように前記第２導電型
ベース層内に選択的に形成され、前記幅Ｗ１よりも太い
幅Ｗ２を有する引出し用溝と、 前記各溝の開口部の高さにほぼ等しい高さまで前記各溝
内にゲート絶縁膜を介して埋込み形成されたゲート電極
と、 前記引出し用溝内のゲート電極の中心部を露出させるよ
うに前記引出し用溝の縁に沿って前記ゲート電極上に形
成された層間膜と、 前記露出されたゲート電極に接して前記層間膜上に形成
された引出し電極と、 前記第１導電型ソース層上に形成されたソース電極と、 前記第１導電型ベース層とは反対面の前記基板上に形成
されたドレイン電極とを備えたことを特徴とする半導体
装置。3. A substrate, a first conductivity type base layer formed on the substrate, a second conductivity type base layer formed on the first conductivity type base layer, and a second conductivity type base layer. A plurality of first conductivity type source layers selectively formed on the surface; and a first conductivity type source layer and a second conductivity type base layer formed substantially parallel to each other in each of the first conductivity type source layers. A plurality of gate grooves having a depth reaching the first conductivity type base layer through the first conductive type base layer; and having a depth equal to the depth of each of the gate grooves, and having a predetermined width W1. A wiring groove selectively formed in the second conductivity type base layer so as to connect the ends of the respective gate grooves to each other; and the second conductive groove so as to be connected to a part of the wiring groove. A drawing groove selectively formed in the mold base layer and having a width W2 larger than the width W1; A gate electrode buried in each of the trenches through a gate insulating film to a height substantially equal to the height of the opening of each of the trenches, and the gate electrode is exposed so as to expose a central portion of the gate electrode in the lead-out trench. An interlayer film formed on the gate electrode along an edge of the lead groove; a lead electrode formed on the interlayer film in contact with the exposed gate electrode; and a first conductive type source layer. A semiconductor device comprising: a formed source electrode; and a drain electrode formed on the substrate on a surface opposite to the first conductivity type base layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9280543A JPH11121741A (en) | 1997-10-14 | 1997-10-14 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9280543A JPH11121741A (en) | 1997-10-14 | 1997-10-14 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH11121741A true JPH11121741A (en) | 1999-04-30 |
Family
ID=17626540
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9280543A Pending JPH11121741A (en) | 1997-10-14 | 1997-10-14 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH11121741A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001085689A (en) * | 1999-09-17 | 2001-03-30 | Toyota Motor Corp | Power semiconductor device |
| JP2002368221A (en) * | 2001-06-08 | 2002-12-20 | Nec Corp | Semiconductor device equipped with longitudinal mosfet and manufacturing method therefor |
| JP2003309263A (en) * | 2002-03-22 | 2003-10-31 | Siliconix Inc | Structure of trench gate mis device and its manufacturing method |
| US6642600B2 (en) | 2002-03-07 | 2003-11-04 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate semiconductor device having first trench and second trench connected to the same |
| JP2005191487A (en) * | 2003-12-26 | 2005-07-14 | Seiko Instruments Inc | Semiconductor device and manufacturing method for the same |
| JP4491875B2 (en) * | 1999-12-13 | 2010-06-30 | 富士電機システムズ株式会社 | Trench type MOS semiconductor device |
| JP2015082632A (en) * | 2013-10-24 | 2015-04-27 | 住友電気工業株式会社 | Silicon carbide semiconductor device and method of manufacturing the same |
-
1997
- 1997-10-14 JP JP9280543A patent/JPH11121741A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001085689A (en) * | 1999-09-17 | 2001-03-30 | Toyota Motor Corp | Power semiconductor device |
| JP4491875B2 (en) * | 1999-12-13 | 2010-06-30 | 富士電機システムズ株式会社 | Trench type MOS semiconductor device |
| JP2002368221A (en) * | 2001-06-08 | 2002-12-20 | Nec Corp | Semiconductor device equipped with longitudinal mosfet and manufacturing method therefor |
| US6642600B2 (en) | 2002-03-07 | 2003-11-04 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate semiconductor device having first trench and second trench connected to the same |
| JP2003309263A (en) * | 2002-03-22 | 2003-10-31 | Siliconix Inc | Structure of trench gate mis device and its manufacturing method |
| JP2005191487A (en) * | 2003-12-26 | 2005-07-14 | Seiko Instruments Inc | Semiconductor device and manufacturing method for the same |
| JP2015082632A (en) * | 2013-10-24 | 2015-04-27 | 住友電気工業株式会社 | Silicon carbide semiconductor device and method of manufacturing the same |
| WO2015060027A1 (en) * | 2013-10-24 | 2015-04-30 | 住友電気工業株式会社 | Silicon carbide semiconductor device and method for manufacturing same |
| US9728633B2 (en) | 2013-10-24 | 2017-08-08 | Sumitomo Electric Industries, Ltd. | Silicon carbide semiconductor device and method for manufacturing the same |
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