JPH11121623A - Semiconductor integrated circuit, positioning method therefor in laser repair device and method for regulating laser power thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance a relief rate of a semiconductor integrated circuit by using a fuse positioning mark as a positioner, by a method wherein the fuse positioning mark is provided in a wiring layer of the semiconductor integrated circuit. SOLUTION: In a semiconductor integrated circuit 3, a positioning mark 9 is formed in an empty region 14 where a fuse 5 is not formed. This positioning mark 9 is separately formed from an actual fuse 5 and also has a shape capable of confirming readily and visually a center in X and Y directions, and further is formed in the same layer as the fuse 5. Accordingly, a printing error caused when forming each wiring layer in a step of manufacturing a semiconductor wafer is removed, namely a misalignment when forming the fuse 5 and the fuse positioning mark 9 by overlapping each layer is removed, thereby enabling accurate positioning. Accordingly, a relief rate of a semiconductor integrated circuit is enhanced as fuse cutting can be accurately performed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit having a memory circuit, such as a DRAM (Dynamic Integrated Circuit).
In a random access memory), by cutting a wiring layer (hereinafter, referred to as a fuse) formed of a conductive material for switching the memory circuit, which is connected to the memory circuit determined to be defective, The present invention relates to a technique for repairing a semiconductor integrated circuit by replacing a memory circuit determined to be defective with a spare memory circuit, and more particularly to a semiconductor integrated circuit, a method for aligning a semiconductor integrated circuit in a repair laser repair device, and a laser repair. The present invention relates to a method for adjusting a laser power of an apparatus.

[0002]

2. Description of the Related Art Conventionally, a memory circuit repair technique for a semiconductor integrated circuit having a memory circuit (hereinafter referred to as a "repair technique")
(Referred to as redundancy). First, a write test of a memory circuit such as a DRAM is performed by a tester. This is a test for writing data to a memory circuit, reading the data, and checking whether the memory circuit operates normally. Thereby, fuse data is created. Fuse data refers to a memory circuit determined to be defective by a write test of the memory circuit.
In order to replace a spare memory circuit formed in the semiconductor integrated circuit with a spare memory circuit, a memory number and a fuse number for cutting a fuse connected to the spare memory circuit are described in advance. Based on the created fuse data, the fuse is cut by a laser repair device. Here, the laser repair device is a device that cuts a fuse by irradiating a laser. By reading the fuse data created by the write test of the memory circuit into this laser repair device and cutting the fuse specified by the fuse data,
The defective memory circuit is replaced with a spare memory circuit. By replacing this memory circuit, the semiconductor integrated circuit can be rescued.

FIGS. 12 to 1 show a first conventional example.
6 will be described in detail. FIG. 12 shows a semiconductor wafer 1
FIG. 2 is a plan view in which a semiconductor integrated circuit 3 is formed. In the semiconductor integrated circuit 3, a memory circuit 4, a plurality of fuses 5, and a spare memory circuit 16 are formed. In the scribe line region 2 formed around the semiconductor integrated circuit 3, alignment marks 8a and 8b used for positioning the semiconductor wafer 1 are formed in the X and Y directions, respectively.

A monitor screen 2 for wafer observation shown in FIG.
Reference numeral 2 is mounted on a laser repair device and has a function of displaying an image of the surface of the wafer 1 captured by a monitor camera mounted in the laser repair device on a screen. Further, on the wafer observation monitor screen 22, a cross-shaped alignment confirmation line 13 in the X and Y directions as shown in the figure is displayed. The center of the intersection of the alignment check line 13 in the X and Y directions is the center position where the laser is irradiated, whereby the fuse 5 displayed on the wafer observation monitor screen 22 is moved to the center where the laser is irradiated. You can check how far it is from.

FIG. 14 is a plan view showing one example of the shape of the fuse 5. The fuse 5 is formed of a wiring layer 10, for example, aluminum, and the lower layer of the fuse 5 is formed of a non-wiring layer 11, for example, an oxide film. Fuse 5
Is surrounded by a cover film 12, the cover film 12 is removed from the upper layer of the fuse 5, and the fuse 5 is formed alone in the X direction.

In FIG. 15, a plurality of fuses 5 having the same shape are formed continuously in the Y direction. Here, a work flow for cutting a fuse using a laser repair device is shown in FIG.
It will be described based on. First, the created fuse data is read into the laser repair device by performing a write test of the memory circuit (procedure 1).

Next, the semiconductor wafer 1 corresponding to the read fuse data is transferred into the laser repair device (procedure 2). Next, the transferred semiconductor wafer 1 is aligned. Monitor screen 2 for wafer observation shown in FIG.
The alignment marks 8a and 8b shown in FIG. 12 are projected on the upper surface 2 and scanning is performed with an alignment laser of a laser repair device, and the waveforms of the alignment marks 8a and 8b are read.
The positions of a and 8b are obtained (procedure 3).

After performing the alignment in this manner, FIG.
The fuse 5 to be cut is displayed on the monitor screen 22 for wafer observation shown in FIG. At this point, the operator is to set the center of the fuse 5 to be cut and the monitor screen 22 for wafer observation in FIG.
It is confirmed whether or not the center of the alignment check line 13 displayed in the above is aligned. Here, if they do not match, the operator manually moves the stage with a stage movement controller of the laser repair device, for example, a joystick, and cuts the fuse 5 to be cut from the center of the alignment check line 13 shown in FIG. Align with the center. With this operation, the center of the alignment check line 13 is irradiated with a laser, and the fuse 5 is cut (procedure 4).

After the alignment is performed by the above-described method, for example, by pressing a start button, the laser repair device starts cutting the fuse 5 based on the fuse data (step 5). As a second conventional example, JP-A-6-232270 will be described with reference to FIGS.

FIG. 20 is a plan view in which the semiconductor integrated circuit 3 is formed on the semiconductor wafer 1. In the semiconductor integrated circuit 3, a memory circuit 4, a plurality of fuses 5, and a spare memory circuit 16 are formed. In addition, the semiconductor integrated circuit 3
The scribe line region 2 formed around the laser target 7 has a laser target 7 used as a reference position at the time of laser irradiation.
a to 7d are formed. Separately from this, a recognition pattern 6 for positioning the laser targets 7a to 7d is formed on the semiconductor integrated circuit 3.

FIGS. 21 to 24 are views showing an embodiment of the recognition pattern 6. FIG. The recognition pattern 6 is formed so that the step between the convex portion and the concave portion becomes clear. here,
It is assumed that the recognition pattern 6 is formed by the wiring layer 10 and the non-wiring layer 11. Next, a work flow in the laser repair device will be described with reference to FIG.

First, by performing a write test of the memory circuit, the created fuse data is read into the laser repair device (procedure 1). Next, the semiconductor wafer 1 corresponding to the read fuse data is transported into the laser repair device (procedure 2). Next, the surface of the corresponding semiconductor integrated circuit 3 of the semiconductor wafer 1 is projected on the wafer observation monitor screen 22 of FIG. 25 by the monitor camera mounted in the laser repair device. Then, a characteristic recognition pattern 6 formed separately from the fuse 5
(FIGS. 21 to 24) are recognized by the laser repair device, and the position of the recognition pattern 6 on the semiconductor integrated circuit 3 is calculated in the laser repair device (procedure 3).

Then, by calculating the position from the recognition pattern 6, the laser target 7 shown in FIG.
The positions of a to 7d are searched. This laser target 7a
When ~ 7d is recognized, the position of the fuse 5 is determined based on this position (procedure 4). Then, after the alignment using the laser targets 7a to 7d is completed,
The fuse 5 connected to the memory circuit 4 determined to be defective is cut by laser irradiation based on the fuse data read into the laser repair device. Thereby, the spare memory circuit 1 formed in the semiconductor integrated circuit 3
6 is replaced. By repeating this work sequence, the semiconductor integrated circuit 3
Can be repaired.

[0014]

However, in the above-mentioned prior art, there is a drawback that the accuracy of positioning cannot be improved. The reason will be described using the first conventional example. In the case of performing the work using the memory circuit repair technique in the semiconductor integrated circuit 3 in the first conventional example 1, after the alignment is performed, the fuse 5 is displayed on the wafer observation monitor screen 22 shown in FIG. The operator manually adjusts the fuse 5 to the alignment check line 13 displayed on the wafer observation monitor screen 22 to perform the alignment.

However, as shown in FIG.
A plurality of fuses having the same shape are continuously formed in the Y direction, and the fuses tend to be reduced year by year as the size of the semiconductor integrated circuit 3 is reduced. It is difficult to match 13 This will be described in detail below with reference to FIGS. FIG. 17 is a plan view of one example of the arrangement of the fuses. FIG.
Similarly to the fuse 5, the fuse 5 is formed of a wiring layer 10, for example, aluminum.
1, for example, formed of an oxide film. The periphery of the fuse 5 is surrounded by a cover film 12, and the cover film 12 is removed from the upper layer of the fuse 5. The fuse 5 is Y
The fuses 5 having the same shape are continuously arranged in the direction. Here, each of the fuses 5 is replaced with a fuse 5a to
5d.

The fuses 5a to 5d have a fuse width h, a distance from the center of the fuse width of the adjacent fuse to the center, ie, a fuse pitch 1, a fuse interval i, and a fuse center position 18 to a cutting center position. The displacement amount when the displacement is up to 17, that is, the cutting center displacement amount is m. FIG. 19 is a plan view of an example in which fuses are arranged in a different direction from FIG.

For example, when the fuse width h of the fuses 5a and 5b is 1.0 μm and the fuse pitch 1 is 2.0 μm, the maximum allowable error of the design value in the semiconductor wafer manufacturing process is ± 0.2 μm, and the laser repair device When both errors of ± 0.5 μm occur in the same direction as the maximum permissible error in the accuracy of the fuse, the fuse cutting center position 17 adjusted by the fuse design coordinate value is the fuse center position 18 on the actual product.
± 0.7 μm (cutting center deviation amount m). Therefore, assuming that the fuse to be actually cut is 5a, the cutting position is shifted by 0.2 [mu] m outside the fuse 5a. Since the fuse pitch 1 is 2.0 μm, the interval i between the fuses 5 a and 5 b is 1.0 μm and 0.2 μm.
If it is shifted by μm, the fuse 5 adjacent to the fuse 5a
From b, the location of 0.8 μm is indicated as the fuse center position. In this case, the operator visually recognizes whether the fuse to be actually cut is the fuse 5a or the fuse 5b, and adjusts the fuse to the center position of the fuse 5a to be cut manually by using a monitor mounted in the laser repair device. Since the lens magnification of the camera is low, the observation magnification of the wafer observation monitor screen 22 as shown in FIG. Therefore, in the case where the above-described positional deviation occurs, 1/10 μm
The task is quite difficult, since we have to tell the difference in units.

Further, the fuses 5 designed on the semiconductor integrated circuit may be arranged in both the X and Y directions as shown in FIGS. Here, the fuses 5a and 5b in FIGS. 17 and 19 will be described as an example. As for the fuses 5a continuously arranged in the Y direction as shown in FIG.
Fuse width h is 1.0 μm and fuse pitch l is 2.0
When the fuse 5a is blown, the center of the alignment check line 13 in FIG.
Although the center of the fuse 5a has a rectangular shape in the X direction that is long in the X direction, the center of the alignment confirmation line 13 in FIG.
8 is shifted, the fuse center position 1 in the X direction
It is difficult for an operator to visually adjust 8 accurately. In this case, if the operator shifts the fuse 5a by 2.0 μm in the X direction from the fuse center position 18, the distance between the fuse center position 18 of the fuse 5a and the cutting position 17, that is, the cutting center shift amount m is 2. 0 μm. At this position, the fuse 5a is blown, and then, as shown in FIG.
When the fuses successively arranged in the X direction are to be cut, when the fuse 5a in FIG.
The position shifted by m is cut. In this case, since the cutting center shift amount m is 2.0 μm, the fuse 5a is set at 2.
Since the position shifted by 0 μm becomes the cutting position 17, the cutting position 17 becomes the center of the fuse 5b and the fuse 5a should be cut, but the adjacent fuse 5b will be cut.

As in the above example, the fuse 5a having the same shape is used.
Fuse group in which ~ 5d are continuously arranged in a narrow pitch;
In the case where the fuse exists in the X and Y directions, if the fuse is shifted from the fuse center position 18, the fuse 5
It is difficult to accurately match the center position 18 of a.
Further, it can be said that the fuse disconnection described above also occurs in the second conventional example.

FIG. 27 is a sectional view showing a part of the semiconductor integrated circuit 3 in which the fuse 5 and the recognition pattern 6 are formed. The lowermost layer 19 is a silicon substrate. A non-wiring layer 11, for example, an oxide film is formed thereon.
Next, a wiring layer 10 to be the fuse 5, for example, aluminum is formed. Recognition patterns 6 are formed on wiring layers 10 other than wiring layer 10 of fuse 5.
The recognition pattern 6 corresponds to the wiring layer 1 on which the fuse 5 is formed.
It may be formed on either the upper part or the lower part of 0. A non-wiring layer 11 is formed around and above the fuse 5 and the recognition pattern 6.

In this example, when performing the operation using the redundancy, the operator allows the laser repair device to recognize the recognition pattern 6 shown in FIG. 20 so that the laser targets 7a to 7d shown in FIG. The position can be obtained, and more accurate positioning can be performed. However, FIG.
7, the wiring layer 10 on which the recognition pattern 6 is formed
And the wiring layer 10 on which the fuses 5 are formed, the misalignment occurs due to a printing error with the layer on which the fuses 5 are formed when the recognition pattern 6 is formed in the manufacturing process of the semiconductor wafer 1. Is recognized and used as a reference value.
An error of about 2 μm may occur.

The timing of using the recognition pattern 6 in this example is based on the sequence shown in FIG. 25.
This is performed before the alignment of the laser targets 7a to 7d shown in FIG. Therefore, when an error of a maximum of ± 0.5 μm occurs during alignment as a precision error of the laser repair device, an error of a maximum of ± 0.7 μm is obtained by adding a maximum allowable error of ± 0.2 μm in a manufacturing process of the semiconductor wafer 1. Occurs, which has an effect when the fuse is blown. When such an error has occurred, the sequence shown in FIG. 26 does not require the intervention of an operator. Since the fuse is cut, it is impossible to accurately irradiate the laser to the center position of the fuse, and the fuse is left uncut due to a positional deviation. Therefore, the defective memory circuit 4 is not replaced with the spare memory circuit 16, and the memory circuit of the semiconductor integrated circuit cannot be repaired.

[0023]

SUMMARY OF THE INVENTION It is an object of the present invention to improve the above-mentioned drawbacks of the prior art, and to cut a fuse in an operation using a memory circuit repair technique in a semiconductor integrated circuit. In a semiconductor integrated circuit and a laser repair device, a fuse alignment mark is formed in a vacant area of a semiconductor integrated circuit, and the fuse alignment mark is used to cut a fuse by using alignment. The present invention provides a method for aligning a semiconductor integrated circuit.

Another object of the present invention is to provide a method for adjusting a laser power of a laser repair device using a fuse alignment mark.

[0025]

SUMMARY OF THE INVENTION The present invention basically employs the following technical configuration to achieve the above object. That is, as a first aspect of the semiconductor integrated circuit of the present invention, in a semiconductor integrated circuit having a fuse alignment mark for a laser repair device, the fuse alignment mark is provided on a wiring layer of the semiconductor integrated circuit. According to a second aspect, in addition to the above-described configuration, the fuse alignment mark is formed of the same material as the fuse. A display means for indicating the interval between fuses provided in a wiring layer of the semiconductor integrated circuit is formed on the fuse alignment mark;
According to a fourth aspect, the display means is a semiconductor integrated circuit, wherein the display means indicates an interval between fuses arranged in the X direction and the Y direction at right angles to each other. A semiconductor integrated circuit, wherein a scale for adjusting laser power of a laser repair device is formed on the fuse alignment mark.

According to another aspect of the method for aligning a semiconductor integrated circuit in a laser repair device of the present invention, a fuse alignment mark formed on a wiring layer of the semiconductor integrated circuit is used. It is a method of aligning the semiconductor integrated circuit in the laser repair device, characterized by performing the position within, as an aspect of the method of adjusting the laser power of the laser repair device of the present invention,
A method for adjusting the laser power of a laser repair device, wherein a mark for adjusting laser power is formed on a wiring layer of a semiconductor integrated circuit, and the laser power of the laser repair device is adjusted using the mark.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor integrated circuit according to the present invention employs the above-described technical configuration.
When adjusting the position of the fuse using the laser repair device, the fuse alignment mark is provided in the wiring layer, so that the center of the fuse position can be detected with high accuracy, and the yield is improved.

In the method for adjusting laser power of a laser repair device according to the present invention, a mark for adjusting laser power is formed on a wiring layer of a semiconductor integrated circuit, and the laser power of the laser repair device is adjusted using the mark. The fuse is cut with the appropriate laser power,
Therefore, the yield is improved. Further, since the laser power adjustment mark also serves as a fuse alignment mark of a semiconductor integrated circuit in a laser repair device, it is possible to adjust the fuse position and adjust the laser power in a narrow area.

[0029]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Specific examples of a semiconductor integrated circuit, a method of aligning a semiconductor integrated circuit in a laser repair device, and a method of adjusting a laser power of the laser repair device according to the present invention will be described below in detail with reference to the drawings. . 1 to 11
FIG. 1 shows that in a semiconductor integrated circuit having a fuse alignment mark for a laser repair device according to the present invention, the fuse alignment mark 9 is provided on a wiring layer 10 of the semiconductor integrated circuit; Numeral 9 indicates that the fuse is formed of the same material as the fuse, and the fuse alignment mark 9 is provided with a display means 30 for indicating the interval between the fuses provided in the wiring layer 10 of the semiconductor integrated circuit. And the display means 30
Indicates the interval i between the fuses arranged in the X and Y directions at right angles to each other, and the fuse alignment mark 9 has a scale 40 for adjusting the laser power of the laser repair device. Is formed.

Similarly, FIGS. 1 to 11 are characterized in that a laser power adjusting mark 9 is formed on a wiring layer of a semiconductor integrated circuit, and the laser power of a laser repair device is adjusted using the mark 9. The laser power adjusting method of the laser repair device is shown, and the laser power adjusting mark 50 is a fuse alignment mark 9 of a semiconductor integrated circuit in the laser repair device.

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 2 is a plan view showing the semiconductor wafer 1 on which the semiconductor integrated circuit 3 is formed. The semiconductor integrated circuit 3 constitutes a DRAM as an example, and a memory circuit 4 is formed in a central portion of the semiconductor integrated circuit 3. In the semiconductor integrated circuit 3, separately from the memory circuit 4, a spare memory circuit 16 built in advance and a spare memory circuit 1 when the memory circuit 4 becomes defective.
A plurality of fuses 5 for switching to 6 are provided. The fuse 5 is connected to the defective memory circuit 4 based on fuse data created when a write test to the memory circuit 4 is performed.
Is replaced with a spare memory circuit 16 by cutting the laser beam with a laser of a laser repair device. A scribe line region 2 is formed around the semiconductor integrated circuit 3, and alignment marks 8a and 8b for positioning the semiconductor wafer 1 are formed on the scribe line region 2.

FIG. 1 is a plan view showing a part of the semiconductor integrated circuit 3 including the fuse alignment mark 9. The semiconductor integrated circuit 3 is formed on the semiconductor wafer 1, and a fuse alignment mark 9 is formed in an empty area 14 in the semiconductor integrated circuit 3. The fuse alignment mark 9 is formed of a wiring layer 10, for example, aluminum, and a non-wiring layer 11, for example, an oxide film. )
To form a cross, and the periphery thereof is surrounded by a non-wiring layer 11.

FIG. 3 is a sectional view showing a part of the semiconductor integrated circuit 3 on which the fuse 5 and the fuse alignment mark 9 are formed. The lowermost layer 19 is formed of a silicon substrate.
A non-wiring layer 11, for example, an oxide film is formed thereon, and then a wiring layer 10, which becomes the fuse 5 and the fuse alignment mark 9, for example, aluminum is formed. A non-wiring layer 11 is formed around and above the wiring layer 10.

FIG. 4 is a plan view showing a design example of the fuse alignment mark 9. The shape of the fuse alignment mark 9 is
The wiring layer 10 is crossed in the X direction and the Y direction (horizontal and vertical) to form a cross shape, and the wiring 10 is arranged like a rectangular block at an interval of a fuse interval i on an extension thereof. At this time, the width of the rectangular block is the same as the fuse width h. As a result, the fuse alignment mark 9 is divided into a central cross block 9a and a surrounding rectangular block 9b. The periphery of the fuse alignment mark 9 is formed so as to be surrounded by the non-wiring layer 11.

FIG. 5 is a plan view showing a design example of the fuse alignment mark 9 similarly to the above. The fuse alignment mark 9 is formed of the wiring layer 10 and the non-wiring layer 11, and has a shape in the X direction and the Y direction (horizontal and vertical) of the wiring layer 10.
Are formed so as to be perpendicular to each other, and the periphery thereof is surrounded by the non-wiring layer 11.

The monitor screen 22 for wafer observation shown in FIG.
Is mounted on a laser repair device, and has a function of displaying on the screen an image of the surface of the wafer 1 captured by a monitor camera mounted in the laser repair device. Further, on the wafer observation monitor screen 22, a cross-shaped alignment check line 13 in the X and Y directions as shown in the figure is displayed. The center of the intersection of X and Y of the alignment check line 13 is the center position where the laser is irradiated, whereby the fuse 5 displayed in the wafer observation monitor screen 22 is moved from the center where the laser is irradiated. You can check how much it is off.

The semiconductor integrated circuit 3 has a fuse 5
The alignment mark 9 is formed in the empty area 14 where no is formed. This alignment mark 9 is
The fuse is formed separately from the actual fuse 5 and has a characteristic shape that allows the center in the X and Y directions to be easily confirmed by visual inspection. Further, in the sectional view of the semiconductor integrated circuit 3 in FIG. As shown, it is formed in the same layer as the fuse 5.

This is because the alignment mark 9 is formed in the same layer as the fuse 5 so that the semiconductor wafer 1
In the manufacturing process described above, there is no printing error caused when forming each wiring layer, that is, a deviation at the time of forming the fuse 5 and the fuse alignment mark 9 due to the superposition of the layers, thereby enabling accurate alignment. . The operation using the memory circuit repair technique for the semiconductor integrated circuit 3 on which the fuse alignment mark 9 is formed is performed in the procedure shown in FIG. The procedure will be described below.

First, the created fuse data is read into the laser repair device by a write test to the memory circuit 4 (procedure 1). Next, the semiconductor wafer 1 is transferred into the laser repair device (procedure 2). Then, alignment is performed using the alignment marks 8a and 8b for alignment of the semiconductor wafer 1 formed in the scribe line region 2 shown in FIG. 2 (procedure 3). Next, after the alignment is performed, the semiconductor integrated circuit 3 including the defective memory circuit 4 is displayed on the monitor screen 22 for wafer observation by the monitor camera mounted in the laser repair device. The fuse alignment mark 9 of the circuit 3 is displayed. When the operator aligns the center of the alignment check line 13 on the wafer observation monitor screen 22 of FIG. 6 with the center of the fuse alignment mark 9, the amount of movement, that is, the amount of deviation is calculated by the computer equipped with the laser repair device. (Step 4).

Finally, the actual semiconductor wafer 1
Is compared with a fuse design coordinate value previously held in the laser repair apparatus, an accurate position is calculated, and the fuse is cut. According to the sequence shown in FIG. 11, the value obtained here is held as an offset value in the computer in the laser repair device, and thereafter, is reflected on the semiconductor wafer 1 that is continuously cut, and the accurate value on the semiconductor wafer 1 is obtained. The fuse 5 can be cut.

As described above, according to the present invention, since the deviation amount of the laser repair device itself and the error at the time of alignment are finally absorbed and registered as the offset value in the laser repair device, the deviation at the time of fuse cutting is minimized. Is possible. Next, a specific example of the method for adjusting the laser power of the laser repair device according to the present invention will be described with reference to FIGS.
This will be described in detail with reference to FIG.

The fuse alignment mark 9 formed on the semiconductor integrated circuit 3 on the semiconductor wafer 1 is shaped as shown in FIG. The fuse alignment mark 9 has the same wiring layer and the same material as that of the fuse 5, and the wiring width h in the X direction and the Y direction of the fuse alignment mark 9 is the same as the wiring width h of the fuse 5, and the center of the fuse 5 A cross-shaped block,
The distance from the surrounding rectangular block is determined by the semiconductor integrated circuit 3
And the width of the rectangular block is the same as the fuse width h.

A notch 31 for indicating the interval i between the fuses 5 is provided in the cross block portion 9a of the fuse alignment mark 9, and is formed in a rectangular shape having an interval i with the side 31a of the notch 31. A display unit 30 for displaying the fuse interval i is formed by the block unit 9b. In the fuse cutting operation shown in FIG. 11, fuse data is created by a write test of the memory circuit 4. At this time, the semiconductor integrated circuit 3 including the defective memory circuit 4, that is, a row for replacing the memory circuit is prepared. For the semiconductor integrated circuit 3 to be manufactured, fuse data is created so as to use the fuse alignment mark 9 of the present invention. After reading the generated fuse data into the laser repair device, the operator transports the semiconductor wafer 1 into the laser repair device and performs alignment. After the alignment, the surface of the semiconductor integrated circuit 3 is projected on the wafer observation monitor screen 22 shown in FIG. 6 by the monitor camera attached to the laser repair device, and the fuse alignment mark 9 is projected. The operator manually moves the alignment confirmation line 13 on the wafer observation monitor screen 22 and the center of the fuse alignment mark 9 displayed on the wafer observation monitor screen 22 with a semiconductor wafer movement controller mounted on the laser repair device, for example, a joystick. To cut the fuse alignment mark 9. From this, fuse alignment mark 9
The actual position of the fuse alignment mark 9 on the semiconductor wafer 1 is compared with the design coordinate value of the fuse alignment mark 9 previously held in the laser repair device from the deviation amount, and an accurate position is calculated. , The actual position of the fuse 5 is also calculated, and the fuse is cut.

At this time, since the fuse alignment mark 9 is formed of the same layer, the same material, and the same wiring width as the actual fuse 5, the laser is irradiated before the actual fuse 5 is cut. It is possible to confirm the size of the cutting trace and whether the laser energy value is appropriate with the cutting trace.
For example, as shown in FIG. 7, when only the cross block portion 9a of the fuse alignment mark 9 is cut and no damage is found on the base, it can be determined that both the energy and the beam size are optimal.

Next, as shown in FIG. 8, in the case where the cross block 9a of the fuse alignment mark 9 and the surrounding rectangular block 9b separated by the distance i between the fuses are cut, even the actual fuse is adjacent. Since the fuse to be blown is blown, the beam size is too large, and it can be determined that the beam size needs to be reduced. Also, as shown in FIG.
If only the center of “a” is cut and remains uncut, the beam size is small or the energy value is small, so even the actual fuse may be left uncut. Therefore, the beam size may be increased or the energy may be increased. It can be determined that it is necessary to increase it.

If the center of the cross block 9a of the fuse alignment mark 9 is damaged as shown in FIG. 10, the energy is so large that even the actual fuse will damage the base at the time of cutting. Therefore, it can be determined that the energy needs to be reduced. As described above, the fuse alignment mark 9 is formed by the protrusion 9c of the cross block 9a.
And a distance i between the side 31a of the notch 31 and the side 31a.
Since the mark for laser power adjustment is formed with the block portion 9b provided with the fuse, the position of the actual fuse 5 and the actual position of the fuse 5 are previously held in the laser repair device by using the fuse alignment mark 9 based on the deviation amount. Comparing the design coordinate values of the fuse 5 which has been performed, calculating an accurate position, cutting the fuse 5, and energy for cutting the fuse,
In addition, final confirmation of the beam size condition can be performed at the same time.

As described above, the present invention has been described with reference to specific examples. In the present invention, the fuse alignment mark 9 of the present invention is provided in the empty area 14 of the semiconductor integrated circuit 3 where the fuse 5 is not formed, and is used. This allows the operator to easily visually align the minute deviation after the alignment of the semiconductor wafer 1 and to set the fuse alignment mark 9 on the same layer, the same material, and the same wiring width as the fuse 5. Thus, it is possible to confirm the cutting trace before cutting the fuse 5 with a laser.

In the above description, the application of the present invention has been described with respect to the technique of repairing a memory circuit in a semiconductor integrated circuit in a laser repair device of a semiconductor integrated circuit (mainly a DRAM) having a memory, but the present invention is not limited to this. Not,
Since the fuse alignment mark of the present invention has a unique shape even in a semiconductor integrated circuit, it may be used as a mark for image recognition that can be easily confirmed. For example, there is a device that performs alignment by image recognition, such as a prober used in a wafer inspection process.

[0049]

As described above, the present invention has the following advantages. The operator can easily and visually position the fuse on the semiconductor integrated circuit, and can cut the fuse accurately, thereby improving the rescue rate of the semiconductor integrated circuit. In addition, the laser can be irradiated before the actual fuse is cut to confirm the trace of the cut, thereby reducing the number of re-execution steps due to insufficient laser irradiation, over-irradiating, and increasing the beam size to adjacent fuses. It is possible to prevent the cause of replacement failure due to damage beforehand, which is effective in reducing the number of steps and improving the rescue rate of the semiconductor integrated circuit.

[Brief description of the drawings]

FIG. 1 is a plan view showing a part of a semiconductor integrated circuit on which a fuse alignment mark of the present invention is formed.

FIG. 2 is a plan view of a semiconductor wafer including an integrated circuit on which a fuse alignment mark of the present invention is formed.

FIG. 3 is a sectional view showing a main part of a semiconductor integrated circuit in which a fuse alignment mark of the present invention and a fuse are formed.

FIG. 4 is a plan view showing a design example of a fuse alignment mark of the present invention.

FIG. 5 is a plan view showing a design example of a fuse alignment mark of the present invention.

FIG. 6 is a diagram showing a registration check line 13 on a wafer observation monitor screen 22 which is a display unit of the laser repair device.

FIG. 7 is a plan view showing a shape after cutting a fuse alignment mark according to the present invention.

FIG. 8 is a plan view showing a shape after cutting a fuse alignment mark of the present invention.

FIG. 9 is a plan view showing the shape of the fuse alignment mark of the present invention after cutting.

FIG. 10 is a plan view showing the shape of the fuse alignment mark of the present invention after cutting.

FIG. 11 is a flowchart showing a work flow of a laser repair apparatus using a semiconductor wafer having a fuse alignment mark formed thereon according to the present invention.

FIG. 12 is a plan view of a semiconductor wafer including a conventional semiconductor integrated circuit.

FIG. 13 is a view showing a display example of a monitor screen for wafer observation which is a display unit of a conventional laser repair device.

FIG. 14 is a plan view showing a conventional fuse shape example.

FIG. 15 is a plan view showing a conventional fuse arrangement example.

FIG. 16 is a flowchart showing a work flow of a laser repair device according to a conventional technique.

FIG. 17 is a diagram for explaining occurrence of a shift at the time of cutting in the fuse of FIG. 15;

FIG. 18 is a diagram for explaining occurrence of displacement at the time of cutting in fuses 5a to 5d that are continuous in the Y direction.

FIG. 19 is a diagram for explaining occurrence of displacement at the time of cutting in fuses 5a to 5d that are continuous in the X direction.

FIG. 20 is a plan view of a semiconductor wafer including a semiconductor integrated circuit on which a recognition pattern is formed according to the related art.

FIG. 21 is a plan view showing an example of a conventional recognition pattern.

FIG. 22 is a plan view showing an example of a conventional recognition pattern.

FIG. 23 is a plan view showing an example of a conventional recognition pattern.

FIG. 24 is a plan view showing an example of a conventional recognition pattern.

FIG. 25 is a diagram showing an example of a monitor screen for wafer observation (having a registration check line) which is a display unit of a conventional laser repair device.

FIG. 26 is a flowchart showing a work flow in a conventional laser repair device.

27 is a cross-sectional view showing a part of the semiconductor integrated circuit in which the recognition pattern and the fuse of FIG. 20 are formed.

[Explanation of symbols]

Reference Signs List 1 semiconductor wafer 2 scribe line area 3 semiconductor integrated circuit 4 memory circuit 5a, 5b wiring layer (fuse) formed of conductive material 6 recognition pattern 7a, 7d laser target 8a, 8b alignment mark 9 fuse alignment mark 10 wiring layer Reference Signs List 11 non-wiring layer 12 cover film 13 alignment check line 14 free area 15 center point 16 spare memory circuit 17 cutting center position 18 fuse center position 19 silicon substrate 20 cutting trace 21 base damage 22 monitor screen for wafer observation h fuse width i Between fuses j Fuse length at opening l Fuse pitch m Cutting center deviation

Claims (8)

[Claims] 1. A semiconductor integrated circuit having a fuse alignment mark for a laser repair device, wherein the fuse alignment mark is provided on a wiring layer of the semiconductor integrated circuit. 2. The semiconductor integrated circuit according to claim 1, wherein said fuse alignment mark is formed of the same material as the fuse. 3. The semiconductor integrated circuit according to claim 1, wherein said fuse alignment mark has display means for indicating an interval between fuses provided in a wiring layer of said semiconductor integrated circuit. 4. The semiconductor integrated circuit according to claim 3, wherein said display means indicates an interval between fuses arranged in an X direction and a Y direction which are perpendicular to each other. 5. The semiconductor integrated circuit according to claim 1, wherein a scale for adjusting a laser power of the laser repair device is formed in the fuse alignment mark. 6. A method for aligning a semiconductor integrated circuit in a laser repair device, comprising: using a fuse alignment mark formed in a wiring layer of the semiconductor integrated circuit, the position of the semiconductor integrated circuit in the laser repair device. A method of aligning a semiconductor integrated circuit in a laser repair device, wherein the alignment is performed. 7. A method for adjusting laser power of a laser repair device, wherein a mark for adjusting laser power is formed on a wiring layer of a semiconductor integrated circuit, and the laser power of the laser repair device is adjusted using the mark. 8. A method for adjusting a laser power of a laser repair device according to claim 7, wherein the laser power adjustment mark is a fuse alignment mark of a semiconductor integrated circuit in the laser repair device.